EP1998367B1 - Procédé de fabrication d'une tranche SOI - Google Patents

Procédé de fabrication d'une tranche SOI Download PDF

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Publication number
EP1998367B1
EP1998367B1 EP08009379.2A EP08009379A EP1998367B1 EP 1998367 B1 EP1998367 B1 EP 1998367B1 EP 08009379 A EP08009379 A EP 08009379A EP 1998367 B1 EP1998367 B1 EP 1998367B1
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EP
European Patent Office
Prior art keywords
wafer
etching
soi
stage
film thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP08009379.2A
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German (de)
English (en)
Other versions
EP1998367A2 (fr
EP1998367A3 (fr
Inventor
Shoji Akiyama
Yoshihiro Kubota
Atsuo Ito
Koichi Tanaka
Makoto Kawai
Yuuji Tobisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
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Shin Etsu Chemical Co Ltd
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Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of EP1998367A2 publication Critical patent/EP1998367A2/fr
Publication of EP1998367A3 publication Critical patent/EP1998367A3/fr
Application granted granted Critical
Publication of EP1998367B1 publication Critical patent/EP1998367B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Claims (4)

  1. Procédé de fabrication d'une tranche de SOI (30) comprenant au moins :
    une étape de préparation d'une tranche de manipulation (20) et d'une tranche donneuse (10) constituée d'un substrat de silicium, dans lequel la tranche de manipulation est une quelconque parmi une tranche de quartz, une tranche de verre, une tranche d'alumine (saphir), une tranche de SiC, et une tranche de nitrure d'aluminium ;
    une étape d'implantation d'ions pour implanter au moins un parmi un ion hydrogène et un ion de gaz rare dans la tranche donneuse pour former une couche à implantation ionique (11) ;
    une étape de liaison pour lier une surface à implantation ionique de la tranche donneuse (12) à une surface de liaison de la tranche de manipulation (22) ;
    une étape de décollage pour décoller la tranche donneuse au niveau de la couche à implantation ionique (11) pour réduire une épaisseur de film de la tranche donneuse, donnant ainsi une couche de SOI (31) ; et
    une étape de gravure pour graver la tranche de SOI pour réduire une épaisseur de la tranche de SOI, dans lequel l'étape de gravure inclut :
    une étape d'exécution de gravure grossière comme gravure humide ;
    un étape de mesure d'une distribution d'épaisseur de film de la couche de SOI après la gravure grossière ; et
    une étape d'exécution de gravure précise comme gravure sèche sur la base de la distribution d'épaisseur de film mesurée de la couche de SOI mise en oeuvre par un procédé PACE ou un procédé GCIB, dans lequel un enlèvement par gravure à l'étape de gravure précise est fixé plus petit qu'un enlèvement par gravure à l'étape de gravure grossière dans une plage de 10 nm à 100 nm.
  2. Procédé de fabrication d'une tranche de SOI selon la revendication 1, un substrat de silicium comme la tranche donneuse est une tranche de silicium monocristallin ou une tranche de silicium monocristallin ayant un film d'oxyde de silicium formé sur une surface de celle-ci.
  3. Procédé de fabrication d'une tranche de SOI selon la revendication 1 ou 2, dans lequel la gravure humide est exécutée en utilisant un agent de gravure contenant au moins un parmi KOH, NH4OH, une solution mixte de NH4OH+H2O2, NaOH, CsOH, EDP, TMAH, et de l'hydrazine.
  4. Procédé de fabrication d'une tranche de SOI selon l'une quelconque des revendications 1 à 3, dans lequel la gravure sèche est exécutée en utilisant un gaz contenant au moins un parmi SF6, NF3, CF4, CHF3, HBr, Cl2, O2 et H2.
EP08009379.2A 2007-05-30 2008-05-21 Procédé de fabrication d'une tranche SOI Active EP1998367B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007144075A JP5415676B2 (ja) 2007-05-30 2007-05-30 Ｓｏｉウェーハの製造方法

Publications (3)

Publication Number Publication Date
EP1998367A2 EP1998367A2 (fr) 2008-12-03
EP1998367A3 EP1998367A3 (fr) 2010-08-11
EP1998367B1 true EP1998367B1 (fr) 2015-04-15

Family

ID=39734966

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08009379.2A Active EP1998367B1 (fr) 2007-05-30 2008-05-21 Procédé de fabrication d'une tranche SOI

Country Status (5)

Country Link
US (1) US9064929B2 (fr)
EP (1) EP1998367B1 (fr)
JP (1) JP5415676B2 (fr)
KR (1) KR101469282B1 (fr)
TW (1) TWI462221B (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5277975B2 (ja) * 2009-01-14 2013-08-28 株式会社村田製作所 複合基板の製造方法
SG163481A1 (en) * 2009-01-21 2010-08-30 Semiconductor Energy Lab Method for manufacturing soi substrate and semiconductor device
JP5643488B2 (ja) * 2009-04-28 2014-12-17 信越化学工業株式会社 低応力膜を備えたｓｏｉウェーハの製造方法
JP2010278341A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 貼り合わせｓｏｓ基板
US20110269295A1 (en) * 2010-04-30 2011-11-03 Hopper Peter J Method of Forming a Semiconductor Wafer that Provides Galvanic Isolation
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
FR2978605B1 (fr) * 2011-07-28 2015-10-16 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
JP5664592B2 (ja) * 2012-04-26 2015-02-04 信越半導体株式会社 貼り合わせウェーハの製造方法
CN102832105B (zh) * 2012-09-10 2015-08-19 豪威科技(上海)有限公司 晶圆减薄方法
TWI629753B (zh) * 2013-04-26 2018-07-11 日本碍子股份有限公司 半導體用複合基板之操作基板
JP6213046B2 (ja) 2013-08-21 2017-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6152829B2 (ja) * 2014-06-17 2017-06-28 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
DE102014114683B4 (de) * 2014-10-09 2016-08-04 Infineon Technologies Ag Verfahren zur herstellung eines halbleiter-wafers mit einer niedrigen konzentration von interstitiellem sauerstoff
EP3234987B1 (fr) * 2014-12-19 2020-09-23 GlobalWafers Co., Ltd. Systèmes et procédés destinés à effectuer des processus de lissage épitaxial sur des structures semi-conductrices
JP6525046B1 (ja) * 2017-12-19 2019-06-05 株式会社Sumco 半導体ウェーハの製造方法
KR101969679B1 (ko) * 2018-07-27 2019-04-16 한양대학교 산학협력단 Soi 웨이퍼와 열처리 공정을 이용한 박막 형성 및 전사 방법
US10658474B2 (en) * 2018-08-14 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thin semiconductor-on-insulator (SOI) substrates

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JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
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Also Published As

Publication number Publication date
JP5415676B2 (ja) 2014-02-12
TW200915480A (en) 2009-04-01
US9064929B2 (en) 2015-06-23
US20080299742A1 (en) 2008-12-04
KR20080106038A (ko) 2008-12-04
JP2008300571A (ja) 2008-12-11
KR101469282B1 (ko) 2014-12-04
EP1998367A2 (fr) 2008-12-03
TWI462221B (zh) 2014-11-21
EP1998367A3 (fr) 2010-08-11

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