JP6152829B2 - Soiウェーハの製造方法 - Google Patents
Soiウェーハの製造方法 Download PDFInfo
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- JP6152829B2 JP6152829B2 JP2014124046A JP2014124046A JP6152829B2 JP 6152829 B2 JP6152829 B2 JP 6152829B2 JP 2014124046 A JP2014124046 A JP 2014124046A JP 2014124046 A JP2014124046 A JP 2014124046A JP 6152829 B2 JP6152829 B2 JP 6152829B2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
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- H01L21/02057—Cleaning during device manufacture
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
- H01L21/67057—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing with the semiconductor substrates being dipped in baths or vessels
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Description
(a)酸化性ガス雰囲気下で熱処理を行って、前記SOI層の表面に熱酸化膜を形成する工程と、
(b)前記熱酸化膜を形成した後のSOI層の膜厚を測定する工程と、
(c)前記SOI層に対してエッチング性を有する洗浄液に前記SOI層を浸漬することを含むバッチ式洗浄を行う工程であって、前記SOI層のエッチング量を、前記工程(b)で測定されたSOI層の膜厚に応じて調整することによって、前記バッチ式洗浄によるエッチング後のSOI層の膜厚を、前記ターゲット値より厚く調整するバッチ式洗浄工程と、
(d)前記バッチ式洗浄工程後のSOI層の膜厚を測定する工程と、
(e)前記SOI層に対してエッチング性を有する洗浄液に前記SOI層を浸漬することを含む枚葉式洗浄を行う工程であって、前記SOI層のエッチング量を、前記工程(d)で測定されたSOI層の膜厚に応じて調整することによって、前記枚葉式洗浄によるエッチング後のSOI層の膜厚を、前記ターゲット値に調整する枚葉式洗浄工程と
を有し、前記工程(a)の後かつ前記工程(b)の前、又は前記工程(b)の後かつ前記工程(c)の前に、前記工程(a)で形成した熱酸化膜を除去することを特徴とするSOIウェーハの製造方法を提供する。
イオン注入剥離法によって作製された直径300mmのSOIウェーハ(SOI膜厚150nm)を46枚用意し、これらを2つのバッチ式洗浄カセット(カセット−01、02)に分けて本発明を実施した例を表1に示す。
比較例1では、酸化後の酸化膜除去と膜厚調整洗浄をバッチ式洗浄機のみで行った。比較例1における酸化膜除去洗浄とバッチ式膜厚調整洗浄は、同時に酸化処理したウェーハ22枚を1つのバッチとして同一カセット(カセット−01)に纏めるバッチ処理で行った。具体的には、まず、工程(b)までは実施例と同様にして行った。次に、15%HF含有水溶液を用いたバッチ式洗浄を100秒行い、熱酸化膜を除去した後、SOI層の表面を乾燥させることなく、SOI層をSC1溶液に浸漬するバッチ式洗浄を180秒行った。SC1条件(組成,液温)は、実施例と同様の条件とした。
また、比較例2では、酸化後の酸化膜除去とSOI膜厚調整洗浄を枚葉式洗浄機のみで行った。まず、工程(b)までは実施例と同様にして行った。次に、SiO2(熱酸化膜)を除去した。次に、SOI層をSC1溶液に浸漬する枚葉式洗浄を、それぞれのSOIウェーハごとに、160〜200秒行った。SC1条件(組成,液温)は、実施例と同様の条件とした。
Claims (5)
- 絶縁層上にSOI層が形成されたSOIウェーハの前記SOI層を所定の厚さまで減少させ、前記SOI層の膜厚をターゲット値とするSOIウェーハの製造方法であって、少なくとも、
(a)酸化性ガス雰囲気下で熱処理を行って、前記SOI層の表面に熱酸化膜を形成する工程と、
(b)前記熱酸化膜を形成した後のSOI層の膜厚を測定する工程と、
(c)前記SOI層に対してエッチング性を有する洗浄液に前記SOI層を浸漬することを含むバッチ式洗浄を行う工程であって、前記SOI層のエッチング量を、前記工程(b)で測定されたSOI層の膜厚に応じて調整することによって、前記バッチ式洗浄によるエッチング後のSOI層の膜厚を、前記ターゲット値より厚く調整するバッチ式洗浄工程と、
(d)前記バッチ式洗浄工程後のSOI層の膜厚を測定する工程と、
(e)前記SOI層に対してエッチング性を有する洗浄液に前記SOI層を浸漬することを含む枚葉式洗浄を行う工程であって、前記SOI層のエッチング量を、前記工程(d)で測定されたSOI層の膜厚に応じて調整することによって、前記枚葉式洗浄によるエッチング後のSOI層の膜厚を、前記ターゲット値に調整する枚葉式洗浄工程と
を有し、前記工程(a)の後かつ前記工程(b)の前、又は前記工程(b)の後かつ前記工程(c)の前に、前記工程(a)で形成した熱酸化膜を除去することを特徴とするSOIウェーハの製造方法。 - 前記工程(b)の膜厚の測定を、前記工程(a)で形成した熱酸化膜を除去せずに行い、前記工程(b)の後かつ前記工程(c)の前に、前記工程(a)で形成した熱酸化膜を、HF含有水溶液を用い、バッチ式洗浄で除去した後、前記工程(c)のバッチ式洗浄を、前記熱酸化膜を除去した後のSOI層の表面を乾燥させることなく、前記SOI層に対してエッチング性を有する洗浄液に前記SOI層を浸漬することにより行うことを特徴とする請求項1に記載のSOIウェーハの製造方法。
- 前記SOIウェーハを、少なくとも、イオン注入により形成された微小気泡層を有するボンドウェーハと支持基板となるベースウェーハとを接合する工程と、前記微小気泡層を境界としてボンドウェーハを剥離してベースウェーハ上に薄膜を形成する工程とを有するイオン注入剥離法によって作製されたSOIウェーハとすることを特徴とする請求項1又は請求項2に記載のSOIウェーハの製造方法。
- 前記バッチ式洗浄及び前記枚葉式洗浄を、SC1溶液に浸漬することを含む洗浄とすることを特徴とする請求項1から請求項3のいずれか1項に記載のSOIウェーハの製造方法。
- 前記工程(c)のバッチ式洗浄後のSOI層の膜厚のバッチ内平均値を、前記ターゲット値と前記ターゲット値+0.5nmの間に制御することを特徴とする請求項1から請求項4のいずれか1項に記載のSOIウェーハの製造方法。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014124046A JP6152829B2 (ja) | 2014-06-17 | 2014-06-17 | Soiウェーハの製造方法 |
SG11201609805PA SG11201609805PA (en) | 2014-06-17 | 2015-04-13 | Method for manufacturing soi wafer |
EP15809306.2A EP3159911B1 (en) | 2014-06-17 | 2015-04-13 | Method for manufacturing soi wafer |
KR1020167035257A KR102241303B1 (ko) | 2014-06-17 | 2015-04-13 | Soi웨이퍼의 제조방법 |
US15/313,473 US9953860B2 (en) | 2014-06-17 | 2015-04-13 | Method of manufacturing SOI wafer |
CN201580027234.8A CN106415784B (zh) | 2014-06-17 | 2015-04-13 | 绝缘体上硅晶圆的制造方法 |
PCT/JP2015/002042 WO2015194079A1 (ja) | 2014-06-17 | 2015-04-13 | Soiウェーハの製造方法 |
TW104112236A TWI611568B (zh) | 2014-06-17 | 2015-04-16 | 絕緣體上矽晶圓的製造方法 |
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JP2014124046A JP6152829B2 (ja) | 2014-06-17 | 2014-06-17 | Soiウェーハの製造方法 |
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JP6152829B2 true JP6152829B2 (ja) | 2017-06-28 |
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US (1) | US9953860B2 (ja) |
EP (1) | EP3159911B1 (ja) |
JP (1) | JP6152829B2 (ja) |
KR (1) | KR102241303B1 (ja) |
CN (1) | CN106415784B (ja) |
SG (1) | SG11201609805PA (ja) |
TW (1) | TWI611568B (ja) |
WO (1) | WO2015194079A1 (ja) |
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WO2021241044A1 (ja) | 2020-05-26 | 2021-12-02 | 信越半導体株式会社 | Soiウェーハの製造方法 |
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JP3319397B2 (ja) | 1998-07-07 | 2002-08-26 | 信越半導体株式会社 | 半導体製造装置およびこれを用いたエピタキシャルウェーハの製造方法 |
WO2003009386A1 (fr) * | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP4509488B2 (ja) * | 2003-04-02 | 2010-07-21 | 株式会社Sumco | 貼り合わせ基板の製造方法 |
JP2004349493A (ja) * | 2003-05-22 | 2004-12-09 | Canon Inc | 膜厚調整装置及びsoi基板の製造方法 |
JP2007266059A (ja) | 2006-03-27 | 2007-10-11 | Sumco Corp | Simoxウェーハの製造方法 |
JP5415676B2 (ja) * | 2007-05-30 | 2014-02-12 | 信越化学工業株式会社 | Soiウェーハの製造方法 |
JP2009054837A (ja) * | 2007-08-28 | 2009-03-12 | Sumco Corp | Simoxウェーハ製造方法およびsimoxウェーハ |
JP5320954B2 (ja) * | 2008-10-03 | 2013-10-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
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- 2015-04-13 US US15/313,473 patent/US9953860B2/en active Active
- 2015-04-13 EP EP15809306.2A patent/EP3159911B1/en active Active
- 2015-04-13 KR KR1020167035257A patent/KR102241303B1/ko active IP Right Grant
- 2015-04-13 WO PCT/JP2015/002042 patent/WO2015194079A1/ja active Application Filing
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Publication number | Publication date |
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CN106415784A (zh) | 2017-02-15 |
CN106415784B (zh) | 2019-06-07 |
KR102241303B1 (ko) | 2021-04-16 |
TW201601296A (zh) | 2016-01-01 |
US20170200634A1 (en) | 2017-07-13 |
EP3159911B1 (en) | 2021-06-09 |
US9953860B2 (en) | 2018-04-24 |
KR20170018336A (ko) | 2017-02-17 |
WO2015194079A1 (ja) | 2015-12-23 |
EP3159911A4 (en) | 2018-02-28 |
SG11201609805PA (en) | 2016-12-29 |
TWI611568B (zh) | 2018-01-11 |
JP2016004890A (ja) | 2016-01-12 |
EP3159911A1 (en) | 2017-04-26 |
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