EP1968190B1 - Schaltung zur Entdeckung von Eingabesignalen - Google Patents

Schaltung zur Entdeckung von Eingabesignalen Download PDF

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Publication number
EP1968190B1
EP1968190B1 EP08004204A EP08004204A EP1968190B1 EP 1968190 B1 EP1968190 B1 EP 1968190B1 EP 08004204 A EP08004204 A EP 08004204A EP 08004204 A EP08004204 A EP 08004204A EP 1968190 B1 EP1968190 B1 EP 1968190B1
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EP
European Patent Office
Prior art keywords
differential
input signal
transistor
circuit
voltage
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EP08004204A
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English (en)
French (fr)
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EP1968190A2 (de
EP1968190A3 (de
Inventor
Norihiro Saitou
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of EP1968190A3 publication Critical patent/EP1968190A3/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

Definitions

  • the present invention relates to an input signal detecting circuit for detecting a differential signal.
  • a circuit for recognizing reception of a signal when the signal is transmitted and received (hereinafter, to be referred to as an input signal detecting circuit) is standardized in the physical layers in many interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect), SATA (Serial AT Attachment), and SAS (Serial Attached Small Computer System Interface). Also, each of the standards defines a value of the input signal amplitude. In order that such standardized circuits operate normally, it is important that an input signal has an amplitude within a range in the standard, independently of the use environment of the circuit.
  • an interface unit uses an analog circuit
  • an analog circuit uses a differential comparing circuit.
  • the differential comparing circuit uses elements such as transistors and resistors.
  • the transistor has a transfer conductance [S] (hereinafter, to be referred to as gm), and a voltage amplification factor of the differential comparing circuit is determined based on a load resistance and gm.
  • a dielectric constant of the gate oxide film is represented as ⁇ ox
  • the vacuum dielectric constant is represented as ⁇ o
  • a mobility of a carrier is represented as ⁇
  • a capacitance C ox of the gate oxide film is represented by the following equation (1).
  • the transfer conductance gm varies in accordance with the temperature because the product ⁇ and the current I ds are included.
  • Such variation of gm dependent on temperature has influence on the output amplitude of the differential comparing circuit. That is, the output amplitude of the differential comparing circuit is increased or decreased on the basis of the temperature.
  • the input signal detecting circuit to which the differential comparing circuit is applied has a temperature condition under which the input signal within the range of the standard cannot be detected.
  • FIG. 1 shows the configuration of the input signal detecting circuit disclosed in the first conventional example.
  • the conventional input signal detecting circuit includes differential comparing circuits CMP7 and CMP8 and an exclusive OR EOR3.
  • an N-channel MOS (Metal Oxide Semiconductor) transistor and a P-channel MOS transistor are referred to as an NMOS transistor and a PMOS transistor, respectively.
  • the differential comparing circuit CMP7 includes NMOS transistors Mn9 and Mn10 as a differential pair, resistors R9 and R10 serving as load resistances, and a constant current source Ib7.
  • the differential comparing circuit CMP8 includes NMOS transistors Mn11 and Mn12 as a differential pair, resistors R11 and R12 serving as load resistances, a resistor Rb1 to supply an offset voltage Voff1, and a constant current source Ib8.
  • One end of the constant current source Ib8 is connected to the sources of the NMOS transistors Mn11 and Mn12, and one end of the resistor R11 is connected to the drain of the NMOS transistor Mn11, and one end of the resistor R12 is connected to the drain of the NMOS transistor Mn12.
  • the other end of the resistor R11 and the other end of the resistor R12 are connected to one end of the resistor Rb1, and the other end of the resistor Rb1 is connected to the power supply voltage VDD.
  • the other end of the constant current source Ib8 is grounded.
  • the gates of the NMOS transistors Mn9 and Mn11 are connected to an input terminal to which an input signal SINP is supplied, and the gates of the NMOS transistors Mn10 and Mn12 are connected to an input terminal to which an input signal SINN is supplied.
  • the NMOS transistor Mn9 is connected to the resistor R9 through a node N9.
  • the NMOS transistor Mn10 is connected to the resistor R10 through a node N10.
  • the NMOS transistor Mn11 is connected to the resistor R11 through a node N11.
  • the NMOS transistor Mn12 is connected to the resistor R12 through a node N12.
  • a differential output signal CMP7out which is composed of an output signal CMP7outP as a positive (normal) phase signal and an output signal CMP7outN as a negative (opposite) phase signal, is outputted from the nodes N9 and N10.
  • a differential output signal CMP8out which is composed of an output signal CMP8outP as a positive (normal) phase signal and an output signal CMP8outN as a negative (opposite) phase signal, is outputted from the nodes N11 and N12.
  • the exclusive OR EOR3 is connected to the nodes N9 to N12 and outputs a signal of an exclusive OR result between the differential output signal CMP7out and the differential output signal CMP8out (an output signal Sout (binary signals Sout3P and Sout3N)).
  • FIGS. 2A, 2B and 2C are timing charts of the operation signals at nodes in the input signal detecting circuit according to the conventional example.
  • a differential input signal SIN is composed of the input signal SINP as the positive phase signal, and the input signal SINN as the negative phase signal, and is supplied to the input signal detecting circuit. It is supposed that the detection of the differential input signal SIN is not required between a time t1 and a time t5, and the detection of the differential input signal SIN is required between the time t5 and a time t9.
  • the input signal SINP is supplied to the NMOS transistors Mn9 and Mn11, and the input signal SINN is supplied to the NMOS transistors Mn10 and Mn12.
  • a load resistance of the differential comparing circuit is assumed to be RL and a voltage (amplitude) of the input signal to the differential comparing circuit is assumed to be V in , a voltage (amplitude) V o of the output signal from the differential comparing circuit is represented by the following equation (3).
  • V o gm ⁇ RL ⁇ V in
  • the voltages of the input signals SINP and SINN are assumed to be SINP and SINN, respectively
  • the voltages of the output signals CMP7outP, CMP7outN, CMP8outP and CMP8outN are assumed to be CMP7outP, CMP7outN, CMP8outP and CMP8outN, respectively
  • the resistances of the resistors R9, R10, R11 and R12 as the load resistances are assumed to be R9, R10, R11 and R12, respectively.
  • the equation (3) is represented by the following equations (4) and (5).
  • the input signal SIN (SINP - SINN) is amplified for the values of gm ⁇ R9 and gm ⁇ R11 as the voltage amplification factors of the differential comparing circuits CMP7 and CMP8 and is outputted as the differential output signals CMP7out (CMP7outP - CMP7outN) and CMP8out (CMP8outP - CMP8outN) of the differential comparing circuits CMP7 and CMP8 (refer to FIG. 2B ).
  • DC operation voltages Vo7P and Vo7N of the output signals CMP7outP and CMP7outN of the differential comparing circuit CMP7 are determined from the following equations (6) and (7) by using the power supply voltage VDD, the resistors R9 and R10 and the constant current source Ib7 (a current value Ib7).
  • V o ⁇ 7 ⁇ P VDD - R ⁇ 10 ⁇ Id ⁇ 7 2
  • V o ⁇ 7 ⁇ N VDD - R ⁇ 9 ⁇ Id ⁇ 7 2
  • DC operation voltages Vo8P and Vo8N of the output signals CMP8outP and CMP8outN of the differential comparing circuit CMP8 are calculated by using the power supply voltage VDD and the resistors Rb1 (the resistance value Rb1), R11 and R12.
  • the power supply voltage VDD, the resistors R9 and R10, R11 and R12, and the constant current sources Ib7 and Ib8 are the same power source, the same resistor and the same current source, the DC operation voltages Vo8P and Vo8N and the DC operation voltages Vo7P and Vo7N are separated by an offset voltage off1 indicated in the following equation (8).
  • Voff ⁇ 1 R b ⁇ 1 ⁇ I b ⁇ 8
  • the amplitude (SINP - SINN) of the differential input signal SIN is small between the time t1 and the time t5.
  • the differential output signal CMP7out of the differential comparing circuit CMP7 and the differential output signal CMP8out of the differential comparing circuit CMP8 do not cross.
  • the differential output signal CMP7out and the differential output signal CMP8out cross.
  • the exclusive OR EOR3 compares the output signal CMP7outP and the output signal CMP8outN, and determines to be a logic level "1", if the output signal CMP7outP is higher in voltage than the output signal CMP8outN, and determines to be a logic level "0" if the output signal CMP7outP is lower than the output signal CMP8outN.
  • the exclusive OR EOR3 compares the output signal CMP7outN and the output signal CMP8outP, and determines to be the logic level "1" if the output signal CMP8outP is higher in voltage than the output signal CMP7outN, and determines to be the logic level "0” if the output signal CMP8outP is lower in voltage than the output signal CMP7outN.
  • the input signal detecting circuit can detect the differential input signal SIN so that the differential output signals CMP7out and CMP8out having amplitudes equal to or higher than the offset voltage Voff1 are obtained. That is, a threshold voltage (hereinafter, to be referred to as a detection threshold voltage) of the differential input signal SIN is set in accordance with the offset voltage Voff1 determined by the equation (8) such that the differential input signal SIN can be detected by the input signal detecting circuit according to the conventional example.
  • a threshold voltage hereinafter, to be referred to as a detection threshold voltage
  • the amplitudes of the differential output signals CMP7out and CMP8out are determined in accordance with the transfer conductance gm whose value varies dependently on temperature. For this reason, even when the detectable differential input signal SIN, (having the amplitude equal to or higher than the detection threshold voltage is supplied, there would be a case that the differential output signals CMP7out and CMP8out having the correct amplitude cannot be outputted due to the influence of a peripheral temperature.
  • the equations (4) and (5) described in the operation of the above conventional circuit indicate a relation between the input and output of the differential comparing circuit.
  • the temperature variation in the transfer conductance gm results from the current flowing through the transistor and the product ⁇ of the capacitance C ox of the gate oxide film and the carrier mobility ⁇ .
  • a temperature variation amount of the transfer conductance gm dependent on the temperature variation in the carrier mobility ⁇ is great, which causes a severe variation in the voltage amplification factor represented by the equations (9) and (10).
  • the offset voltage Voff1 is assumed to be stable for the temperature
  • the detection threshold voltage of the differential input signal SIN can be also assumed to be stable.
  • FIGS. 3A and 3B are diagrams showing the waveforms of the differential output signals 7out and 8out when the differential input signal SIN having an amplitude of the detection threshold voltage or more is supplied to the input signal detecting circuit according to the conventional example.
  • FIGS. 3A and 3B show the waveforms when the peripheral temperature is -25 °C and 75 °C.
  • the DC operation voltages Vo7P (Vo7N) and Vo8P (Vo8N) in the differential comparing circuits CMP7 and CM8 are 800 mV and 760 mV, respectively, and they does not almost vary.
  • the offset voltage is 40 mV, which is constant independently of the temperature.
  • the amplitudes of the differential output signals CMP7out and CMP8out are 50 mV at the temperature of -25 °C, they decrease to 35 mV at the temperature of 75 °C.
  • the differential output signal 7out and the differential output signal 8out are separated by 5 mV, and the differential input signal SIN cannot be detected. In this way, there would be a case that the originally detectable input signal cannot be detected because the peripheral temperature increases.
  • a second example of a conventional input signal detecting circuit, according to the preamble of claim 1 is disclosed in US 2006/0033535 A1 .
  • the input signal detecting circuit for detecting a very small signal is strongly required to provide a high sensibility and simultaneously avoid erroneous detection.
  • a detection voltage range namely, an allowable range of the detection threshold voltage (the amplitude) becomes narrow. For this reason, it is necessary to reduce or remove detection irregularity caused based on peripheral temperature, as mentioned above.
  • an object of the present invention is to provide an input signal detecting circuit which can detect a differential signal with a small amplitude in a high accuracy while preventing detection irregularity.
  • an input signal detecting circuit having the features of claim 1 is provided.
  • the input signal detecting circuit of the present invention it is possible to detect an input signal of the detection threshold voltage or more without receiving the influence of a peripheral environment. Also, the voltage of the detectable differential input signal can be selected from a plurality of detection threshold voltages.
  • the input signal detecting circuit according to a first embodiment of the present invention will be described below with reference to FIGS. 4 to 9 .
  • FIG. 4 is a circuit diagram showing the configuration of the input signal detecting circuit according to the first embodiment of the present invention.
  • the input signal detecting circuit in the first embodiment is a circuit for detecting the amplitude of a differential input signal SIN, which is composed of an input signal SINP as a positive (normal) phase signal, and an input signal SINN as a negative (opposite) phase signal, and converting the differential input signal SIN into a binary signal.
  • the input signal detecting circuit according to the first embodiment includes differential comparing circuits CMP7 and CMP80, a differential exclusive OR circuit EOR3 connected to the output ends thereof, and a temperature compensating circuit C1 for controlling an offset voltage Voff1. That is, the input signal detecting circuit according to the first embodiment includes the differential comparing circuit CMP80 instead of the differential comparing circuit CMP8 in the input signal detecting circuit in the conventional example and further includes the temperature compensating circuit C1.
  • the differential comparing circuit CMP80 in this embodiment includes an offset adjusting circuit A1, instead of the resistor Rb1 provided to adjust the offset in the conventional example. Also, the temperature compensating circuit C1 outputs a control signal with a voltage Vc corresponding to a peripheral temperature, to the offset adjusting circuit A1 and controls the offset voltage Voff1.
  • the offset adjusting circuit A1 includes a PMOS transistor Mp1 and an operational amplifier AMP1 and gives the offset voltage Voff1 to a differential output signal CMP8out.
  • the source of the PMOS transistor Mp1 is connected to a power supply voltage VDD, and the drain thereof is commonly connected through a node N13 to one of sets of ends of resistors R11 and R12.
  • the output terminal of the operational amplifier AMP1 is connected to the gate of the PMOS transistor Mp1, and a negative input terminal is connected to the node N13 between the drain of the PMOS transistor Mp1 and the set of ends of the resistors R11 and R12. Also, the positive input terminal of the operational amplifier AMP1 is connected to the temperature compensating circuit C1 to receive the control signal. A resistance pair of the resistors R11 and R12 and a differential pair of NMOS transistors Mn11 and Mn12 are connected between the node N13 and a grounded potential.
  • the operational amplifier AMP and the PMOS transistor Mp1 function as a voltage follower. In such configuration, a same voltage as the voltage Vc of the control signal supplied to the positive input terminal from the temperature compensating circuit C1 is supplied to the negative input terminal.
  • a voltage applied between the source and the drain in the PMOS transistor Mp1 is given as the offset voltage Voff1 to the differential output signal CMP8out. Consequently, a DC operation voltage Vo80P (Vo80N) of the differential comparing circuit CMP80 is separated from a DC operation voltage Vo70P (Vo70N) of the differential comparing circuit CMP7 for the offset voltage Voff1.
  • the differential comparing circuits CMP7 and CMP80 output the output signals CMP7outP and CMP8outP whose voltages oscillate by taking to the DC operation voltages Vo70P and Vo80P as centers.
  • the differential comparing circuits CMP7 and CMP80 output the output signals CMP7outN and CMP8outN whose voltages oscillate by taking the DC operation voltages Vo70N and Vo80N as centers.
  • description will be given under the assumption that the DC operation voltage Vo70P and the DC operation voltage Vo70N have a same value, and the DC operation voltage Vo80P and the DC operation voltage Vo80N have a same value.
  • the input signal detecting circuit detects the differential input signal SIN having an amplitude equal to or higher than a predetermined amplitude as the detection threshold amplitude. That is, in the input signal detecting circuit, the amplitude of the differential input signal SIN that can be detected is determined in accordance with the value of the offset voltage Voff1.
  • the offset voltage Voff1 is required to be set to a voltage corresponding to a desirable detection threshold amplitude. Specifically, the offset voltage Voff1 is set to a voltage equal to the amplitudes of the differential output signals CMP7out and CMP8out outputted on the basis of the differential input signal SIN of the detection threshold amplitude.
  • the offset voltage Voff1 according to the conventional example is a fixed value that is determined in accordance with the resistor Rb.
  • the offset voltage Voff1 in the first embodiment is a variable value that is determined by the offset adjusting circuit A1 that is controlled by the temperature compensating circuit C1.
  • the temperature compensating circuit C1 outputs the control signal of the voltage Vc to the offset adjusting circuit A1 and controls the offset voltage Voff1.
  • the temperature compensating circuit C1 contains NMOS transistors Mn20 and Mn21, a constant current source Ib21, and resistors R20 and R21.
  • One end of the constant current source Ib21 is connected to the power supply voltage VDD, and the other end thereof is connected to the NMOS transistor Mn20.
  • the respective gates of the NMOS transistor Mn20 and the NMOS transistor Mn21 are connected to each other, and form a current mirror circuit.
  • the gate and the drain of the NMOS transistor Mn20 are commonly connected to the other end of the constant current source Ib21, and the source is grounded through the resistor R21.
  • the drain of the NMOS transistor Mn21 is connected through the resistor R20 to the power supply voltage VDD, and the source is grounded.
  • a node N14 between the NMOS transistor Mn21 and the resistor R20 is connected to the positive input terminal of the operational amplifier AMP1. With such configuration, the voltage of the node 14 is outputted as the control signal to the offset adjusting circuit A1.
  • a current Imn21 flowing through the NMOS transistor Mn21 varies on the basis of the peripheral temperature of the input signal detecting circuit. For this reason, the voltage Vc of the node N14, namely, the control signal varies.
  • the temperature compensating circuit C1 can output the control signal that is varied on the basis of the peripheral temperature.
  • the characteristics of the respective elements in the input signal detecting circuit are preferable to be set such that the temperature characteristic of the control signal and the temperature characteristic of the amplitude of the differential output signals CMP7out and CMP8out are equal to each other.
  • the offset voltage Voff1 varies in accordance with variation of the amplitude of the differential output signals CMP7out and CMP8out dependent on temperature.
  • the resistor R21 is connected between the NMOS transistor Mn20 of the current mirror circuit and the ground.
  • a voltage Vgs21 between the source and the drain in the NMOS transistor Mn21 is a summation of a voltage generated across the resistor R21 by the constant current Ib21 and a voltage Vgs20 between the source and the drain in the NMOS transistor Mn20 after variation on the basis of the peripheral temperature.
  • Vgs20 #Vgs21, and the current Imn21 flowing through the NMOS transistor Mn21 is varied on the basis of the temperature.
  • the voltage Vc across the resistor R20 is similarly varied on the basis of the temperature.
  • the output voltage of the operational amplifier AMP1 to which the voltage Vc is supplied is varied depending on temperature.
  • the voltage at the node N13 has a value in which the variation of the operational amplifier AMP dependent on temperature is considered.
  • the operational amplifier AMP1 used in the input signal detecting circuit according to the first embodiment has a high open gain, and the output voltage can be varied on the basis of the temperature.
  • the temperature characteristic of the offset voltage Voff1 controlled by the temperature compensating circuit C1 will be described.
  • the current flowing through the drain is typically represented by the following equation (11).
  • I ds 1 2 ⁇ ⁇ ⁇ W L ⁇ V gs - V t 2
  • the voltage Vgs21 between the gate and the source in the NMOS transistor Mn21 is represented by the equation (14) (which is equal to a sum of the voltage Vgs20 between the gate and the source in the NMOS transistor Mn20 and a voltage across the resistor R21).
  • the voltage Vgs20 between the gate and the source in the NMOS transistor is represented by the equation (15) by using the equation (12). From the equations (13), (14) and (15), the current Imn21 is represented by the following equation (16).
  • V gs ⁇ 21 I b ⁇ 21 ⁇ R ⁇ 21 + V gs ⁇ 20
  • the equation (16) indicates the current Imn21 with respect to the constant current Ib21.
  • the temperature coefficient K includes the product ⁇ that is varied on the basis of the temperature.
  • the equation (16) is differentiated with respect to the temperature coefficient K, the variation amount in the current Imn21 in association with the temperature change can be determined.
  • the second item on the right side indicates a variation amount of the current Imn21 corresponding to the temperature change.
  • the actual variation amount of the current Imn21 depends on the structure of the NMOS transistor and a technique for manufacturing it.
  • FIG. 5 is a temperature characteristic diagram showing a relation between current Imn21 and temperature.
  • a curve a indicates the temperature characteristic of the current Imn21 when the resistor R21 has 0 ⁇
  • a curve h indicates the temperature characteristic of the current Imn21 in this embodiment (the resistor R21 ⁇ 0).
  • the current Imn21 according to the first embodiment is increased with the increase in the temperature.
  • the curve a indicates the characteristic of the typical current mirror circuit.
  • Vc VDD - Im ⁇ n ⁇ 21 ⁇ R ⁇ 20
  • the voltage Vc is supplied as the control signal to the positive input terminal of the operational amplifier AMP1. Since the operational amplifier AMP1 and the PMOS transistor Mp1 constitute the voltage follower circuit, the voltage Vc also appears at the negative input terminal of the operational amplifier AMP1. That is, the offset voltage Voff1 as a voltage between the drain and the source in the PMOS transistor Mp1 becomes equal to the voltage Vc.
  • FIG. 6 shows the temperature characteristic diagram showing a relation between the offset voltage Voff1 and the temperature. As mentioned above, since the current Imn21 increases with the temperature increase, the offset voltage Voff1 decreases with the temperature increase ( FIG. 6 and the equation (18)).
  • the temperature characteristic of the amplitudes of the differential output signals CMP7out and CMP8out will be described below.
  • the NMOS transistors Mn9, Mn10, Mn11 and Mn12 are the transistors having the same characteristics and the resistors R10, R11 and R12 are the resistors having the same characteristic.
  • the absolute values of the voltages of the output signals CMP7outP, CMP7outN, CMP8outP and CMP8outN become
  • the voltages of the output signals CMP7outP, CMP7outN, CMP8outP and CMP8outN are assumed to be CMP7outP, CMP7outN, CMP8outP and CMP8outN, respectively. Since the differential output signal CMP8out is similar to the differential output signal CMP7out, only the differential output signal CMP7out will be described hereinafter.
  • voltage increase rates of the differential input signal SIN and the differential output signal CMP7out in the differential comparing circuit CMP7 are represented by the equation (9).
  • the equation (2) is substituted into the transfer conductance gm of the equation (9), the equation (19) is obtained.
  • CMP7out CMP7outP - CMP7outN.
  • CMP ⁇ 7 ⁇ out SIN K ⁇ Ids 2 ⁇ R ⁇ 9
  • both of a variation amount of the offset voltage Voff1 (the voltage Vc at the node N14) dependent on temperature and a variation amount of the amplitudes of the differential output signals CMP7out and CMP8out dependent on temperature are determined on the basis of (1/2) K 1/2 .
  • the offset voltage Voff1 is required to be varied on the basis of the temperature, so as to follow the variations in the differential output signals CMP7out and CMP8out dependent on temperature. For this reason, it is preferable that the variation amount of the offset voltage Voff1 dependent on temperature and the variation amount of the amplitudes of the differential output signals CMP7out and CMP8out dependent on temperature are equal to each other.
  • the constant current source Ib21, the resistor R9 and the resistor R21 are selected to meet the equation (21).
  • the resistors R9, R10, R11 and R12 are equal in resistance value
  • the resistors R20, R21 are equal in resistance value.
  • MOS transistors having the temperature coefficients K the gate width W, the gate length L, the gate oxide film capacitance C ox and the carrier mobility ⁇
  • the variation of the amplitudes of the differential output signals CMP7out and CMP8out dependent on the peripheral temperatures in the differential comparing circuits CMP7 and CMP8 and the variation of the offset voltage Voff1 dependent on the peripheral temperature in the temperature compensating circuit C1 become equal to each other.
  • FIG. 8 shows a relation of the amplitude of the differential output signal CMP7out (CMP8out) in the input signal detecting circuit configured to meet the equation (21) and the temperature characteristic of the offset voltage Voff1.
  • the amplitudes of the differential output signals CMP7out and CMP8out are decreased with the increase in the peripheral temperature, so that the offset voltage Voff1 is also decreased by the variation amount for the decrease in the amplitudes.
  • FIGS. 3A and 3B are waveform diagrams showing the waveforms of the differential output signals 7out and 8out when the differential input signal SIN having the detectable amplitude is supplied to the input signal detecting circuit according to the first embodiment.
  • FIGS. 3a and 3B show the waveforms when the peripheral temperature is low (-25 °C) and high (75 °C).
  • a voltage difference for the offset voltage Voff1 is generated between the DC operation voltage Vo70P (Vo70N) of the differential comparing circuit CMP7 and the DC operation voltage Vo80P (Vo80N) of the differential comparing circuit CMP80.
  • the offset voltage Voff1 is 40 mV
  • the DC operation voltage Vo70P (Vo70N) is 800 mV
  • the DC operation voltage Vo80P (Vo80N) is 760 mV.
  • both of the amplitudes (the maximum amplitudes) of the differential output signals CMP7 and CMP80 are 50 mV.
  • the offset voltage Voff1 is decreased to 25 mV by 15 mV, and the DC operation voltage Vo70P (Vo70N) becomes 800 mV, and the Dc operation voltage Vo80P (Vo80N) becomes 775 mV.
  • both of the amplitudes (the maximum amplitudes) of the differential output signals CMP7 and CMP80 are 35 mV, and they are decreased by 15 mV as compared with a case of -25 °C. That is, in association with the increase in the peripheral temperature, the amplitude of the differential output signal and the offset voltage are decreased by the same variation amount.
  • the temperature characteristics of the amplitudes of the differential output signals CMP7 and CMP8 and the temperature characteristic of the offset voltage Voff1 exhibit an inversely proportional relation.
  • the differential output signals CMP7 and CMP80 are not separated unlike the conventional example, even if the temperature is increased, and they exhibit the overlapping of a certain amount (here, 10 mV). Therefore, according to the first embodiment, it is possible to detect the input differential signal SIN having the desirable amplitude without any influence of the peripheral temperature.
  • FIG. 10 is a circuit diagram showing the configuration of the input signal detecting circuit in the second embodiment.
  • the input signal detecting circuit in the second embodiment includes a switching circuit SW52 for switching the value of the control signal, instead of the temperature compensating circuit C1 of the input signal detecting circuit in the first embodiment.
  • the other components are similar to those of the first embodiment.
  • a temperature compensating circuit C2 will be described below.
  • the temperature compensating circuit C2 contains an NMOS transistor Mn52 and the switching circuit SW52, in addition to the temperature compensating circuit C1 in the first embodiment.
  • the switching circuit SW52 has two terminals, and one end thereof is connected to the gate of the NMOS transistor Mn52, and the other end is connected through a node N15 to the gate of the NMOS transistor Mn21 and the gate and drain of the NMOS transistor Mn20 and the constant current source Ib21.
  • the drain of the NMOS transistor Mn52 is connected through the node N14 and the resistor 20 to the power supply voltage VDD, and the source is grounded.
  • the gate of the NMOS transistor Mn52 is connected through the switching circuit SW52 to the node N15 (the gate and drain of the Mn20 and the constant current source Ib21) .
  • the temperature compensating circuit C2 carries out the same operation as the temperature compensating circuit C1 in the first embodiment.
  • the switching circuit SW52 is in the ON state, the NMOS transistors Mn20, MN21 and MN52 form a current mirror circuit.
  • the voltage Vc of the node N14 indicates a value different from the voltage Vc when the switching circuit SW52 is in the OFF state. That is, the input signal detecting circuit in the second embodiment can switch the voltage value of the offset voltage Voff1 to a different value by the switching circuit SW52.
  • the detection threshold voltage As a limit value (the detection threshold voltage) of the amplitude of the differential input signal SIN that can be detected by the input signal detecting circuit, only one is set. However, in the second embodiment, a desirable detection threshold voltage can be selected and used from the two kinds of the detection threshold voltages.
  • the second embodiment has the configuration in which one set of the switching circuit SW52 and the NMOS transistor Mn52 is added to the temperature compensating circuit C1.
  • the configuration may be used in which under the similar connection, a plurality of sets of switches and MOS transistors are added to the temperature compensating circuit C1. In such a case, in the input signal detecting circuit, the desirable detection threshold voltage can be selected from the plurality of detection threshold voltages.
  • the temperature compensating circuit C2 when the NMOS transistors Mn21 and Mn52 are same in structure and in size, and the switching circuit SW52 is in the ON state, it is equivalent to the configuration in which the gate width of the NMOS transistor Mn21 in the first embodiment is doubled.
  • the temperature coefficient K is proportional to the gate width.
  • the temperature compensating circuit C2 when the switching circuit SW52 is turned ON, the temperature coefficient K is made doubled as compared with the OFF case. That is, when the switching circuit SW52 is set to the ON state, the temperature compensating circuit C2 exhibits the configuration and operation that are equivalent those of the first embodiment, but the temperature coefficient K has a value determined by the NMOS transistors Mn21 and MN54 (here, two times that of the OFF state).
  • the current Imn21 is increased with the increase in the temperature coefficient K.
  • the voltage Vc of the node 14 is decreased with the increase in the temperature coefficient K. That is, when the switching circuit SW52 is turned ON, the offset voltage Voff1 has a value smaller than that of the OFF state. For this reason, the input signal detecting circuit in the second embodiment can detect the differential input signal SIN having the amplitude smaller than that of the OFF state, by turning ON the switching circuit SW52.
  • the temperature compensating circuit C2 becomes equivalent to that of the first embodiment although the temperature coefficient K is different.
  • the offset voltage Voff1 varies, following the variation dependent on temperatures of the differential output signals CMP7out and CMP8out.
  • the input signal detecting circuit in the second embodiment can select the desirable detection threshold voltage from the plurality of detection threshold voltages through the switching circuit SW52.
  • the differential comparing circuit using the NMOS transistors has been described.
  • the differential comparing circuit using the PMOS transistors may be used.
  • the offset adjusting circuit A1 contains the PMOS transistor, instead of the PMOS transistor Mp1.
  • the NMOS transistor in the temperature compensating circuit C1 (C2) may be the PMOS transistor.

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Claims (12)

  1. Eingangssignalerfassungsschaltung, die Folgendes umfasst:
    einen ersten Komparator (CMP7), der zum Verstärken eines differenziellen Eingangssignals und zum Ausgeben eines ersten differenziellen Ausgangssignals aufgebaut ist;
    einen zweiten Komparator (CMP80), der zum Verstärken des differenziellen Eingangssignals durch Verwendung eines Steuersignals und zum Ausgeben eines zweiten differenziellen Ausgangssignals aufgebaut ist; und
    eine differenziellen Exklusiv-ODER-Schaltung (EOR3), die zum Ausgeben eines resultierenden Exklusiv-ODER-Signals aus dem ersten und zweiten differenziellen Ausgangssignal aufgebaut ist,
    dadurch gekennzeichnet, dass die Eingangssignalerfassungsschaltung weiter eine Temperaturkompensationsschaltung (C1) umfasst, die zum Ausgeben des Kontrollsignals mit einer Spannung, die einer Umgebungstemperatur entspricht, aufgebaut ist und dass
    der zweite Komparator (CMP80) zum Verändern einer Betriebsgleichspannung als Reaktion auf das Steuersignal aufgebaut ist.
  2. Eingangssignalerfassungsschaltung gemäß Anspruch 1, wobei der zweite Komparator (CMP80) Folgendes umfasst:
    eine Offset-Einstellungsschaltung (A1), die dazu aufgebaut ist, dem zweiten differenziellen Ausgangssignal eine Offset-Spannung mit der als Reaktion auf das Steuersignal bestimmten Spannung zu geben.
  3. Eingangssignalerfassungsschaltung gemäß Anspruch 2, wobei die differenzielle Exklusiv-ODER-Schaltung (EOR3) das resultierende Exklusiv-ODER-Signal eines differenziellen Signals eines positiven Phasensignals des ersten differenziellen Ausgangssignals und ein entgegengesetztes Phasensignal des zweiten differenziellen Ausgangssignals und ein differenzielles Signal eines positiven Phasensignals des zweiten differenziellen Ausgangssignals und ein entgegengesetztes Phasensignal des ersten differenziellen Ausgangssignals ausgibt.
  4. Eingangssignalerfassungsschaltung gemäß Anspruch 3, wobei jede Temperaturcharakteristik einer Amplitude des ersten differenziellen Ausgangssignals und einer Amplitude des zweiten differenziellen Ausgangssignals der Temperaturcharakteristik des Spannungswerts des Steuersignals umgekehrt proportional ist.
  5. Eingangssignalerfassungsschaltung gemäß Anspruch 3 oder 4, wobei der erste Komparator (CMP7) Folgendes umfasst:
    ein erstes differenzielles Paar aus zwei Transistoren (Mn9, Mn10) die gemeinsam mit einer ersten Konstantstromquelle (IB7) verbunden sind; und
    ein erstes Lastwiderstandspaar aus Lastwiderständen (R9, R10), das mit dem ersten differenziellen Paar durch ein erstes Knotenpaar verbunden ist, von dem das erste differenzielle Ausgangssignal ausgegeben wird,
    wobei der zweite Komparator Folgendes umfasst:
    ein zweites differenzielles Paar aus zwei Transistoren (Mn11, Mn12), die gemeinsam mit einer zweiten Konstantstromquelle (IB8) verbunden sind; und
    ein zweites Lastwiderstandspaar aus Lastwiderständen (R11, R12), das mit dem zweiten differenziellen Paar durch ein zweites Knotenpaar verbunden ist, von dem das zweite differenzielle Ausgangssignal ausgegeben wird,
    wobei das zweite Lastwiderstandspaar mit einer Stromversorgung durch die Offset-Einstellungsschaltung (A1) verbunden ist und
    die Offset-Einstellungsschaltung (A1) den Strom, der durch das zweite Lastwiderstandspaar fließt, als Reaktion auf das Steuersignal, das von der Temperaturkompensationsschaltung (C1) zugeführt wird, steuert.
  6. Eingangssignalerfassungsschaltung gemäß Anspruch 5, wobei die Temperaturkompensationsschaltung (C1) eine Stromspiegelschaltung umfasst,
    die Stromspiegelschaltung einen ersten Transistor (Mn20) und einen zweiten Transistor (Mn21) umfasst, deren Gates wechselseitig miteinander verbunden sind,
    der erste Transistor (Mn20) zwischen einer dritten Konstantstromquelle (IB21) und einem ersten Widerstand (R21), der mit Erde verbunden ist, vorgesehen ist,
    der zweite Transistor (Mn21) zwischen einem zweiten Widerstand (R20), der mit der Stromversorgung verbunden ist, und Erde vorgesehen ist und
    die Temperaturkompensationsschaltung (C1) das Steuersignal aus einem Verbindungsknoten (N14) zwischen dem zweiten Transistor (Mn21) und dem zweiten Widerstand (R20) zu der Offset-Einstellungsschaltung (A1) ausgibt.
  7. Eingangssignalerfassungsschaltung gemäß einem der Ansprüche 5 bis 6, wobei die Offset-Einstellungsschaltung (A1) eine Spannungsfolgerschaltung aus einem dritten Transistor (Mp1) und einem Operationsverstärker (AMP1) umfasst,
    der dritte Transistor (Mp1) zwischen der Stromversorgung und dem zweiten Lastwiderstandspaar vorgesehen ist und
    der Operationsverstärker (AMP1) einen ersten Eingangsanschluss aufweist, der mit der Temperaturkompensationsschaltung (C1) verbunden ist, einen zweiten Eingangsanschluss, der mit einem Knoten (N13) zwischen dem zweiten Lastwiderstandspaar und dem dritten Transistor (Mp1) verbunden ist, und einen Ausgangsanschluss, der mit einem Gate des dritten Transistors (Mp1) verbunden ist.
  8. Eingangssignalerfassungsschaltung gemäß Anspruch 7, wobei der erste und zweite Transistor N-Kanal MOS-Transistoren sind und
    der dritte Transistor (Mp1) ein P-Kanal MOS-Transistor ist.
  9. Eingangssignalerfassungsschaltung gemäß Anspruch 7, wobei der erste und zweite Transistor P-Kanal MOS-Transistoren sind und
    der dritte Transistor (Mp1) ein N-Kanal MOS-Transistor ist.
  10. Eingangssignalerfassungsschaltung gemäß einem der Ansprüche 3 bis 9, wobei die Temperaturkompensationsschaltung (C1) weiter umfasst:
    eine Schaltung (SW52), die zum Wählen des Steuersignals als eines aus einer Anzahl von Signalen aufgebaut ist.
  11. Eingangssignalerfassungsschaltung gemäß einem der Ansprüche 3 bis 9, wobei die Temperaturkompensationsschaltung (C1) weiter Folgendes umfasst:
    einen vierten Transistor (Mn52), der ein Drain aufweist, das mit dem Verbindungsknoten verbunden ist, und eine Source, die mit dem Drain des zweiten Transistors (Mn21) verbunden ist; und
    eine Schaltung (SW52), die zwischen einem Drain des ersten Transistors (Mn20) und einem Gate des vierten Transistors (Mn52) vorgesehen ist.
  12. Eingangssignalerfassungsschaltung gemäß Anspruch 11, wobei ein Leitungstyp des vierten Transistors (Mn52) der gleiche ist wie jener des ersten und zweiten Transistors (Mn20, Mn21).
EP08004204A 2007-03-07 2008-03-06 Schaltung zur Entdeckung von Eingabesignalen Not-in-force EP1968190B1 (de)

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JP2013042195A (ja) * 2009-12-15 2013-02-28 Panasonic Corp インターフェイス回路
TWI421665B (zh) * 2010-06-04 2014-01-01 Univ Nat Sun Yat Sen 角落偵測電路
CN102384999B (zh) * 2010-08-30 2015-08-19 深圳艾科创新微电子有限公司 一种高速传输事件检测方法及电路
CN102176282B (zh) * 2011-01-28 2013-05-15 深圳市金宏威技术股份有限公司 用于电力载波系统的功率放大装置及电力载波系统
CN103209068B (zh) * 2012-01-12 2017-05-17 国民技术股份有限公司 一种全双工信号传输电路、信号传输方法
TW201416263A (zh) * 2012-10-18 2014-05-01 Vehicle Semiconductor Technology Company Ltd E 泛用於各式汽車發電機之信號偵測電路
CN104536510B (zh) * 2014-11-18 2016-04-20 中山大学 一种差分电压转电流电路
CN105700604B (zh) * 2014-11-28 2017-05-10 成都振芯科技股份有限公司 一种低压源耦异或逻辑电路结构
CN106357244B (zh) * 2015-07-16 2019-06-14 创意电子股份有限公司 振幅阈值检测器
CN106533400B (zh) * 2015-09-09 2019-05-10 创意电子股份有限公司 振幅阈值检测器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW282598B (de) 1995-02-22 1996-08-01 Fujitsu Ltd
US5570052A (en) 1995-06-07 1996-10-29 Philips Electronics North America Corporation Detection circuit with differential input and hysteresis proportional to the peak input voltage
US6194965B1 (en) * 1999-09-03 2001-02-27 Cypress Semiconductor Corp. Differential signal detection circuit
JP2001111421A (ja) * 1999-10-06 2001-04-20 Hitachi Ltd オフセットキャンセル回路及びａ／ｄ変換器
JP3849839B2 (ja) * 2000-03-08 2006-11-22 横河電機株式会社 増幅回路
US6486710B1 (en) * 2001-06-29 2002-11-26 Intel Corporation Differential voltage magnitude comparator
CN1599975A (zh) * 2002-10-04 2005-03-23 三菱电机株式会社 带温度补偿功能的差动放大器
JP4623556B2 (ja) * 2004-08-13 2011-02-02 ルネサスエレクトロニクス株式会社 信号検出回路

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TWI385498B (zh) 2013-02-11
JP2008219761A (ja) 2008-09-18
CN101262213A (zh) 2008-09-10
KR100932870B1 (ko) 2009-12-21
US7714621B2 (en) 2010-05-11
EP1968190A2 (de) 2008-09-10
CN101262213B (zh) 2012-05-09
EP1968190A3 (de) 2009-09-09
US20080218238A1 (en) 2008-09-11
KR20080082517A (ko) 2008-09-11
TW200848973A (en) 2008-12-16

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