Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/20—Design optimisation, verification or simulation
  • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/10—Noise analysis or noise optimisation

Definitions

• the invention relates to a method, an apparatus and a software product for assisting the design of integrated circuits, in particular on silicon.
• the electronic systems are formed either of an integrated circuit on a single silicon substrate, or consist of a system integrated electronics formed of several integrated circuits in the same housing or in different housings.
• the electronic systems are formed either of an integrated circuit on a single silicon substrate, or consist of a system integrated electronics formed of several integrated circuits in the same housing or in different housings.
• Integrated electronic systems are commonly made up of hundreds of millions of elementary components.
• design automation tools use abstract models to simulate in a simplified manner the behaviors of the components, including electrical behavior, and / or magnetic and / or thermal. This simplification is done by considering only first-order behaviors.
• these tools idealize the operation of the components. For example, during the simulation of a single-substrate integrated circuit, the silicon support is considered ideal, that is to say either perfectly insulating or perfectly conductive.
• these known tools consider the distribution grid of the power supply of the components as perfect, that is to say without resistance to the passage of electric current.
• the interference gives rise to parasites more complex than the delay or signal advance.
• the presence of interference can induce a change in the electrical potential or the frequency of the analog signals as well as a variation in the signal processing speed.
• the invention provides a method, apparatus and software tools for determining before manufacture whether an integrated circuit (s) electronic system is functioning properly.
• the method for verifying the proper functioning of electronic systems with integrated circuit (s) using analog signals consists of:
• Temporal means the noise sensitivity threshold values as a function of frequency and / or time. Such a template establishment for the various sensitive circuits, which involves the definition of thresholds, allows the automation of the method according to the invention.
• the noise-sensitive circuits can be analog circuits as well as digital circuits.
• the noise-sensitive circuits may be chosen from the group comprising: analog and RF circuits such as amplifiers, filters, oscillators, mixers, sample-and-hold circuits, memory type digital circuits, PLLs, input-output circuits and voltage references.
• analog and RF circuits such as amplifiers, filters, oscillators, mixers, sample-and-hold circuits, memory type digital circuits, PLLs, input-output circuits and voltage references.
• a circuit comprising at least one noise sensitive circuit is itself considered as a noise sensitive circuit.
• the method is such that the noise-sensitive circuits are selectable at will.
• the method makes it possible to automatically select noise-sensitive circuits and also to select noise-sensitive circuits at will that have not been selected automatically.
• All circuits of the system can, in one embodiment, be considered as noise generators.
• the noise is then modeled for all the circuits of the electronic system. Indeed, it has been found that a circuit that apparently generates a very low level noise may be the circuit that most disturbs the operation of the electronic system. This disturbance may be due to the fact that it constantly generates noise, or that it generates this noise in a frequency range which corresponds to the frequency range in which an analog circuit is sensitive. Under these conditions, it may be better not to neglect any circuit of the system.
• these noise generating circuits are selected from the group comprising: digital circuits, memory cells and analog and RF circuits such as VCOs and power amplifiers, input-output circuits.
• RF circuits such as VCOs and power amplifiers, input-output circuits.
• a circuit comprising at least one such noise generating circuit is itself considered as a noise generating circuit.
• the method starts from data relating to the topology of each circuit (which is generally available in circuit libraries). and consists in determining the position of the different circuits or blocks, determining the size and position of the various supply lines, determining the entry / exit points, and determining the noise reaching each sensitive circuit by the position of the circuits noise generators with respect to these sensitive circuits.
• the first level of the hierarchy is a component such as a transistor
• the second level of the hierarchy is an elementary function such as an AND gate or an OR gate
• the third level of the hierarchy is an assembly of elementary functions to realize a specific function, etc., the number of levels of hierarchy not being limited.
• these feed lines are identified and isolated so as to take account mainly or exclusively of these lines for determine the noise transfer.
• Another simplification consists in giving a greater weight to the noise generating circuits close to the sensitive circuits than the noise generating circuits further away from the sensitive circuits. For example, the subdivision is finer as the noise generating circuit is close to a sensitive circuit.
• no connection of a circuit model is neglected, but each of them is assigned an adjustable weight at will. For example, not only power connections, but also connections with clock signals, which provide steep rising edges at a high frequency, and large buses are taken into account.
• the weight assigned to each connection of a model is, for example, a degree of accuracy for each connection.
• a first degree of precision for a connection is to consider it as a purely resistive element
• a second degree of precision is to consider it as being both resistive and capacitive
• a third degree of precision consists in considering this connection as being both resistive, capacitive and inductive.
• the noise modeling includes the modeling of the noise generation by the various noise generating circuits, the modeling of the injection of this noise inside the substrate, the interconnections and / or the housing of the noise. electronic system circuits, as well as modeling the propagation of this noise inside the substrate, the interconnections and / or the circuit package of the electronic system.
• FIG. 1 is a diagram showing several steps of a method according to the invention
• FIG. 2 is a diagram illustrating a step of a method according to the invention
• FIG. 3 is an AND gate diagram with an indication of 4a, 4b, 4c and 4d are diagrams showing a waveform storage step for characterizing noise
• FIG. 5 is a diagram showing two AND gates
• Figure 7 is a diagram of a step of a method according to the invention.
• FIG. 1 represents the data and the software products necessary for the implementation of an exemplary embodiment of the invention.
• the type and concentration of carriers in particular, the type and concentration of carriers, the nature and thickness of the various metallization layers, the types of insulators and the housings.
• a database 12 containing the characteristic data provided by the manufacturers, namely the silicon founders and the package manufacturers.
• the silicon manufacturer provides detailed information on the density variation of impurities in the thickness of a substrate, on the thicknesses of the conductive layers and oxides disposed on the substrate.
• the characteristics useful for the system for assisting the design of integrated circuits are extracted from the base 12 by a characterization block 14 and these data extracted by the block 14 are compressed in a block 16.
• Compression means a method for decreasing the amount of information to be stored.
• the silicon smelter provides information with great accuracy on the variation of impurity density in the thickness of the substrate and the compression consists of simplifying these data by considering only discrete slices of the substrate and selecting only a single value in each slice.
• the circuit data stored in a block 22 of cell models in addition to the technological data, it is necessary to know the circuit data stored in a block 22 of cell models as well as the data relating to the geometrical arrangement of the circuit elements. compared to others, these data being stored in blocks 32 and 40.
• the cell models stored in the block 22 consist of electrical circuits formed of resistors, capacitors, inductances and transistors as well as the electrical description of the noise sources and the noise sensitivity masks.
• the data of the elementary circuits are stored in a block 24.
• noise sensitivity gauge is meant the thresholds of sensitivity to noise admissible as a function of frequency and / or time.
• the noise characteristics of its various components namely, on the one hand, the noise emitted by each circuit, and on the one hand, are determined on the other hand, the noise sensitivity of each circuit.
• To characterize the noise it is necessary to perform experiments whose description is stored in a block 26. These experiments are measurements (block 31) and / or simulations (block 30). After carrying out measurements and / or simulations, experimental signals (simulation or measurement) are obtained which are defined and stored in a block 28.
• This cell feature data is thus provided at block 22 which contains not only the circuit organization (i.e. the various circuit parts and their connections), but also the noise produced by each circuit as well as the noise sensitivity of each of these circuits.
• the following will be described, in connection with the figures, methods for characterizing the noise emitted and / or the sensitivity to the noise received by each circuit.
• the received noise sensitivity is characterized by a sensitivity mask.
• each of the sensitive circuits must be subjected to a noise below a determined threshold.
• This noise depends not only on the components of the circuit and their connections, but also their geometric positions with respect to each other.
• This segmentation of the circuits is performed in the block 34 which receives data provided by a block 32 in which one stores, on the one hand, the respective positions of the various circuits and, on the other hand, the positions of the connection lines.
• a block 40 is provided in which the assembly geometrical data is provided in the housing, in particular the position of the circuits relative to each other. to others inside the case.
• Block 40 also contains the relative position data of integrated circuits when using a set of integrated circuits in different housings.
• the circuit data retained in block 34 are stored by a block 42; the segmentation thus carried out makes it possible to select, on the basis of the circuit models stored in the block 22, the physical elements of the noise generating circuits and the noise sensitive elements.
• a block 50 completely characterizes the parasitic interferences between the circuits. These characterizations or models contain in particular the transfer function of the entire system that carries parasites. These characterizations are stored in a block 52.
• a block 54 receives data from the block 22 and the block 52 to calculate the distribution of noise from the generating elements of such parasites.
• This noise distribution is stored in a block 56.
• This noise distribution is used in a block 58 which traverses the set of noise-sensitive circuits and compares the sensitivity mask of each of these sensitive circuits with the noise to which each of these circuits is subject, given the position of each of them. If none of the noise-sensitive elements receives noise greater than its size, then a signal 60 is generated to run the integrated electronic system. In the opposite case, a fault signal 62 is produced from this integrated electronic system.
• Design Systems provides SubstrateStorm software. As an example, again, mention may be made of the software tool Space of the Dutch University DeIft.
• the models represent both the components and the manufacturing parameters, including the substrate, the housing and the interconnections. These are formed of a superposition of layers of metal and insulation.
• the model of an interconnection is a resistor and an inductor and the insulator between two metal layers forms a capacitor.
• the company's Assura software tool For example, the company's Assura software tool
• Cadence Design Systems characterizes interconnections as inductors, resistors and capacitors. Mention may also be made of the "Caliber xRC” and “Caliber xL” tools from Mentor Graphics.
• the Space software tool mentioned above also makes it possible to characterize the interconnections. However, this tool is limited to resistors and capacitors. It can be completed by a tool for extracting inductances and mutual inductances such as the Fast Henry software tool from the American University MIT. This tool is described in Mr. Kamon's article “Fast Henry: A Multiple Accelerated 3D Inductance Extraction Program," IEEE Transactions MTT Volume 42, No. 9, pages 1750-1758, 1994.
• housings Electrical models of housings are generally provided by the manufacturers of such housings. You can also use a software called HFSS Ansoft American company.
• the noise is carried mainly by the supply lines.
• these supply lines are identified and isolated and only these lines, as well as the substrate and the case, are used to form the electrical model 50 which will characterize the noise generating elements or parasitic elements.
• the electrical model 50 which will characterize the noise generating elements or parasitic elements.
• the elements actually sensitive to noise are identified.
• the distance separating the noise generating elements from the noise sensitive elements is taken into account.
• the identification of the noise generating elements is performed for each power supply.
• the two-dimensional space is subdivided, for example by a square-mesh network whose pitch increases as a function of the distance to the noise-sensitive elements, and in each mesh, a simplification is made to retain only an equivalent contribution of all the noise generating circuits in this mesh.
• a) All electrical elements between two identical nodes are considered to be in parallel.
• each supply network is connected to the substrate by a single physical object. This virtual physical object has a determined shape, for example square, whose area is the sum of the areas of real physical objects found in each circuit of the mesh. Its position corresponds to the center of gravity of all surfaces considered.
• the software product is such that it makes it possible to take all the nodes into account, but assigning a different weight to each node. For example, if you want to consider only the power nodes, then we will assign a zero weight to the interconnections with the clock signals and buses. It is also possible to indicate a degree of precision on the electrical model for each node; for example, the model can neglect the inductances at each node. As yet another example, the interconnections with the clock signals - which provide steep ascent or descent fronts at a high frequency - and the large buses are selected.
• Cell models 22 serve mainly to identify and / or characterize the noise generating elements.
• FIG. 3 shows an AND gate having two inputs A and B with a power supply supplying a voltage V dd at the input, and an intensity i dd i and at the output a voltage V ss and a current i ss .
• this AND gate provides its output signal on a load which is, for example, a capacitor.
• the AND gate finally injects a current i SUb directly into the semiconductor substrate.
• the values idd ⁇ iss and i SU b are determined for example by simulation, as represented by the diagrams of FIGS. 4b, 4c and 4d.
• the current i ss is the consumed current that differs from the current supplied i dd since this supplied current i dd is derived to the load as well as to the substrate i SU b-
• the various waveforms corresponding to the various transitions are stored in a base large capacity data.
• the input current of the power is the sum of input currents ii and i 3 of each of the gates and likewise the output current i ss is the sum of the output currents i 2 and i 4 on each of the gates.
• the waveforms of currents i dd and i ss are sums of stored values (FIGS. 4b and 4c).
• Cell models 22 are also used to identify and characterize the sensitivity mask of noise-sensitive cells.
• the noise sensitivity threshold of the corresponding cell for each frequency we mean the noise sensitivity threshold of the corresponding cell for each frequency.
• the noise sensitivity values are considered as a function of time, this time being determined by a reference such as a clock. For example, in the case of an analog / digital converter, the noise sensitivity is greatest during the sampling of the analog signal.
• each circuit model is either a noise generator, a noise sensitivity "template", or a combination of both.
• noise is characterized by waveforms at connection points connected to noise sensitive circuits.
• the characterization method of the noise distribution just described is not always satisfactory. Indeed, it requires a relatively complex analog simulation.
• This analog simulation is of the "Spice” type, for example proposed in a "3f5" version on the website of the American University of Berkeley.
• Commercial simulators such as "Specter” software distributed by Cadence Design Systems can also be mentioned.
• This method also has the disadvantage of requiring a simplified model that only takes into account the coupling by the substrate between noise generating circuits and noise sensitive circuits.
• the invention provides two improvements to the known technique, these improvements that can be used independently of one another.
• the first improvement is to use a more realistic model of circuit, as represented by a simplified example in Figure 6.
• the circuit model takes into account not only the coupling by the substrate but also the coupling by the interconnections and by the housing.
• the substrate 78 supports a power input pad 82 connected by a wire 80 to a tab 84 of the housing.
• the connecting wire 80 is modeled by inductance and resistance.
• interconnections in the form of metal lines 86 for example for the supply network V dd -
• These metal lines 86 feed a circuit 88 made on the substrate 78, this circuit 88 being for example of digital type with an access 98.
• the wires 86 are represented by inductances and resistors as well as capacitors 90 with other wires 92. In this model, mutual inductances between wires 80, 86 and 94 are taken into account. is also connected to a tab 96 of the housing. The accuracy of the model can be improved by including the capacitances between the wires 86 and the substrate 78, as well as the coupling capacitors between wires 80 and 94 and between tabs 84 and 96.
• the pads 84, 96 and the access 98 to the circuit 88 and access 102 to a circuit 104 on the substrate constitute interconnection points to the power supplies and to the noise sensitive circuits.
• the circuits 88 and 104 are connected to the substrate. It is known to characterize circuits comprising multiplicities of nodes, namely, the nodes relating to the power supplies 82, 84, 98, 102, 96, as well as the nodes Ni, N 2 which constitute the nodes of a network.
• the laws of Kirchoff make it possible to connect together the various values of current intensities in the network.
• each waveform 120 (FIG 7), which is represented by a current signal or voltage varying as a function of time, is divided into time windows of a determined duration, for example 100 picoseconds. , and in each of these time windows, for example t 0 (FIG. 7), the minimum value m and the maximum value M of the signal as well as the minimum time t m of rise and the minimum time of descent t d of the signals are determined. .
• These four parameters m, M, t m , t d are characteristics of a triangular signal.
• This signal can easily be represented by its Fourier transform or the like, such as a Laplace transform.
• the number of parameters of these transforms is also restricted.
• the method according to the invention makes it possible to determine whether an integrated electronic system using analog signals, functions correctly before it is physically realized, with databases having reasonable memory capacities and with relatively short calculation times.
• the invention also extends to the electronic circuit or the software capable of implementing the method described above.

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