WO2008007026A2 - Procédé de modélisation de l'activité de commutation d'un circuit numérique - Google Patents
Procédé de modélisation de l'activité de commutation d'un circuit numérique Download PDFInfo
- Publication number
- WO2008007026A2 WO2008007026A2 PCT/FR2007/051646 FR2007051646W WO2008007026A2 WO 2008007026 A2 WO2008007026 A2 WO 2008007026A2 FR 2007051646 W FR2007051646 W FR 2007051646W WO 2008007026 A2 WO2008007026 A2 WO 2008007026A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cells
- circuit
- switching
- software
- time
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Definitions
- the present invention relates to a method for modeling the switching activity of a digital circuit.
- the invention is an alternative to the exhaustive or pseudo-exhaustive simulation for determining the switching activity of a circuit, the invention not being a simulation method.
- the invention makes it possible to quickly calculate a switching activity model of a circuit, without it being necessary to know precisely the architecture of this circuit.
- the invention finds a particularly advantageous application in the field of software for the control of signal integrity in a mixed electronic system comprising analog circuits and digital circuits.
- electronic systems include integrated circuits on a single silicon block, or on several silicon substrates in the same housing, as well as the assembly of components (integrated or not) on a printed circuit.
- a step consists in checking the integrity of the signals on a system, that is to say to establish a precise map of the noise observable inside the system in order to know if certain circuits sensitive to the noise will work or not.
- noise generating circuits the aggressors
- noise sensitive circuits the victims
- all the circuits of the system can be considered as noise generators (aggressors).
- the noise generating circuits it is preferable to choose the noise generating circuits in the group comprising: digital circuits, memory cells, analog and radio-frequency (RF) circuits, such as VCOs (Voltage Controlled Oscillator), amplifiers power, and input-output circuits.
- RF radio-frequency
- digital circuits tend to generate noise when switching their input signals.
- a circuit comprising at least one noise generating circuit is itself considered as a noise generating circuit.
- the noise-sensitive circuits are selected from the group consisting of: analog and RF circuits, such as amplifiers, filters, oscillators, mixers, sample-and-hold devices, memory type digital circuits, phase, input-output circuits and voltage references.
- analog and RF circuits such as amplifiers, filters, oscillators, mixers, sample-and-hold devices, memory type digital circuits, phase, input-output circuits and voltage references.
- a circuit comprising at least one noise-sensitive circuit is itself considered to be sensitive to noise.
- the noise generated by the aggressors spreads to the victims through the substrates on which the circuits, the metal interconnections and the housings are integrated. This noise tends to degrade the performance of the victims.
- noise is any signal generated by an aggressor block that has an unwanted influence on the victims.
- the noise observable in such systems is related to the switching activity of the digital cells that make up the digital circuits of the system. In design assistance software, it may therefore be necessary to know the switching activity of the digital part of an
- a cell that switches is a cell whose inputs change logical state, a logic state (0 or 1) corresponding to a voltage range.
- the logic state 0 may for example correspond to a voltage between 0 and 5% of the supply voltage of a cell, while the logic state 1 can for example correspond to a voltage between 95 and 100% of the supply voltage of a cell.
- the cell has internal activity as soon as one of its inputs changes state.
- the determination of the switching activity, whether medium or bounded can be performed from a SPICE modeling any transistor circuit. This modeling makes it possible to simulate very precisely a switching activity for given input signals, but requires a lot of resources and is only applicable with small circuits.
- VHDL Very Large Scale Integration in English
- VLSI circuits Very Large Scale Integration in English
- the first level is a functional simulation in the strict sense of the cells in which no propagation delay is taken into account.
- a second level of simulation takes into account the internal cell switching delays (delays to move from one logical state to another).
- a third level of simulation takes into account the internal delays of switching, as well as the propagation delays of the information on the lines between the cells (wire delay).
- test patterns For N entries that can take two logical states, 2 ⁇ N * (2 ⁇ N-1) test patterns are to be applied to the primary inputs of the circuit for exhaustive processing; which generates a very long treatment time.
- the invention proposes to solve the problems of complex implementation of existing techniques and a wider application when the complete architecture of the circuit is not available.
- the invention results from a simple observation on the manner in which the signals are transmitted within a digital circuit.
- the cells connected to the inputs of this circuit switch and transmit a signal to the following cells connected to them, the signals thus transmitting gradually into the circuit.
- the switching activity therefore increases until a peak of activity is reached. Then the activity decreases until the different cells have switched for that clock signal or this excitation signal. It is therefore possible, by experiment, to apply switching activity profile models that generically respond to this observation on the evolution of the switching activity.
- These activity profiles can be derived from known statistical distribution models, such as Normal distribution or Poisson distribution.
- the choice of the statistical distribution most relevant to the observation that has been made is the Poisson distribution, which introduces the notion of "service” of digital cells or "queue”. This notion of service is thus matched to the number of cells that can switch for a particular excitation signal.
- the Poisson distribution thus indicates the amount of cells that switched over time (the area of the distribution), to finally give a total area representative of the number of cells that switched for a clock edge or an excitation signal. given.
- the Poisson mathematical model is empirically adapted to physical criteria that account for the actual switching activity of the cells.
- the model is adapted to physical parameters according to which it is likely that the distribution of switching times varies with time.
- the distribution of Poisson as it has been adapted is thus parameterizable according to the number of cells capable of switching (estimation or determination), the average fanout value encountered for each cell, and the minimum transmission delay. information from one cell to another.
- the fate of each cell gives the number of cells connected at the output of each cell considered. While the minimum period of Transmission is the minimum of the sum of the delay of switching of a cell (delay delay in English) and the delay of transmission of the signals on the interconnections between two cells (wire delay in English).
- Poisson distribution has the advantage of allowing the modeling of the switching activity inside a digital circuit without knowing precisely the complete description of the cells of this circuit and the connections between them. Indeed, simply with an indication of the cell population (number of cells, average fanout, etc.), we can model the switching activity of the circuit early in the design flow, for example before the logical synthesis of the digital circuit. .
- the invention therefore relates to a method of modeling a switching activity of a digital circuit, this digital circuit comprising cells interconnected by interconnections, these cells switching at a time when at least one of their inputs changes from state, successive commutations of the cells of the circuit occurring during a clock period TcIk of this circuit, this clock period TcIk being the delay on which a signal applied to the input of the circuit is processed by the cells of this digital circuit, characterized in that, the clock period being divided into time slots, it comprises the following steps: - calculating, from a suitable statistical model, the number of cells that can switch over each time interval of the period of time; clock, and
- FIG. 1 a graphical representation of a statistical model according to the invention of a switching activity developed from a Poisson model and a schematic representation of the distribution of the switching intervals to the different cells of a digital circuit.
- FIG. 2 an algorithm according to the invention ensuring the adaptation of the Poisson's law to obtain discrete values of cells able to switch during the time slots of a clock period;
- FIG. 3 a schematic representation of several activity profiles according to the invention of a circuit during a clock period, the Poisson activity model taking into account several stimuli in a reference period of one electronic system;
- FIG. 4 a schematic representation of steps of a variant of the invention in which the Poisson distribution is divided into equal areas corresponding to the calls of the same number of cells in a given time interval.
- FIG. 1 shows a schematic representation of a mixed electronic system 1 comprising analog blocks 2.1 -2.Q and digital blocks 3.1-3. K.
- the digital block 3.3 has cells 4.1-4. L digital. Each cell 4.1-4. L has one or more logic gates and perform a particular function. These cells 4.1 -4.L are interconnected via interconnections 6. The state changes of these cells 4.1-4. L are synchronized by a clock signal CLK applied to clock inputs of block 3.3.
- This clock signal CLK has a period TcIk which is the period over which a signal applied to primary inputs E1-EN of the block is processed by the cells 4.1-4. L of block 3.3.
- the Poisson's law has thus been adapted to the mean quantization of the fa cells and to the number of cells capable of switching Na, k being a positive integer.
- Na is the number of cells of the circuit that can be called over a clock period TcIk, that is to say those likely to receive a variation on their inputs.
- Na L / 2 is chosen, which is representative of the average switching activity of a digital block.
- netlist contains information about 4.1 -4.L cells and the interconnections between these cells. If such information is not available, it is known from experience that the average fanout of an electronic circuit can be 2, 3 or 4 as the first hypothesis.
- Tclk / tm. tm is the minimum transmission time of information from one cell to another within block 3.3.
- the duration tm is defined by the minimum duration separating two commutations of two successive cells, one being connected to the input of the other and controlling it.
- the duration tm results from the combination of two delays. The first is the switching delay of a cell which is the time for the cell to change state when one of its inputs receives a rising or falling edge.
- the second is the signal transmission delay between the cells which corresponds to the signal propagation delay on the interconnections between cells linked in particular to the RC networks of lines and to the cell input capacitors.
- the time tm can be determined from manufacturer data of cells 4.1-4. L.
- the duration tm which is a duration less than TcIk 1, could also be a constant value other than the minimum duration separating two commutations of two successive cells.
- the rounding to the nearest integer of S [i] .tm is determined and this integer round is associated with the corresponding interval.
- the number of cells capable of switching over the time interval [t0; t1 [ is equal to the integer part of (2,15.tm).
- a graph 12 in sticks is then obtained, the area of each stick 13 giving an integer number of cells capable of switching for each time interval [tk; tk + 1 [.
- the area of the set of sticks 13 is equal to the total number of cells that can be called (ie switched) during a clock period TcIk.
- the instructions of Part A of the algorithm of Figure 2 which are included within a loop implemented for each interval [tk; tk + 1 [, allow the calculation of the integer number of cells switching over an interval.
- the difference 14 between the real value of the area and the rounding to the nearest integer of this area is kept in memory and accumulated with the other differences existing on the other intervals [tk; tk + 1 [.
- this whole part positive or negative
- this whole part is added to the number of cells that can switch to the next interval. This ensures that the total area of the bars 13 is equal to Na. In other words, one redistributes on the whole of the graph 12 the differences that can exist between the value of the area of the stick and the rounding with the integer closest to this area.
- Part B of the algorithm of Figure 2 includes instructions for redistributing the calculated differences.
- the variable "difference” corresponds to the accumulation of differences between the values real cells and round to the nearest integer of these values.
- the integer part (INT) of the variable "difference” is added to the number of cells that can switch over the time interval, if this integer part is not 0.
- the differences can be compensated naturally and it is not necessary to perform this compensation calculation to implement the method according to the invention.
- Part D of the algorithm of FIG. 2 thus makes it possible to assign a non-zero value to the variable "Cells_called_in_delay" representing, we have seen, the number of cells likely to be called on an interval, when the number of cells on this interval should be zero according to the algorithm, but that the area of the Poisson curve is not equal to the number cells (Na) that can switch in block 3.3.
- the variable "difference" of 1 is decremented to compensate for the interval that has been assigned to the interval.
- a random delay is assigned to each cell over each time interval [tk; tk + 1 [.
- this delay is worth k.tm + rand ().
- tm, rand () being a function giving a random value between 0 and 1. This choice makes it possible to smooth current calls within a time interval [tk; tk + 1 [during which the call is made over an interval and not strictly at times k.tm with k integer (which might also be possible).
- two cells are randomly assigned to each other and assigned a switching instant equal to, for example, tm + 0.1tm and tm + 0.3tm with respect to the beginning of the clock period.
- tm + 0.1tm and tm + 0.3tm with respect to the beginning of the clock period.
- the draws of the cells are carried out without discount. that is, once a cell has been drawn, it can no longer be drawn.
- the distribution of the switching instants of the cells 4.1 -4.L of the block 3.3 occurs each time a rising edge 17 or a falling edge 18 of a clock signal CLK or reference signal is observable.
- a single reference signal is defined for all digital blocks of the electronic system.
- K may have several switching activity profiles 12 over a TcIk clock period, the same activity profile repeating itself within the period clock. Two successive profiles 12 may be separated from each other by a non-zero delay.
- the multiplication of the profiles is also observable on different fronts, for example on the rising edge and on the falling edge of the clock.
- the digital block 3 operates at a frequency four times greater than that of the clock signal CLK.
- Td time delay between the beginning of the reference period of the TcIk system and the start of the switching activity of the digital block 3.1-3.
- K time delay
- This offset Td can for example be due to a response time of the digital block 3.1-3. K linked to the clock signal that passes through other circuits or by a clocktree in English before being applied to the digital block.
- the mixed system 1 comprising several digital circuits 3.1-3. K
- cells 4.1-4 are associated. L of the noise injection spectra and a delay with respect to the clock edge for the effective call time of the injected noise waveform, this delay being calculated using Poisson modeling. 12. For each cell, a resulting spectrum is obtained which is the spectrum multiplied by a frequency delay operator. It is then possible to combine these resulting spectra to calculate the overall noise of a block. And it is then possible to combine these block noises to calculate the overall noise injected into the system 1 for a given switching activity model.
- the area of the curve P (t) indicates the number of cells likely to switch for a time interval associated with this area.
- the total area 31 of the curve P (t) is thus equal to the total number Na of cells of the digital circuit capable of switching.
- the Na cells considered as likely to switch are chosen at random in the same manner as previously.
- n 6 Na being a multiple of 6.
- F (t) is solved for different values of the number of cells called, these values being multiples of the number of cells. Nope.
- rand () is a random function giving a value between 0 and 1.
- rand () is a random function giving a value between 0 and 1.
- the switching pattern can be repeated several times within a clock period TcIk.
- the various steps of the method according to the invention can be implemented by an electronic circuit or with the aid of software executed by a computer, the software being recorded on a support of the floppy disk type, CD, DVD, USB memory, or any other equivalent medium.
- the invention extends to the circuit manufacturing method comprising a preliminary step of modeling the switching activity according to the invention, as well as the software for implementing the invention.
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Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/373,483 US20100017173A1 (en) | 2006-07-13 | 2007-07-12 | Method of modelling the switching activity of a digital circuit |
JP2009518937A JP2009543240A (ja) | 2006-07-13 | 2007-07-12 | デジタル回路のスイッチング活動状態をモデル化する方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0652987A FR2903794B1 (fr) | 2006-07-13 | 2006-07-13 | Procede de modelisation de l'activite de commutation d'un circuit numerique |
FR0652987 | 2006-07-13 |
Publications (2)
Publication Number | Publication Date |
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WO2008007026A2 true WO2008007026A2 (fr) | 2008-01-17 |
WO2008007026A3 WO2008007026A3 (fr) | 2008-03-06 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/FR2007/051646 WO2008007026A2 (fr) | 2006-07-13 | 2007-07-12 | Procédé de modélisation de l'activité de commutation d'un circuit numérique |
Country Status (4)
Country | Link |
---|---|
US (1) | US20100017173A1 (fr) |
JP (1) | JP2009543240A (fr) |
FR (1) | FR2903794B1 (fr) |
WO (1) | WO2008007026A2 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US8191022B2 (en) * | 2008-07-15 | 2012-05-29 | Rambus Inc. | Stochastic steady state circuit analyses |
US9310990B2 (en) | 2010-04-26 | 2016-04-12 | Blackberry Limited | Portable electronic device and method of controlling same |
US9710590B2 (en) * | 2014-12-31 | 2017-07-18 | Arteris, Inc. | Estimation of chip floorplan activity distribution |
KR20160123452A (ko) * | 2015-04-15 | 2016-10-26 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 그의 구동 방법 |
EP3327710A4 (fr) * | 2015-07-21 | 2019-03-06 | Shenzhen Royole Technologies Co., Ltd. | Circuit de pixel et son procédé d'attaque, et panneau d'affichage |
US11093675B1 (en) * | 2020-03-18 | 2021-08-17 | International Business Machines Corporation | Statistical timing analysis considering multiple-input switching |
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GB2316572B (en) * | 1996-08-14 | 2000-12-20 | Fujitsu Ltd | Multicasting in switching apparatus |
JP3569681B2 (ja) * | 2001-02-02 | 2004-09-22 | 株式会社半導体理工学研究センター | 半導体集積回路における電源電流波形の解析方法及び解析装置 |
CA2617235A1 (fr) * | 2004-08-06 | 2006-02-16 | Entaire Global Intellectual Property, Inc. | Systeme informatique permettant de surveiller activement et d'ameliorer la securite de garantie d'un portefeuille de prets en vue de faciliter son financement et sa securisation. |
US7821996B2 (en) * | 2005-10-27 | 2010-10-26 | Motorola Mobility, Inc. | Mobility enhancement for real time service over high speed downlink packet access (HSDPA) |
FR2897178B1 (fr) * | 2006-02-07 | 2008-09-05 | Coupling Wave Solutions Cws Sa | Procede d'estimation d'un bruit genere dans un systeme electronique et procede de test d'immunite au bruit associe |
US7797217B2 (en) * | 2006-03-15 | 2010-09-14 | Entaire Global Intellectual Property, Inc. | System for managing the total risk exposure for a portfolio of loans |
US8112340B2 (en) * | 2006-05-12 | 2012-02-07 | Standard & Poor's Financial Services Llc | Collateralized debt obligation evaluation system and method |
FR2902910B1 (fr) * | 2006-06-26 | 2008-10-10 | Coupling Wave Solutions Cws Sa | Procede de modelisation du bruit injecte dans un systeme electronique |
-
2006
- 2006-07-13 FR FR0652987A patent/FR2903794B1/fr not_active Expired - Fee Related
-
2007
- 2007-07-12 US US12/373,483 patent/US20100017173A1/en not_active Abandoned
- 2007-07-12 WO PCT/FR2007/051646 patent/WO2008007026A2/fr active Application Filing
- 2007-07-12 JP JP2009518937A patent/JP2009543240A/ja active Pending
Non-Patent Citations (6)
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BIN ZHANG AND MICHAEL ORSHANSKY: "SER Prediction by Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses" PROCEEDINGS OF WORKSHOP ON THE SYSTEM EFFECTS OF LOGIC SOFT ERRORS, [Online] 5 avril 2005 (2005-04-05), pages 1-4, XP002410749 Extrait de l'Internet: URL:http://www.crhc.uiuc.edu/SELSE/> [extrait le 2006-12-07] * |
BRIAIRE J ET AL: "Principles of Substrate Crosstalk Generation in CMOS Circuits" IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 19, no. 6, juin 2000 (2000-06), XP011007851 ISSN: 0278-0070 * |
BROSTER I ET AL: "Comparing real-time communication under electromagnetic interference" PROCEEDINGS. 16TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS IEEE COMPUT. SOC LOS ALAMITOS, CA, USA, 2004, pages 45-52, XP002410967 ISBN: 0-7695-2176-2 * |
BURLESON W ET AL: "Trading Off Transient Fault Tolerance andPower Consumption in Deep Submicron (DSM) VLSI Circuits" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 12, no. 3, mars 2004 (2004-03), pages 299-311, XP011109998 ISSN: 1063-8210 * |
JOSE MONTEIRO ET AL: "Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation" IEEE TRANSACTIONS ON COMPUTER-AIDEDDESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 16, no. 1, janvier 1997 (1997-01), pages 121-127, XP011007390 * |
NAJM F N ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Transition density, a stochastic measure of activity in digital circuits" PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE. SAN FRANCISCO, JUNE 17 - 21, 1991, PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), NEW YORK, IEEE, US, vol. CONF. 28, 17 juin 1991 (1991-06-17), pages 644-649, XP010575395 ISBN: 0-89791-395-7 * |
Also Published As
Publication number | Publication date |
---|---|
WO2008007026A3 (fr) | 2008-03-06 |
US20100017173A1 (en) | 2010-01-21 |
FR2903794A1 (fr) | 2008-01-18 |
JP2009543240A (ja) | 2009-12-03 |
FR2903794B1 (fr) | 2008-09-05 |
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