Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28158—Making the insulator
  • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
  • H01L21/048—Making electrodes
  • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts

Definitions

• the present invention relates to a silicon layer which is very sensitive to oxygen and a process for obtaining this layer.
• Silicon carbide is a very interesting IV-IV compound semiconductor material, which is particularly suitable for high power, high voltage or high temperature devices and sensors.
• the conventional oxidation (direct oxidation of SiC) of the SiC surfaces in particular the hexagonal surfaces of this material
• SiC surfaces in particular the hexagonal surfaces of this material
• the conventional oxidation (direct oxidation of SiC) of the SiC surfaces generally leads to the formation of oxides of Si and C, which have poor electrical properties, and SiO 2 / SiC interfaces that are not steep, the transition between SiC and SiO 2 being done on several atomic layers.
• the electron mobility in the MOS structure inversion layers on p-SiC is much smaller (by a factor of 10) than on the silicon due to the disorder at the interface.
• a process for obtaining SiO 2 passivation on SiC is known from EP-A-0637069 (Created Research, Inc.). Obtaining a layer of SiO 2 of 62nm from a Si layer, in accordance with this document, requires high-temperature thermal oxidation (about 1200 0 C) and at a very high pressure of oxygen (approximately the atmospheric pressure, that is to say about 10 5 Pa).
• the miniaturization of microelectronic devices creates a need for increasingly thin passivation layers, the interface between a passivation layer and the substrate that carries it becoming more and more abrupt.
• No. 6,667,102 A corresponding to WO 01/39257 A discloses a silicon layer which is sensitive to oxygen at ambient temperature. This layer is formed on hexagonal silicon carbide and has a 4x3 surface structure.
• the present invention aims to overcome the above disadvantages.
• It relates to a silicon layer that greatly promotes the growth of an oxide on a substrate and leads to an interface
• SiO 2 / substrate which is steep, while allowing softer oxidation conditions than those permitted by the known art, mentioned above.
• the invention makes it possible to obtain thinner passivation layers than those obtained by this known technique.
• the subject of the present invention is a formed silicon layer, in particular deposited on a substrate, this layer being characterized in that it has a 3 ⁇ 2 structure, the substrate being able to receive this 3 ⁇ 2 silicon structure or to promote its formation.
• the layer has a 3 ⁇ 2 surface structure (it is also said to be 3 ⁇ 2 reconstructed), the substrate being able to receive this 3 ⁇ 2 surface structure of silicon or to promote its formation. .
• the layer is oxidizable at a temperature of less than or equal to 65 ° C.
• the substrate is ⁇ -SiC silicon carbide.
• the present invention also relates to a silicon oxide layer, this layer resulting from the oxidation of the silicon layer that is the subject of the invention.
• the present invention also relates to a surface covered with this layer of silicon oxide.
• the present invention furthermore relates to a method for obtaining the silicon layer that is the subject of the invention, in which silicon is deposited in a substantially uniform manner on a surface of the substrate.
• the present invention also relates to another method for obtaining a silicon oxide layer on a substrate, this other method being characterized in that it comprises the following successive steps: (a) the formation (in particular the deposition) of the silicon layer which is the subject of the invention on the substrate, and
• the oxidation of the silicon layer is carried out at a temperature of less than or equal to 65 ° C., more particularly at a temperature ranging from room temperature to 500 ° C.
• this temperature is the ambient temperature (approximately 20 ° C.).
• the SiO / Si or SiO 2 / substrate interface which is obtained after oxidation, is abrupt, the transition between the substrate and SiO 2 being practically on a few atomic layers.
• the silicon layer formed (in particular deposited) on the substrate has a 3 ⁇ 2 surface structure (it is also said that it is reconstructed 3 ⁇ 2), the substrate being able to receive this 3x2 surface structure of silicon or suitable to promote the formation of this structure.
• the substrate is made of a material selected from silicon carbide and silicon.
• the silicon carbide may be monocrystalline, polycrystalline, amorphous or porous.
• the silicon layer is formed on a ⁇ -SiC surface, preferentially on the (001) face.
• the Joule effect can be used, preferably by passing a continuous electric current through the substrate.
• the various steps of the method which is the subject of the invention are preferably carried out in an ultrahigh vacuum chamber, advantageously the same chamber during the entire process.
• the heating of the substrate can be done by electron bombardment of this substrate.
• the surface of the substrate is rinsed before the formation of the silicon layer on this surface.
• the rinsing is carried out with an organic solvent, this solvent advantageously comprising ethanol or methanol.
• the substrate is degassed before the formation of the silicon layer.
• the substrate is heated, preferably at about 65 ° C., in particular for silicon carbide, under a reduced pressure, advantageously 3 ⁇ 10 -9 Pa, for a sufficient duration, for example 24 hours, to be degassed.
• one or more annealing of the substrate can also be carried out, until no LEED contaminant is detected, that is to say by electron diffraction.
• low energy in English, low energy electron diffraction
• RHEED that is to say by high energy electron diffraction and reflection
• at least one annealing and then cooling of the substrate is carried out.
• each annealing is carried out as follows:
• the substrate is heated at 1000 ° C. for 3 minutes and then at 0 ° C. for 1 minute and then at 1200 ° C. for 1 minute, and then the substrate is slowly cooled at a rate of 100 ° C. per minute to the temperature ambient (approximately 20 ° C.).
• Such a method makes it possible to deposit silicon in a substantially uniform manner on a surface of the substrate.
• the silicon layer of step (a) is formed at room temperature.
• the thickness of this layer is preferably less than or equal to 10 nm.
• at least one annealing of the silicon layer is carried out after the formation of this layer in step (a).
• a surface of the substrate, maintained at ambient temperature is prepared, according to the methods indicated above, to receive the silicon layer, and then is deposited in a substantially uniform manner.
• the silicon on the surface of the substrate, at least one annealing of the substrate on which the silicon has been deposited is carried out at least 1000 ° C., the total annealing time being at least 5 minutes, and cooling is carried out up to ambient temperature (approximately 20 ° C.) the substrate at a speed of at least 100 ° C./minute.
• the substrate may also be brought to a temperature above ambient temperature, for example at about 65 ° C., to effect the deposition.
• the deposition and annealing steps can also be performed simultaneously, the deposition being done in this case at high temperature.
• the silicon layer is formed on this substrate at room temperature, then the assembly constituted by the substrate and this layer is then subjected to at least annealing at least 65O 0 C, the total annealing time being at least 7 minutes, the annealing or annealing being followed by cooling at a speed of at least 50 ° C / minute.
• the preparation of the surface of the substrate to receive the monocrystalline silicon and / or to promote the formation of the latter comprises an auxiliary heating of the substrate to at least 1000 ° C., a substantially uniform auxiliary deposition of monocrystalline silicon on the surface of the substrate thus heated and at least one auxiliary annealing of the substrate after this auxiliary deposition, at least 65 ° C., the total auxiliary annealing time being at least 7 minutes.
• the preparation of the surface of the substrate preferably comprises a degassing of the substrate under ultra-vacuum then at least one annealing of this substrate, followed by cooling of the substrate.
• the silicon layer is preferably formed by vacuum evaporation.
• this layer can be formed in other ways, for example by chemisorption / interaction of silane or by evaporation by electron bombardment of a silicon sample.
• the silicon is deposited on the substrate from a silicon sample whose surface is larger than that of the substrate.
• the surface of the silicon sample and the surface of the substrate are separated by a distance of the order of 2 to 3 cm.
• the oxidation of the silicon layer is carried out following the deposition of the silicon layer, advantageously in the same enclosure.
• the oxidation of the silicon layer is made with an oxygen exposure in the range of 8000 langmuirs (about 0.8 Pa) to 15000 langmuirs (about 1.5 Pa). exposure is preferably equal to 10,000 langmuirs (about IPa. s).
• an oxide layer With the method of obtaining an oxide layer according to the invention, it is possible to increase the thickness of the oxide to 10 nm with a steep remaining interface. To obtain a result Similarly, the amount of oxide can be advantageously increased by higher exposures to oxygen and by slightly higher temperatures, close to 65O 0 C. In the present invention, annealing can be carried out after the oxidation of the oxide. 3x2 structure silicon layer.
• the present invention is very useful for the manufacture of MOS devices and in particular of MOSFET devices (MOS type field effect transistors).
• FIG. single appended schematically illustrates the manufacture of a silicon layer in accordance with the invention.
• a silicon layer having a 3 ⁇ 2 structure can be obtained according to the methods described in document FR 2 823 770 A, corresponding to US 2004/0104406 A.
• a cubic monocrystalline silicon carbide sample is used which is commercially available from NovaSiC and Hoya Companies as well as from LETI (a laboratory of the Atomic Energy Commission).
• the used face of this sample is the face (100).
• This sample may consist of a thin film, of thickness greater than or equal to 1 ⁇ m, epitaxied on a silicon wafer, or may be a solid sample having a thickness of about 300 ⁇ m.
• this sample has, for example, a length of 13 mm and a width of 5 mm.
• the sample is introduced into an ultrahigh vacuum chamber where a pressure of the order of 3xlCT 9 Pa is established and where this sample is heated by a direct Joule effect by passing an electric current through the sample. .
• the temperature of the latter is measured using an infrared pyrometer. First, the sample is degassed, leaving it for 24 hours at 65 ° C. under ultrahigh vacuum.
• the sample is then subjected to a series of annealing operations until no contaminants are detected, for example by photoemission, and the surface of the sample is well ordered, as verified by LEED or by RHEED:
• the sample is heated at 1000 ° C. for 3 minutes and then at 0 ° C. for 1 minute and then at 1200 ° C. for 1 minute; the sample is then slowly cooled at a rate of 100 ° C. per minute to room temperature (approximately 20 ° C.).
• silicon carbide sample having, for example, a length of 20 mm and a width of 10 mm
• silicon sample having, for example, a length of 20 mm and a width of 10 mm
• silicon is deposited uniformly on the surface of the sample of silicon carbide maintained at ambient temperature.
• the silicon carbide sample and the silicon sample face each other and are at a distance D of 2 cm one of
• the larger surface area of the silicon sample allows homogeneity, i.e., uniformity, of silicon deposition on the silicon carbide sample.
• SiC thus coated with silicon the annealing series described above: this sample is heated at 1000 ° C. for 3 minutes and then at 0 ° C. for 1 minute and then at 1200 ° C. for 1 minute.
• the sample thus coated with Si then undergoes a new series of anneals: 1 minute at 75O 0 C then 1 minute at 700 0 C and then 5 minutes at 65O 0 C.
• the sample is then slowly cooled to room temperature, at a rate of 50 ° C. per minute.
• the surface of ⁇ -SiC (100) thus obtained has a 3 ⁇ 2 structure (square mesh).
• the 3x2 reconstructed areas have dimensions of the order of 550 nm x 450 nm, can have a low density of steps and have a few islands of Si in formation 3x2.
• the reconstructed islets have dimensions of the order of 550 nm x 450 nm, can have a low density of steps and have a few islands of Si in formation 3x2.
• 3x2 are then selected for the next step. Silicon can then be added and allows the epitaxial growth of a 3x2 reconstructed silicon layer.
• the pumping means making it possible to obtain the utravide are symbolized by the arrow 8.
• the substrate 4 is mounted on a suitable support 10 and the heating means of the substrate by the Joule effect are symbolized by the arrows 12.
• Joule heating means of the silicon sample 14 are also seen, these means being symbolized by arrows 16.
• This oxidation proceeds as follows: the sample coated with a layer of Si-3 ⁇ 2 is exposed to oxygen, while being maintained at a temperature in the range from 25 ° C. to 65 ° C. ; the exposure to oxygen is equal to 10 4 langmuirs (approximately IPa s).
• This last process can be done several times in a row, the interface between the SiO 2 and the substrate remaining abrupt.
• Samples of varying thicknesses, as needed, can therefore be obtained by varying the exposure to oxygen.
• the oxidation of the silicon layer 2 is preferably made in the chamber 6.
• the chamber is provided with the means necessary for this oxidation, in particular an oxygen input (not shown).

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Formation Of Insulating Films (AREA)
• Physical Vapour Deposition (AREA)
• Chemical Vapour Deposition (AREA)
• Recrystallisation Techniques (AREA)
• Silicon Compounds (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)

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• 2005
  • 2005-07-05 FR FR0552059A patent/FR2888398B1/fr not_active Expired - Fee Related
• 2006
  • 2006-07-04 US US11/988,343 patent/US20090294776A1/en not_active Abandoned
  • 2006-07-04 JP JP2008519928A patent/JP2008544945A/ja active Pending
  • 2006-07-04 WO PCT/EP2006/063856 patent/WO2007003638A1/fr active Application Filing
  • 2006-07-04 EP EP06764054A patent/EP1900012A1/de not_active Ceased

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