EP1900014A2 - Zum grossteil aus siliciumcarbid hergestelltes und mit einer dünnen stöchiometrischen folie aus siliciumnitrid beschichtetes substrat zur erzeugung elektronischer komponenten und verfahren zur gewinnung einer solchen folie - Google Patents

Zum grossteil aus siliciumcarbid hergestelltes und mit einer dünnen stöchiometrischen folie aus siliciumnitrid beschichtetes substrat zur erzeugung elektronischer komponenten und verfahren zur gewinnung einer solchen folie

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Publication number
EP1900014A2
EP1900014A2 EP06792480A EP06792480A EP1900014A2 EP 1900014 A2 EP1900014 A2 EP 1900014A2 EP 06792480 A EP06792480 A EP 06792480A EP 06792480 A EP06792480 A EP 06792480A EP 1900014 A2 EP1900014 A2 EP 1900014A2
Authority
EP
European Patent Office
Prior art keywords
substrate
layer
silicon
sic
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06792480A
Other languages
English (en)
French (fr)
Inventor
Patrick Soukiassian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universite Paris Sud Paris 11
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Universite Paris Sud Paris 11
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Universite Paris Sud Paris 11 filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1900014A2 publication Critical patent/EP1900014A2/de
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048Making electrodes
    • H01L21/049Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to a substrate, in particular silicon carbide (SiC), covered by a thin layer of stoichiometric silicon nitride, for the manufacture of electronic components, and a process for obtaining such a layer. It applies in particular in microelectronics.
  • Silicon is currently the semiconductor material most used in the electronics industry, mainly because of the exceptional properties, especially insulating, of its native oxide, silicon dioxide (SiO 2 ). From this point of view, SiC is especially interesting since the passivation of its surface can be carried out by growth of SiO 2 under conditions similar to those of silicon.
  • Silicon carbide (SiC), semi ⁇ conductive compound IV - IV is therefore a very interesting material which is particularly suitable for devices and sensors of high power, high voltage, high frequency or high temperature and which can be monocrystalline (in cubic, hexagonal (there are more than 170 polytypes) or rhombohedral), polycrystalline, amorphous or porous.
  • MOS Metal Oxide Semiconductor
  • SiC-based electronic devices such as high-performance MOS transistors, and in particular those based on the hexagonal polytypes (H) of this material, are surface passivation, which is related to oxidation of SiC, and the insulating structures on SiC.
  • SiC Independently of its exceptional qualities as a semiconductor (a factor of merit up to 1000 times higher than that of Si, GaAs and InP), SiC has the same native oxide (SiO 2 ) as silicon, oxide whose insulating qualities remain to this day unequaled.
  • the present invention is part of this technological field and proposes a solution to one points of passage for the success of the SiC industry.
  • the present invention aims to solve the problems mentioned above and, in particular, the elimination of electronic interface states, it also allows to obtain interfaces as abrupt as possible and free of defects, as well as the elaboration devices less sensitive to the migration of dopants during the manufacture of microelectronic devices.
  • the inventors have also discovered a process for preparing this layer, having the property of limiting or blocking the diffusion of dopants and passivating the defects at the insulating / semiconductor interfaces (in particular SiO 2 / Si)
  • the present invention firstly relates to a substrate, in particular silicon carbide, for the manufacture of electronic components, this substrate being characterized in that it is covered with a thin layer of nitride of stoichiometric silicon.
  • the invention also relates to a process for obtaining a layer of stoichiometric silicon nitride on a substrate in the presence of at least one nitrogen gas, this process being characterized in that the The substrate is covered with a layer of material which is permeable to this nitrogen gas and in that the stoichiometric silicon nitride layer is able to form at the interface between the substrate and the layer of the material.
  • the substrate is able to receive the material or to promote its formation.
  • the material is furthermore capable of being oxidized.
  • the material is silicon.
  • this silicon is monocrystalline.
  • the layer of the material has a thickness between 0.5 nm and 20 nm.
  • the substrate is silicon carbide.
  • the silicon carbide is monocrystalline and has a ⁇ -SiC structure, in which case the face (100) is preferably used, or an ⁇ -SiC structure, in which case the (0001) face is preferably used.
  • the preparation of the surface of the substrate able to receive the monocrystalline silicon and / or to promote its formation comprises an auxiliary heating of the substrate to at least 1000 ° C., a substantially uniform auxiliary deposition of monocrystalline silicon on the surface of the heated substrate and at least one auxiliary annealing of the substrate after this deposit auxiliary, at least 65O 0 C, the total auxiliary annealing time being at least 7 minutes.
  • the silicon is deposited substantially uniformly on the surface of the substrate.
  • the silicon layer has a cubic structure and its thickness ranges from 0.5 nm to 20 nm.
  • the silicon is deposited on the substrate, this substrate being heated around 65O 0 C, the compound resulting from this deposit is then annealed at at least 65O 0 C, the total annealing time being at least 7 minutes, then cooled to a speed of at least 50 ° C / minute.
  • the preparation of the surface of the substrate preferably comprises a degassing of the substrate under ultrahigh vacuum (10 ⁇ 10 Torr or about 10-8 Pa) and then at least one annealing of this substrate followed by cooling of the substrate. It is preferable that the cooling is not too fast to avoid thermal shocks.
  • the silicon is deposited from a surface of a silicon sample, this surface being greater than the surface of the substrate, and the distance between these surfaces is between 2 cm and 3 cm.
  • the deposition of silicon may be followed by one or more anneals at temperatures of, for example, between 700 ° C. and 1000 ° C. It is preferable to check the quality of the deposit, for example by slow electron diffraction (LEED). or electrons fast (RHEED) or X-ray diffraction (XRD) or photoelectron (PED). Several anneals and deposits can thus be carried out until a silicon film is obtained.
  • the deposited silicon is cubic, the mesh parameter of the SiC being approximately equal to that of Si minus 20%.
  • the deposited silicon preferably has an atomic arrangement of the 3 ⁇ 2 type to prepare a ⁇ -SiC (100) and 4x3-type surface to prepare an ⁇ -SiC (OOOl) surface.
  • the nitrogen gas is preferably selected from nitrogen oxide NO, NO 2 , ammonia NH 3 , nitrous oxide N 2 O and atomic nitrogen.
  • NO is used; in this case, it is preferable to remove any oxide trace due to oxynitriding, in order to obtain a stoichiometric layer of silicon nitride (Si 3 N 4 ); to do this, it is advantageous to employ a heat treatment such as annealing of the surface, preferably at least 1000 ° C.
  • Exposure to NO can be carried out by various known methods, such as for example the exposure of the substrate to this gas via a tube or a gas inlet located in front of the substrate or not far from it so that the enclosure in which the gas exposure is carried out contains the desired amount of gas.
  • the exposure sufficiency can be monitored by spectrometry.
  • photoemission spectrometry in English, synchrotron radiation-based photoemission spectroscopy
  • heart levels Si 2p, C Is, O Is and N Is Si 2p, C Is, O Is and N Is.
  • the substrate is exposed to NO molecules under vacuum.
  • the exposure is preferably carried out under a diet of 100 langmuirs
  • the exposure is made from a gas line facing the surface of the substrate.
  • the gas line is placed at a distance D from the surface of the silicon carbide, D being preferably between 2 cm and 3 cm, so that the oxynitriding can take place homogeneously.
  • the exposure can be carried out independently at ambient temperature (from 10 ° C. to 30 ° C.) or up to 800 ° C. at 1000 ° C., in which case the substrate is heated by appropriate means, for example by Joule effect.
  • the annealing mentioned above can be carried out by appropriate means, for example by Joule effect; these means are preferably the same as those that can be used during exposure to NO.
  • the annealing is carried out at a temperature of between 800 ° C. and 1000 ° C., more particularly at 1000 ° C., the temperature at which it has been found that only oxygen has been eliminated.
  • the cooling is carried out under vacuum or in an inert atmosphere, preferably at a pressure ranging from 10 ⁇ 6 Pa to 10 ⁇ 5 Pa. To avoid a thermal shock, it is preferable that the cooling rate does not exceed 50 ° C. per minute.
  • the steps of exposure and removal of oxide are carried out simultaneously or continuously.
  • the present invention also relates to a method of manufacturing an electronic component, in particular a MOS device, on a substrate, in which process a silicon nitride layer is formed on the substrate by the method that is the subject of the invention.
  • FIG 1 schematically illustrates an installation for obtaining a stoichiometric silicon nitride Si 3 N 4 layer according to the invention
  • FIG. 2 is a schematic sectional view of an SiC substrate covered with such a layer according to the invention.
  • Figure 1 schematically illustrates an installation for obtaining a stoichiometric Si 3 N 4 layer according to the invention.
  • References 1, 2 and 3 respectively represent a monocrystalline SiC substrate, a structured monocrystalline Si thin layer, and a substrate support.
  • Reference 4 represents a gas line
  • the arrow 5 symbolizes the entry of the NO gas into the vacuum chamber 6.
  • the arrows 7 and 8 respectively symbolize pumping means and means for heating the substrate 1 for example by Joule effect.
  • the pumping means 7 make it possible to obtain the exposure regime for the NO molecules.
  • the substrate 1 lined with the Si layer 2 is mounted on the support 3.
  • the gas line 4 supplies the chamber 6 with NO molecules. It is positioned at a distance D from the surface of the substrate 1 of silicon carbide. This distance D is between 2 and 3 cm.
  • This exposure under vacuum leads to oxy-nitriding of the SiC substrate coated with the Si layer.
  • the exposure is carried out from the gas line 4 facing the surface of the silicon carbide coated with the Si layer.
  • the exposure is carried out at ambient temperature (10 ° C. to 30 ° C.) under a diet included, for example, between 100 langmuirs
  • this exposure can also be done at high temperature, up to a temperature of the order of 800 0 C to 1000 0 C.
  • the substrate is heated by means 8.
  • the exposure is followed by annealing at high temperature under ultra-high vacuum, for example at 1000 ° C.
  • the means for heating the substrate are used when an exposure at a temperature different from the ambient temperature is chosen. For exposure at ambient temperature, these means are therefore not implemented.
  • the means 8 for heating the substrate are also usable during the annealing of the substrate under vacuum, carried out after the exposure leading to the oxynitriding of the surface of the silicon carbide.
  • FIG. 2 shows the result of the implementation of the process according to the invention: the substrate 1 is covered with a layer 10 of stoichiometric Si 3 N 4 .
  • a layer 12 of non-stoichiometric Si 3 N 4 covers this layer 10 and the layer 12 is covered by a residual silicon layer 14.
  • this barrier makes it possible to prevent the diffusion of these dopants in the oxide layer of the SiO 2 / Si interfaces; this property remains valid for SiC.
  • This advantageous property is important because the presence of these dopants in the oxide layer causes a very significant degradation of the performance of the devices using such layers as, for example, the MOS devices.
  • WO 01/39257A corresponding to US Pat. No. 6,667,102 A, discloses a method of manufacturing a silicon oxide layer, intended to solve some of the above disadvantages, on a silicon carbide or silicon substrate. coated with a thin layer of silicon having a 4x3 surface structure.
  • This layer may particularly and advantageously be formed on a reconstructed 6H-SiC (0001) surface, for example 3 ⁇ 3, V 3 ⁇ V 3, 6 V 3 ⁇ 6 V 3 or 1 ⁇ 1.
  • 6H-SiC (0001) surface for example 3 ⁇ 3, V 3 ⁇ V 3, 6 V 3 ⁇ 6 V 3 or 1 ⁇ 1.
  • SiO interfaces are obtained. 2 / SiC abrupt, the transition being made almost on a few atomic layers between the substrate and the silicon layer formed.
  • the Si / SiC system can be "oxidized" by following, for example, the process described in WO 01/39257 A.
  • SiO 2 / SiC interface is obtained with, in addition to a layer of non-stoichiometric silicon nitride, a thin layer of stoichiometric Si 3 N 4 between the SiO 2 oxide and the SiC, which makes it possible to stop the diffusion of dopants. in the oxide layer during heat treatments used in the manufacture of electronic devices incorporating such layers. It is also possible to deposit a new layer of Si in order to obtain a more or less thick layer of SiO 2 .
  • nitriding and thin film oxy-nitriding is the role played by the two silicon compounds in the passivation of defects at the SiO 2 / SiC interfaces.
  • the process for obtaining the nitriding layer according to the invention is very advantageous alone or in combination with that described in WO 01/39257 A.
  • the first example relates to the oxynitriding of a 3 ⁇ 2 structured ⁇ -SiC (100) surface and to the formation of a sub-stoichiometric silicon nitride.
  • ⁇ - SiC (IOO) 3x2 3x2 reconstruction
  • Direct oxy-nitriding of the SiC surface is then carried out.
  • the surface ⁇ -SiC (100) 3 ⁇ 2 which has been prepared, is exposed to NO by evaporation under vacuum, from a gas line facing the surface of the silicon carbide.
  • the exposure is carried out at room temperature (approximately 10-30 ° C.), under a regime situated for example between 100 and 10,000 languages, that is to say between approximately 10 -2 Pa ⁇ s and approximately 1 Pa. s.
  • This exposure can also be carried out at elevated temperature, up to a temperature of the order of 800 ° C. to 1000 ° C.
  • Thermal anneals to 65O 0 C lead to the formation of oxynitrides (Si-O x -N y ) richer in nitrogen, this effect being already known for silicon.
  • the anneals are carried out independently, under vacuum or under an inert atmosphere.
  • SiC sample is similar to that obtained with the Si. It is found that annealing at a temperature of 1000 0 C eliminates oxygen and leaves only a single reaction product that is composed of a sub-stoichiometric silicon nitride of small thickness (ranging from an atomic layer to several nanometers), whose presence is highlighted by observing the electronic levels of heart Si 2p and N Is, while the absence of oxygen is evidenced by the electronic heart level 0 Is.
  • the SiC carbon plane, located under the nitride, is not directly affected because it is the subsurface Si atoms that are involved in the oxynitriding process. A similar situation has been observed in the interaction of oxygen with the SiC surface.
  • a second example relates to the oxynitriding of the ⁇ -SiC (100) 3 ⁇ 2 surface modified by a thin layer of Si (3 ⁇ 2 structure) deposited and to the formation of a stoichiometric Si nitride (Si 3 N 4). ).
  • Si 3 N 4 stoichiometric Si nitride
  • silicon is deposited in a substantially uniform manner.
  • the exposure is made at room temperature (10 to 3O 0 C), located under a scheme, for example, between 100 and 10000 langmuirs langmuirs, i.e. between about 10 -2 Pa. S to about 1 Pa s. Note that this exposure also operates at high temperature, up to a temperature of the order of 800 0 C to 1000 0 C.
  • oxy-nitrides are obtained which are located under the surface, this time under the Si thin film, above the first SiC carbon plane. at the interface of these two layers.
  • the Si 3 N 4 film is very thin (between one and ten atomic monolayers) but its thickness is sufficient to block the diffusion of the dopants, without altering the qualities of the SiO 2 insulation layer that is can grow on the Si layer after obtaining the stoichiometric Si 3 N 4 layer.
  • a third example relates to the oxynitriding of the ⁇ -SiC (OOO1) 3x3 surface, on which a layer of Si (several atomic layers in formation 4x3) has been deposited, and to the formation of stoichiometric silicon nitride ( If 3 N 4 ).
  • the oxy-nitriding is also carried out on a monocrystalline silicon carbide substrate, having a 3 ⁇ 3 structured ⁇ -SiC (0001) surface.
  • the oxy-nitriding experimental method described in the foregoing is applied to hexagonal silicon carbide coated with a pre-deposited Si layer, forming a 4x3 cubic Si structure.
  • oxy-nitriding SiC coated with Si 4x3 is carried out.
  • the silicon carbide, coated with the Si 4x3 silicon layer thus prepared is exposed to NO molecules by evaporation under vacuum, from a gas line facing the surface of the coated silicon carbide.
  • the exposure is carried out at ambient temperature (approximately 10 to 30 ° C.) under a regime of, for example, between 100 and 10,000 langmuirs, that is to say between approximately 10 ⁇ 2 Pa ⁇ s and approximately 1 Pa. s. Note that this exposure also works at high temperature, up to a temperature of the order of 800 0 C to 1000 0 C. As in the case of the ⁇ -SiC surface (100)
  • 3x2 of the silicon carbide coated with the layer of Si 3x2, oxy-nitrides are again obtained which are located under the surface, under the thin film of Si, above the first carbon plane of the SiC.
  • annealing at 1000 ° C f not only is a nitride of Si sub-stoichiometric as before, but also a very thin layer (one to ten atomic layers) of Si 3 N 4 consisting of Si nitride stoichiometric which is also located under the Si layer, above the carbon plane.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP06792480A 2005-07-05 2006-07-04 Zum grossteil aus siliciumcarbid hergestelltes und mit einer dünnen stöchiometrischen folie aus siliciumnitrid beschichtetes substrat zur erzeugung elektronischer komponenten und verfahren zur gewinnung einer solchen folie Withdrawn EP1900014A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0552060A FR2888399B1 (fr) 2005-07-05 2005-07-05 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche
PCT/EP2006/063858 WO2007003639A2 (fr) 2005-07-05 2006-07-04 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche

Publications (1)

Publication Number Publication Date
EP1900014A2 true EP1900014A2 (de) 2008-03-19

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EP06792480A Withdrawn EP1900014A2 (de) 2005-07-05 2006-07-04 Zum grossteil aus siliciumcarbid hergestelltes und mit einer dünnen stöchiometrischen folie aus siliciumnitrid beschichtetes substrat zur erzeugung elektronischer komponenten und verfahren zur gewinnung einer solchen folie

Country Status (5)

Country Link
US (1) US20100012949A1 (de)
EP (1) EP1900014A2 (de)
JP (1) JP2009500837A (de)
FR (1) FR2888399B1 (de)
WO (1) WO2007003639A2 (de)

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Publication number Priority date Publication date Assignee Title
US10446681B2 (en) 2017-07-10 2019-10-15 Micron Technology, Inc. NAND memory arrays, and devices comprising semiconductor channel material and nitrogen
US10559466B2 (en) 2017-12-27 2020-02-11 Micron Technology, Inc. Methods of forming a channel region of a transistor and methods used in forming a memory array
US10297611B1 (en) 2017-12-27 2019-05-21 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells
JP7304577B2 (ja) * 2019-11-27 2023-07-07 国立大学法人大阪大学 絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法
US20230187525A1 (en) * 2020-03-17 2023-06-15 Hitachi Energy Switzerland Ag Insulated Gate Structure, Wide Bandgap Material Power Device With the Same and Manufacturing Method Thereof
US11538919B2 (en) 2021-02-23 2022-12-27 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells
CN114429898A (zh) * 2021-12-17 2022-05-03 浙江富芯微电子科技有限公司 一种用于制备氮化物单晶薄膜的碳化硅复合衬底

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FR2757183B1 (fr) * 1996-12-16 1999-02-05 Commissariat Energie Atomique Fils atomiques de grande longueur et de grande stabilite, procede de fabrication de ces fils, application en nano-electronique
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FR2823739B1 (fr) * 2001-04-19 2003-05-16 Commissariat Energie Atomique Procede de fabrication de nanostructures unidimensionnelles et nanostructures obtenues par ce procede
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Also Published As

Publication number Publication date
US20100012949A1 (en) 2010-01-21
WO2007003639A3 (fr) 2007-03-15
FR2888399B1 (fr) 2008-03-14
FR2888399A1 (fr) 2007-01-12
JP2009500837A (ja) 2009-01-08
WO2007003639A2 (fr) 2007-01-11

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