Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/04—Coating on selected surface areas, e.g. using masks
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/02—Elements
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
  • C30B29/605—Products containing multiple oriented crystallites, e.g. columnar crystallites
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/1608—Silicon carbide

Definitions

• METAL NANO-OBJECTS FORMED ON SEMICONDUCTOR SURFACES, AND METHOD FOR MANUFACTURING SUCH NANO-OBJECTS
• the present invention relates to metallic nano-objects, formed on the surfaces of a semiconductor, and more particularly of a semiconductor having a large "gap", that is to say having a large forbidden bandwidth, as well as 'a manufacturing process for these nano-objects.
• the invention relates more particularly to metallic nano-objects, such as, for example, atomic wires, one-dimensional nano-structures and metallic quantum dots, formed in particular on silicon carbide surfaces, as well as a process for manufacturing such nano-objects.
• metallic nano-objects such as, for example, atomic wires, one-dimensional nano-structures and metallic quantum dots, formed in particular on silicon carbide surfaces, as well as a process for manufacturing such nano-objects.
• the invention applies in particular to the field of nano-electronics.
• the fabrication of the nano-objects is done by self-organization, in particular at room temperature and above, without individual manipulation of atoms, for example by near field microscopy, which is done mostly cold (using liquid nitrogen or liquid helium) to avoid the migration of atoms (see documents [7] to [9] cited below).
• the present invention provides metallic nano-objects, such as atomic wires, one-dimensional nanostructures and metallic quantum dots, which are likely to be very useful in the fields of nano-electronics and opto-electronics.
• the invention also solves the problem of manufacturing such nano-objects on the surface of a large gap semiconductor, in particular silicon carbide.
• the substrates candidates for such an organization, are the substrates for which the diffusion barrier of. surface is anisotropic as a function of a parameter such as temperature, a mechanical stress
• Nano-objects are produced by controlling the very delicate balance between the adsorbate-adsorbate and adsorbate-substrate interactions (the adsorbate being the metal) and by controlling the diffusion barrier of the atoms of the metal.
• the invention makes it possible to obtain atomic wires and nanostructures of a metal, in particular silver, the direction of which is perpendicular to that of atomic lines, or atomic wires, of silicon which has been previously formed on the surface of a silicon carbide substrate.
• the present invention firstly relates to a set of nano-objects, in particular atomic wires, one-dimensional nano-structures and quantum dots, this set being characterized in that the nano-objects are made of a metal and formed on the surface of a substrate of a monocrystalline semiconductor material.
• This monocrystalline semiconductor material can be chosen from monocrystalline silicon carbide, monocrystalline diamond, monocrystalline covalent semiconductors and monocrystalline compound semiconductors.
• This substrate can be a monocrystalline substrate of silicon carbide in the cubic phase.
• the surface is a surface of cubic silicon carbide, rich in silicon ⁇ -SiC (100) 3x2.
• Nano-objects can be three-dimensional clusters of metal on the surface.
• the aggregates are distributed in an ordered fashion over the surface and thus form a network of metal studs.
• the surface is a surface of cubic silicon carbide, terminated Si ⁇ -SiC (100) c (4x2), and the nano-objects are parallel atomic wires or parallel nanometric one-dimensional bands of metal .
• the surface may include parallel atomic wires of Si, the atomic wires and one-dimensional bands of the metal being perpendicular to these atomic wires of Si.
• the surface may include passivated zones and non-passivated zones, the nano-objects being formed on these non-passivated zones of the surface.
• the present invention also relates to a method for manufacturing a set of nano-objects in which a surface of a substrate made of a monocrystalline semiconductor material is prepared and a metal is deposited on the surface thus prepared.
• This .semiconducteur monocrystalline material may be selected from the monocrystalline silicon carbide, monocrystalline diamond, covalent monocrystalline semiconductors and semiconductor monocrystalline compounds.
• This substrate can be a monocrystalline substrate of silicon carbide in cubic phase.
• the metal can be deposited at a temperature above room temperature.
• a surface of cubic silicon carbide, rich in ⁇ -SiC (100) 3 ⁇ 2 silicon is prepared and the metal is deposited on the surface thus prepared.
• a finished silicon carbide surface Si, ⁇ -SiC (100) c (4x2) is prepared.
• the metal is deposited at room temperature on the surface thus prepared and atomic wires of the metal are obtained by surface migration of the metal atoms along rows of Si-Si dimers from the surface c (4x2). are parallel to the rows of Si-Si dimers or silicon wires.
• a thermal annealing of the substrate can be carried out at a temperature below the total desorption temperature of the metal.
• the metal can be deposited by evaporation under vacuum or in an inert atmosphere. Passivated zones can be formed on the prepared surface and then the metal is deposited on non-passivated zones on this surface.
• the metal can be chosen from metals whose band is full, metals of the jellium type, alkali metals (in particular sodium and potassium) and transition metals.
• a laser can be used to obtain the desorption of metal either by thermal interaction of the beam emitted by this laser on the surface covered with metal, or by desorption of the metal, induced by electronic transitions (DIET ).
• DIET electronic transitions
• the surface can be a finished surface C of sp type, namely the ⁇ -SiC (100) c (2x2) surface.
• This surface can include atomic lines of C of sp3 type.
• a network of metal studs is formed on the surface of the substrate in monocrystalline semiconductor material, the material of the material is locally transformed substrate located under the pads and eliminating the network of pads to obtain a super-network of pads made of the transformed material.
• the local transformation of the material of the substrate is chosen from oxidation, nitriding and oxynitriding in order to obtain a super-network of studs made of the oxide, niture or oxynitride of the material.
• FIG. 1 is a schematic view of aggregates three-dimensional metal, obtained in accordance with the invention
• FIG. 2 is a schematic top view of metallic atomic wires, obtained in accordance with the invention and parallel to atomic lines of Si
• FIG. 3 is a schematic top view of wires metallic atoms and metallic one-dimensional bands, obtained in accordance with the invention and perpendicular to atomic lines of Si
• FIG. 4 is a schematic top view of such atomic wires and one-dimensional bands, obtained in accordance with the invention, on non-passivated areas of a silicon carbide surface
• FIG. 5 is a schematic view of a network of sodium aggregates obtained in accordance with the invention on an SiC substrate
• Figure 6 is a schematic sectional view of this substrate, carrying a super-network of studs silica obtained by a process in accordance with the invention
• - Figure 7 represents photographs of LEED of a clean surface ⁇ -SiC (100) 3x2 (A), of the same surface covered by aggregates of Na and organized in 3x1 network (B) and the same surface covered by • Na aggregates and organized into a 3x2 network (C).
• quantum dots By forming an image of the surface by STM or scanning tunneling microscopy, we see that the silver does not wet the surface and forms three-dimensional aggregates whose sizes range from 0.9nm to 3nm and are therefore likely to constitute quantum dots ("quantum dots").
• the number, size and spacing of these aggregates or islands can vary depending on the amount of silver deposited and the annealing temperatures. This mode of growth indicates a dominant interaction between silver atoms.
• FIG. 1 is a schematic top view of the surface 2 on which the aggregates 4 are formed.
• the deposit of silver takes place in an enclosure where the pressure is less than 2 ⁇ 10 -8 Pa and is for example 6 ⁇ 10 -9 Pa; the distance between the surface and the source of silver is approximately 15cm; the current passing through the silver source during the deposit is worth 4A; the deposit time is between 2 minutes and 8 minutes (8 minutes corresponding to approximately a silver monolayer); the deposit takes place leaving the sample of SiC at room temperature (approximately 20 ° C).
• the necessary annealing is carried out at approximately 500 ° C.
• FIG. 2 is a schematic top view of the surface 6 carrying the parallel rows 8 of Si-Si dimers and the atomic wires of metal 9, which are parallel to these rows.
• annealing is carried out below the total silver desorption temperature (700 ° C).
• the silver layer is selectively desorbed and the atoms remaining on the surface organize themselves to make parallel one-dimensional bands of silver, nanometric in size, or parallel atomic wires of silver.
• the direction of these atomic wires and of these one-dimensional bands is perpendicular to the rows of dimers.
• FIG. 3 is a schematic top view of the surface 6 carrying the parallel rows 8 of Si-Si dimers and the atomic silver wires 10 as well as the one-dimensional nanometric silver bands 12.
• the deposit of silver takes place in an enclosure where the pressure is equal to 2.1 ⁇ 10 ⁇ 9 Pa; the silver is deposited for 8 minutes by means of a silver source traversed by a current of 4A; during silver deposition, the sample is left at room temperature; after deposition, the annealing of the sample takes place by passing it through a current of 0.5A for 5 minutes.
• silver wires can be constructed perpendicular to the Si atomic wires (see document [5]). This is extremely important for building artificial nanoscale networks, which can be very useful in nanoelectronics.
• Silver can be replaced by other metals with a solid band, such as gold or copper, or by metals of the jellium type, such as aluminum.
• jellium-type metal is a metal whose electron gas is substantially homogeneous and whose positive ionic charges are substantially "spread" ("smeared") throughout the volume of the metal to give a background (“ background ”) positive and consistent.
• Silver can also be replaced by transition metals such as Mo,, Ta, Nb, Co, Fe, Mn, Cr, Ti for example.
• the invention makes it possible to dope or to manufacture nanostructures having, for example, advantageous magnetic properties in spin electronics.
• Silver can also be replaced by other metals such as alkali metals, which are remarkable catalysts for surface reactions with organic or inorganic molecules (see documents [1] and [2]).
• the alkali metals also have the remarkable property of considerably lowering the work of output of the electrons, and of reaching the regime of negative electro-affinity, that is to say of constituting natural emitters of electrons.
• the present invention allows this emission to be made from nanostructures of alkali metals (Cs, Rb, K or Na for example).
• this evaporation can be carried out at higher pressure, in an inert atmosphere (rare gas, etc.).
• the process which is the subject of the invention makes it possible to selectively control the migration or the desorption of the atoms of the metal (for example silver) by acting on the temperature.
• a variation of the latter acts on the movement of the Si-Si dimers on SiC or causes this movement.
• the surface of cubic SiC is prepared, finished Si ⁇ -SiC (100) c (4x2) and without the atomic lines of silicon, the metal is deposited and annealed below the total desorption temperature of the metal.
• atomic wires of the metal and / or nanometric one-dimensional bands of this metal are obtained. These atomic wires and these one-dimensional bands are parallel to each other and are perpendicular to the direction in which the parallel rows of Si-Si dimers would be formed.
• a prepared surface of a cubic SiC sample is locally passivated with hydrogen and the atomic wires and / or one-dimensional bands of the metal are formed in the non-passivated areas.
• Figure 4 is a schematic top view of the surface 14 passively passivated and thus comprising passivated zones, such as zone 15, and non-passivated zones 16 and 18.
• the parallel atomic lines of silicon, which are present in these zones 16 and 18, have the reference 20.
• the areas that are not to be passivated are covered with a photoresist layer and the latter is eliminated after passivation of the non-covered areas. Knowing a priori the direction of the rows of Si-Si dimers, it is possible to form rectangular non-passivated zones of which one of the sides is parallel to this direction.
• this surface is prepared in order to present, on an atomic scale, a controlled organization of c symmetry (4x2). This surface is then exposed to molecular hydrogen until saturation. Upon exposure to molecular hydrogen, the SiC is kept at room temperature.
• the cubic SiC is placed in a treatment enclosure, in which a pressure of less than 5 ⁇ 10 -10 hPa prevails, and heated by passing an electric current directly through this SiC substrate.
• the latter is heated for several hours at 650 ° C. and then brought several times to 1100 ° C. for one minute Using a source of silicon heated to 1300 ° C., several monolayers of silicon are deposited on the surface (100) of the cubic SiC.
• part of the deposited silicon is evaporated in a controlled manner until the surface has an organization on the atomic scale (reconstruction) of 3 ⁇ 2 symmetry. This symmetry of the surface can be controlled by electron diffraction.
• the surface is maintained at room temperature.
• the SiC surface is exposed until saturation (greater than 50L). This saturation can be monitored by a tunneling microscope or by a valence band photoemission technique.
• the Na aggregates are identified using a 3.1 eV plasmon which exactly corresponds to the energy of spherical Na aggregates. Results also suggest that sodium aggregates are regularly spaced and their size tends to decrease when their coverage rate increases. Indeed, for the largest deposits (of the order of the atomic monolayer up to several monolayers - atomic) and after gradual annealing up to 350 ° C, the diffraction pattern of slow electrons becomes very contrasted, thus showing that the Na aggregates are well organized and regularly spaced on the ⁇ -SiC (100) 3 ⁇ 2 surface.
• Self-organized quantum Na dots are thus formed by varying the balance between adsorbate-adsorbate and adsorbate-substrate interactions, by controlling the temperature and the quantity of metal deposited. This result is very important and the plots obtained differ very significantly from other quantum plots by the intrinsic properties of alkali metals such as sodium.
• these pads are produced on the surface of a semiconductor, which is unprecedented, and what is more, it is a large gap semiconductor.
• alkali metals such as Na have a very low electroaffinity. They considerably lower, by several electronvolts, the work function ("work function") of the surface and one can arrive at a negative electroaffinity regime (with the surface alone or exposed to oxygen), c i.e. a natural electron emitter, or a photoelectron emitter when the system is exposed to light.
• a comparable phenomenon is used for the manufacture of light amplifiers in night vision devices from gallium arsenide surfaces coated with Cs and oxygen.
• the polymer (respectively organometallic) studs which are discussed above, can also serve as anchoring points, on the surface where they are formed, for the molecules which have made it possible to form these studs.
• small quantities approximately of the order of langmuir
• inorganic or organic molecules for example hydrogen, oxygen, or any other molecule or element known to those skilled in the art as being capable of interacting with Na or alkali metals.
• a sample thus prepared is then placed in a vacuum chamber. In the latter, a pressure of approximately 10 ⁇ 9 Pa is established.
• Sodium is then deposited on the sample using a zeolite source, of the type which are sold by the SAES Getters company, after having perfectly degassed this source, so that the pressure increase in the enclosure during the deposition does not exceed 3 ⁇ 10 ⁇ 9 Pa. This gives sodium aggregates on the surface.
• the deposit takes place at room temperature
• Annealing is then carried out (at temperatures of a few hundred degrees, for example 350 ° C., for a period of a few seconds to a few minutes) of the surface of ⁇ -SiC (100) 3 ⁇ 2 covered with the sodium aggregates.
• These anneals optimize the number, size and position of these aggregates. They can be done by Joule effect, by passing an electric current through the sample of SiC and by controlling the temperature of this last using a pyrometer or a thermocouple for example.
• sodium was used to form the aggregates.
• sodium could be replaced by other alkali metals, more particularly potassium, Cs, Rb or alkaline earth metals such as Mg, Ca and Ba for example.
• a SiC substrate was used, which may be, in the context of the present invention, of cubic or hexagonal type, rich in Si and / or C.
• substrate by a diamond substrate or by a substrate made of a covalent semiconductor material, for example Si or Ge, or by a substrate made of a semiconductor material composed III-V (for example GaAs, InP, GaSb, GaP or InAs) or II-VI (for example CdTe, ZnO or ZnTe).
• III-V for example GaAs, InP, GaSb, GaP or InAs
• II-VI for example CdTe, ZnO or ZnTe
• the low-temperature thermal desorption which was discussed above, can be implemented in a range of temperatures from ambient temperature (about 25 ° C) to the desorption temperature of the metal considered on the substrate considered.

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