EP1801857A2 - Dispositifs de mémoire non volatile multibit et leurs procédés de fabrication - Google Patents

Dispositifs de mémoire non volatile multibit et leurs procédés de fabrication Download PDF

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Publication number
EP1801857A2
EP1801857A2 EP06126309A EP06126309A EP1801857A2 EP 1801857 A2 EP1801857 A2 EP 1801857A2 EP 06126309 A EP06126309 A EP 06126309A EP 06126309 A EP06126309 A EP 06126309A EP 1801857 A2 EP1801857 A2 EP 1801857A2
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EP
European Patent Office
Prior art keywords
control gate
gate electrodes
pair
fins
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP06126309A
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German (de)
English (en)
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EP1801857A3 (fr
Inventor
Yoon-Dong Park
Won-Joo Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of EP1801857A2 publication Critical patent/EP1801857A2/fr
Publication of EP1801857A3 publication Critical patent/EP1801857A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Definitions

  • Example embodiments of the present invention relate to semiconductor memory devices, for example, non-volatile memory devices having a floating node and/or a trap-type node as a storage node, and methods of fabricating the same.
  • Related art flash memory devices have a floating node such as a polysilicon film as a storage node.
  • Related art silicon-oxide-nitride-oxide-silicon (SONOS) memory devices have a trap-type node such as silicon nitride film as a storage node.
  • SONOS silicon-oxide-nitride-oxide-silicon
  • limited memory integration and/or speed may result from limitations in forming fine patterns.
  • a related art Fin-FET may use top and side surfaces of a fin structure as a channel region. Therefore, the Fin-FET may have a larger channel area as compared to a planar transistor, which may result in a higher current flow. As a result, the Fin-FET may provide higher performance than the planar transistor.
  • CMOS complementary metal-oxide-semiconductor
  • the related art fin memory cell uses an area of at least 2F X 2F to provide 2-bit operation when the gate length is 1 F, the area per bit is 2F 2 /bit. An area per bit of 2F 2 /bit may limit the performance of the fin memory cell.
  • Example embodiments of the present invention provide a non-volatile memory device that occupies less area per bit and may perform multi-bit operation.
  • Example embodiments of the present invention also provide a method of fabricating the NAND type non-volatile memory device.
  • a multi-bit non-volatile memory device may include a semiconductor substrate.
  • the semiconductor substrate may include a body and at least one pair of fins protruding above the body.
  • a first insulation layer may be formed on the body between the paired fins, and a plurality of control gate electrodes may extend across the first insulation layer and the fins and may at least partly cover upper portions of outer walls of the fins.
  • the control gate electrodes may be insulated from the semiconductor substrate.
  • a plurality of storage nodes may be interposed between the control gate electrodes and the fins and insulated from the semiconductor substrate.
  • the control gate electrodes may be sequentially paired into groups of two and a first distance between adjacent control gate electrodes included in respective adjacent pairs may be greater than a second distance between the control gate electrodes of each pair.
  • the NAND type multi-bit non-volatile memory device may further include a plurality of contact plugs contacting respective sidewalls near edges of the control gate electrodes.
  • the contact plugs contacting the control gate electrodes of each pair may be arranged on the same side, and the contact plugs contacting adjacent control gate electrodes included in respective adjacent pairs may be arranged at opposite sides.
  • a semiconductor substrate including a body and at least one pair of fins may be provided.
  • the fins may protrude above the body.
  • a first insulation layer may be interposed between the pair of fins.
  • a second insulation layer may be on a portion of the body at an outer side of the paired fins and may expose an upper portion of outer walls of the paired fins.
  • a plurality of storage nodes may be formed on upper portions of outer walls of the paired fins.
  • a plurality of preliminary control gate electrodes may be formed extending across the first insulation layer, the second insulation layer and the fins and may cover the storage nodes. The preliminary control gate electrodes may be spaced apart from each other by third insulation layers.
  • a plurality of pairs of control gate electrodes may be formed on respective sidewalls of the third insulation layers by forming a trench located in each of the preliminary control gate electrodes and extending across the paired fins.
  • the control gate electrodes may be sequentially paired into groups of two and a first distance between adjacent control gate electrodes included in respective adjacent pairs may be greater than a second distance between the control gate electrodes of each pair.
  • a plurality of contact plugs contacting respective sidewalls near edges of the control gate electrodes may be formed.
  • FIG. 1 is a schematic view of a non-volatile memory device according to an example embodiment of the present invention.
  • Non-volatile memory devices may be flash memories having a floating node, or a SONOS memory having a trap-type node.
  • a non-volatile memory device may have a NAND structure.
  • FIG. 1 illustrates a cell region of a NAND type non-volatile memory device, according to an example embodiment of the present invention.
  • bit lines BL1 through BL8 may be arranged in columns, and a plurality of word lines WL1 through WL10 may be arranged in rows.
  • the rows and columns may be interchanged.
  • the numbers of bit lines and word lines shown in FIG. 1 are only examples, and are not intended to be limiting in any way.
  • First ends of the bit lines BL1 through BL8, for example, portions of the bit lines BL1 through BL8 located at the outer side of the tenth word line WL10, may be connected to a common source line (not shown).
  • a ground section line (not shown) forming a ground section transistor may be interposed between the tenth word line WL10 and the common source line.
  • a string section line (not shown) forming a string section transistor may be located at the outer side of the first word line WL1.
  • the common source, ground selection and string selection lines are well known in the art, and therefore, a detailed description of these components will be omitted for the sake of brevity.
  • First and second device isolating insulation layers 125 and 135 may be alternately located between the bit lines BL1 through BL8.
  • the first device isolating insulation layer 125 may be located between the first and second bit lines BL1 and BL2
  • the second device isolating insulation layer 135 may be located between the second and third bit lines BL2 and BL3.
  • the bit lines BL1 through BL8 may be paired such that a bit line located on each side of each respective first device isolating insulation layer 125 makes a pair.
  • the first and second bit lines BL1 and BL2 may make a first pair
  • the third and fourth bit lines BL3 and BL4 may make a second pair.
  • the other word lines WL5 through WL10 may also be paired.
  • a first pair of contact plugs 175a and 175b may be formed on edge sidewalls of a first pair of word lines WL1 and WL2, respectively.
  • the first pair of contact plugs 175a and 175b corresponding to the first pair of word lines WL1 and WL2 may be formed on the left side of the bit lines BL1 through BL8.
  • other pairs of contact plugs 175a and 175b may be formed on second to fifth pairs of word lines WL3 and WL4, WL5 and WL6, and WL9 and WL 10.
  • the first pair of contact plugs 175a and 175b of the first pair of word lines WL1 and WL 2 may be formed on the same side.
  • the second pair of contact plugs 175a and 175b of the second pair of word lines WL3 and WL4, which are adjacent to the first pair of word lines WL1 and WL2, may be formed on the opposite side to the first pair of contact plugs 175a and 175b.
  • the first pair of contact plugs 175a and 175b of the first pair of word lines WL1 and WL2 may be formed on the left side
  • the second pair of contact plugs 175a and 175b of the second pair of word lines WL3 and WL4 may be formed on the right side.
  • the contact plugs 175a and 175b may be paired and arranged in a zigzag or staggered pattern.
  • the staggered arrangement of the pairs of contact plugs 175a and 175b may increase integration of devices, according to example embodiments of the present invention.
  • the distance between the pairs of word lines may increase to suppress (e.g., prevent) short circuits between the pairs of contact plugs 175a and 175b. This may reduce the integration of the device.
  • the pairs of contact plugs 175a and 175b may be arranged in a staggered pattern and the distance between the pairs of word lines may decrease.
  • the second pair of bit lines BL3 and BL4 and the first pair of word lines WL1 and WL2 may be located in an area C and may form a unit cell 100 of the NAND cell shown in FIG. 1.
  • FIG. 2 is a perspective view of a unit cell of a non-volatile memory device, according to an example embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2.
  • FIG. 4 is a cross-sectional view taken along line II-II of FIG. 2.
  • a semiconductor substrate 110 may include a body 102 and a pair of fins 105a and 105b.
  • the pair of fins 105a and 105b form the second pair of bit lines BL3 and BL4, and a pair of control gate electrodes 155a and 155b form the first pair of word lines WL1 and WL2.
  • the first device insulation layer 125 may be formed in between the fins 105a and 105b.
  • a second device isolating insulation layer 135 may be formed on the body 102 to contact the outer walls of the fins 105a and 105b.
  • the control gate electrodes 155a and 155b may extend across the fins 105a and 105b and the first and second device isolating insulation layers 125 and 135.
  • the control gate electrodes 155a and 155b may at least partly cover the upper portions of the outer walls of the fins 105a and 105b, and may be insulated from the semiconductor substrate 110.
  • Storage nodes 150a and 150b may be located between the upper portions of the outer walls of the fins 105a and 105b and the control gate electrodes 155a and 155b.
  • the fins 105a and 105b may protrude upwards from the body 102 of the semiconductor substrate 110 and may be spaced apart from each other.
  • the fins 105a and 105b may be spaced apart from each other in a direction X1 and extend in a direction X2.
  • the semiconductor substrate 110 may be formed of, for example, bulk silicon, bulk silicon-germanium or any other semiconductor material having similar or substantially similar properties.
  • the semiconductor substrate may be formed in a multi-layer structure.
  • the multilayer structure may have a first layer formed of, for example, bulk silicon or bulk silicon-germanium and a second layer (e.g., a second epitaxial layer) formed of, for example, silicon or silicon-germanium.
  • the fins 105a and 105b may be formed of the same or substantially the same material as the body 102. Alternatively, in at least one other example embodiment of the present invention, the fins 105a and 105b may be formed of a different material, for example, an epitaxial layer formed on the body 102.
  • the first device insolating insulation layer 125 may be formed between the fins 105a and 105b, and the second device isolating insulation layer 135 may be formed on the body 102 to contact the outer walls of the fins 105a and 105b.
  • the second device isolating insulation layer 135 may cover a lower portion of the outer walls of the fins 105a and 105b, but may expose an upper portion of the outer walls of the fins 105a and 105b.
  • the first and second device isolating insulation layers 125 and 135 may isolate the fins 105a and 105b from one another and from other fins (not shown).
  • each of the first and second device isolating insulation layers 125 and 135 may include a silicon oxide layer or a layer formed of any suitable semiconductor material with similar or substantially similar properties.
  • control gate electrodes 155a and 155b may be formed on the semiconductor substrate 110 having an SOl-like structure.
  • the SOl-like structure differs from related art SOl structures in that the fins 105a and 105b may be connected to the body 102 in a direction X3, whereas an active region of related art SOl structures is floated from the body. Accordingly, the structure of the semiconductor substrate 110, according to an example embodiment of the present invention, is referred to as an SOl-like structure, which will be described in more detailed below.
  • Gate insulation layers 140a and 140b may be formed on the outer walls and top surface of the fins 105a and 105b.
  • the gate insulation layers 140a and 140b may function as tunneling passages and will be referred to as tunneling insulation layers.
  • the gate insulation layers 140a and 140b may be formed of a silicon oxide layer, a silicon nitride layer, a high-K dielectric layer, a multi-layer structure including one or more of these layers or any other suitable material or structure.
  • the storage nodes 150a and 150b may be interposed between portions of the gate insulation layers 140a and 140b and portions of the control gate electrodes 155a and 155b.
  • the storage nodes 150a and 150b may be formed on the upper portions of the outer walls of the fins 105a and 105b. Alternatively, in at least one other example embodiment of the present invention, the storage nodes 150a and 150b may extend to the top surfaces of the fins 105a and 105b.
  • Each of the storage nodes 150a and 150b may include a polysilicon layer, a silicon-germanium layer, a silicon or metal area (e.g., dot), and/or a nano-crystal or a silicon nitride layer.
  • Storage nodes 150a and 150b including, for example, the polysilicon layer or the silicon-germanium layer may be used as floating nodes.
  • the storage nodes 150a and 150b including, for example, the silicon or metal area, the nano-crystal or the silicon nitride layer may be used as charge trap nodes.
  • Channels functioning as conductive passages for charges may be formed at upper end portions of the outer walls of the fins 105a and 105b and near the top surfaces of the fins 105a and 105b.
  • the channel may not be formed on the inner walls of the fins 105a and 105b, between which the first device isolating insulation layer 125 is formed.
  • the primary (e.g., major) conductive passages of the charges may be formed on the outer walls of the fins 105a and 105b based on (or considering) a relative area.
  • the area of the channel may be adjusted.
  • the operating current e.g., the speed of the non-volatile memory device
  • the performance of the non-volatile memory device may improve.
  • Impurity regions 170 may be formed near the surfaces of the fins 105a and 105b at both sides of the control gate electrodes 155a and 155b.
  • the impurity regions 170 may serve as source and drain regions.
  • the impurity regions 170 may be connected to the semiconductor substrate 110, for example, by diode-junctions.
  • the semiconductor substrate 110 may be doped with p-type impurities.
  • the n-type and p-type impurities may be interchanged.
  • the control gate electrodes 155a and 155b may extend in the direction X1 and may be spaced apart from each other in a direction X2.
  • An intergate insulation layer 160 may be formed (or interposed) between the control gate electrodes 155a and 155b.
  • the intergate insulation layer 160 may protrude or extend above the top surfaces of the control gate electrodes 155a and 155b.
  • each of the control gate electrodes 155a and 155b may include a polysilicon layer, a metal layer, a metal silicide layer or a multi-layer including the polysilicon, metal and/or metal silicide layers.
  • the intergate insulation layer 160 may include, for example, a silicon oxide layer or a layer or layer structure having similar insulating properties.
  • the unit cell 100 may further include a blocking insulation layer (not shown) for insulating the control gate electrodes 155a and 155b from the storage nodes 150a and 150b.
  • the blocking insulation layer may be formed between the storage nodes 150a and 150b and the control gate electrodes 155a and 155b, and between the first device isolation insulation layer 125 and the control gate electrodes 155a and 155b.
  • the blocking insulation layer may include, for example, a silicon oxide layer or a layer or layer structure having similar insulating properties.
  • the expansion of a depletion region formed on the fins 105a and 105b may be limited.
  • the expansion of the depletion region may be limited.
  • the depletion region may be limited in the direction X1 (the direction of the widths of the fins 105a and 105b), but may extend in the direction X3.
  • the widths of the fins 105a and 105b are reduced, the influence or function of the depletion region formed in the direction X3 may be suppressed.
  • the fins 105a and 105b may form an SOl-like structure similar to the SOl structure. Therefore, an off-current and a junction leakage current, generated, for example, by the expansion of the depletion region, may be reduced.
  • the gate length W1 of each of the control gate electrodes 155a and 155b may be about 0.25F
  • the width W2 of each of the fins 105a and 105b may be about 0.25F
  • the width W3 of the first device isolating insulation layer 125 may be about 0.5F.
  • the width of the unit cell 100 in the direction X1 may be about 2F.
  • the distance between the control gate electrodes 155a and 155b which corresponds to the distance between the second pair of word lines WL3 and WL4, may be about 0.5F.
  • the distance between adjacent word lines included in respective adjacent pairs may be two times the distance between the paired word lines.
  • FIGS. 5 through 14 are sectional views illustrating a method of fabricating a non-volatile memory device according to an example embodiment of the present invention.
  • a non-volatile memory device fabricated according to this embodiment may correspond to the unit cell 100 depicted in FIG. 2.
  • like reference numbers refer to like parts.
  • a first mask pattern (e.g., a hard mask pattern) 115 may be formed on the semiconductor substrate 110.
  • the semiconductor substrate 110 may be formed of, for example, bulk silicon or bulk silicon-germanium.
  • the semiconductor substrate may have a multi-layer structure including a layer formed of bulk silicon or bulk silicon-germanium, and an epitaxial layer formed of silicon or silicon-germanium.
  • the first mask pattern 115 may be formed to expose a region where a first trench 120 may be formed.
  • the first mask pattern 115 may be formed in a line pattern extending straight or substantially straight. Although two straight lines are illustrated in FIG. 5, the line pattern may include more than two straight lines.
  • the first mask pattern 115 may be formed by forming a first mask layer (e.g., hard mask layer (not shown)) on the semiconductor substrate 110 and patterning the first mask layer.
  • the patterning may be performed using, for example, photolithography or etching.
  • the first mask layer may be formed of a material having an etch selectivity relative to the semiconductor substrate 110.
  • the first mask layer may include, for example, a nitride layer or an oxynitride layer.
  • the semiconductor substrate 110 may be etched using the mask pattern 115 as an etching mask, to form the first trench 120.
  • the depth of the first trench 120 may be selected according to the height of the fins (e.g., 105a and 105b of FIG. 8). Although only one first trench 120 is illustrated in FIG. 1, a plurality of first trenches 120 may be formed, for example, in an array.
  • the first device isolating insulation layer 125 may be formed to fill the first trench (e.g., 120 of FIG. 5).
  • an insulation layer (not shown) for the first device isolating insulation layer 125 may be deposited to fill the first trench 120.
  • the insulation layer may include, for example, an oxide layer.
  • the insulation layer may be etched using etch-back or chemical mechanical polishing (CMP) until the mask pattern (115 of FIG. 15) is exposed, thereby forming the first device isolating insulation layer 125.
  • CMP chemical mechanical polishing
  • the first mask pattern 115 may be selectively removed, leaving the first device isolating insulation layer 125 filling the first trench (120 of FIG. 2) in the semiconductor substrate 110 and protruding or extending above the top surface of the semiconductor substrate 110.
  • a first insulation spacer 130 may be formed on each sidewall of the protruding portion of the first device isolation insulation layer 125.
  • the first insulation spacers 130 may cover portions of the semiconductor substrate 110 where the fins (105a and 105b of FIG. 8) may be formed.
  • the first insulation spacers 130 may be formed by depositing and etching a material layer.
  • a first insulation spacer layer (not shown) may be formed on the first device isolating insulation layer 125.
  • the first insulation spacer layer may be etched (e.g., anisotropically etched) to form the first insulation spacer 130 on each sidewall 127 of the protruding portion of the first device isolating insulation layer 125.
  • the first insulation spacers 130 may be formed on the sidewalls of the first device isolating insulation layer 125, for example, using a self-alignment or any other suitable method.
  • the width of the first insulation spacer 130 may be adjusted by controlling the thickness of the first insulation spacer layer.
  • the first insulation spacer layer may include a nitride layer, an oxynitride layer or any other suitable layer.
  • the exposed portion of the semiconductor substrate 110 may be etched to form a second trench 133 using the first insulation spacers (130 of FIG. 7) as an etching mask.
  • the semiconductor substrate 110 may include the body 102 and the pair of fins 105a and 105b.
  • the widths of the fins 105a and 105b may be determined based on the widths of the first insulation spacers 130. For example, by adjusting the widths of the first insulation spacers 130, the widths of the fins 105a and 105b may be adjusted, and fins 105a and 105b each having a sub-micro-scale width may be formed. The side surface of each of the fins 105a and 105b may contact and be supported by the first device isolating insulation layer 125, thereby enabling the fins 105a and 105b to be formed higher and thinner, while suppressing the likelihood that the fins 105a and 105b collapse during or after fabrication.
  • a plurality of device isolating insulation layers 125 may be formed, for example, in an array, and pairs of fins 105a and 105b may be formed on the sidewalls of each device isolating insulation layers 125.
  • the second device insulation layer 135 may be formed in the second trench (133 of FIG. 8).
  • the second device insulation layer 135 may include, for example, a silicon oxide layer or any other similar insulation layer.
  • an insulation layer (not shown) for the second device isolating insulation layer may be formed on the structure depicted in FIG. 8. The insulation layer may be etched until the fins 105a and 105b are exposed, thereby forming the second device isolating insulation layer 135.
  • the second device insulation layer 135 may be selectively etched to expose the upper portions of the fins 105a and 105b.
  • a second mask pattern e.g., hard mask pattern (not shown)
  • the second device insulation layer 135 may be selectively etched using the second mask pattern as an etching mask.
  • the gate insulation layers 140a and 140b may be formed on the exposed portion of the fins 105a and 105b.
  • the gate insulation layers 140a and 140b may be formed on the top portions and the outer side of the upper portions of the fins 105a and 105b.
  • the gate insulation layers 140a and 140b may be formed, for example, by thermally oxidizing the fins 105a and 105b.
  • Storage nodes 150a and 150b at least partly covering the gate insulating layers 140a and 140b may be formed to cover portions of the gate insulation layers 140a and 140b.
  • the storage nodes 150a and 150b may be formed at the outer sides of the fins 105a and 105b.
  • the storage node layers 150a and 150b may be formed by depositing a storage node layer (not shown) and etching the storage node layer using, for example, anisotropic dry etching, or any other suitable method.
  • Each of the storage nodes 150a and 150b may include a polysilicon layer, a silicon-germanium layer, a silicon or metal area or dot, a nano-crystal, a silicon nitride layer, or a layer of material having similar or substantially similar properties.
  • a blocking insulation layer (not shown) covering the storage nodes 150a and 150b may be formed.
  • the blocking insulation layer may be formed by depositing a silicon oxide layer on the resultant structure on which the storage nodes 150a and 150b are formed.
  • Preliminary control gate electrodes 155 may be formed to cover the storage nodes 150a and 150b.
  • the preliminary control gate electrodes 155 may extend across the fins 105a and 105b and the first and second device insulation layers 125 and 135.
  • the preliminary control gate electrodes 155 may be spaced apart from each other in the direction in which the fins 105a and 105b extend.
  • a preliminary control gate electrode layer (not shown) may be formed on the resultant structure on which the storage nodes 150a and 150b are formed.
  • a third mask pattern (e.g., hard mask pattern) 157 may be formed and the preliminary control gate electrode layer may be etched using the third mask pattern 157 as a mask pattern to form the preliminary control gate electrodes 155.
  • the intergate insulation layer 160 may be formed between the preliminary control gate electrodes 155.
  • the integrate insulation layer 160 may protrude or extend above the preliminary control gate electrodes 155.
  • an insulation layer (not shown) for the intergate insulation layer 160 may be formed on the structure depicted in FIG. 11, and the insulation layer may be etched until the mask pattern (157 of FIG. 11) is exposed to form the intergate insulation layer 160.
  • the third mask pattern 157 may then be removed.
  • the intergate insulation layer 160 may include, for example, a silicon oxide layer or a layer of a material having similar or substantially similar properties.
  • second insulation spacers 165 may be formed on both sidewalls of the protruding portion of the intergate insulation layer 160.
  • a second insulation spacer layer (not shown) may be formed on the structure depicted in FIG. 12, and the second insulation spacer layer may be etched using, for example, an anisotropic etching (or any other similar) method, to form the second insulation spacers 165.
  • the second insulation spacers 165 may each include, for example, a silicon nitride layer, although any other similar or substantially similar insulating layer may be used.
  • a third trench may be formed on each of the preliminary control gate electrodes 155 by etching the preliminary control gate electrodes 155 using the second insulation spacers (165 of FIG. 13) as an etching mask.
  • the pair of control gate electrodes 155a and 155b arranged on respective sidewalls of the intergate insulation layer 160 may be formed.
  • the second insulation spacers 165 may allow the third trench region to be exposed and/or limit the widths of the control gate electrodes 155a and 155b.
  • the control gate electrodes 155a and 155b may be supported by the intergate insulation layer 160, which may suppress the likelihood of collapse when the control gate electrodes 155a and 155b have a micro-scale line width.
  • the second insulation spacers 165 may be removed. Alternatively in another example embodiment of the present invention, the second insulation spacers 165 may be left in place.
  • impurity regions (170 of FIG. 4) may be formed near the surface of the fins 105a and 105b between the control gate electrodes 155a and 155b.
  • the impurity region under the intergate insulation layer 160 may be formed before the intergate insulation layer 160 is formed.
  • the impurity region formed at the outer sides of the control gate electrodes 155a and 155b may be formed after the control gate electrodes 155a and 155b are formed.
  • the contact plugs may be formed on the sidewalls near the edges of the control gate electrodes 155a and 155b.
  • the contact plugs may correspond to the contact plugs 175a and 175b formed near the edges of the word lines WL1 and WL2 (see, e.g., FIG. 1).
  • the contact plugs 175a and 175b may be paired and the pairs of contact plugs 175a and 175b may be formed in zigzag or staggered arrangement or pattern.
  • the widths of the gate electrodes 155a and the fins 105a and 105b illustrated in FIG. 14 may be the same or substantially the same as those described with respect to FIGS. 3 and 4.
  • the distance (W5 in FIG. 3) between the control gate electrodes 155a and 155b which may correspond to the distance between the paired word lines (WL3 and WL4 of FIG. 1), may be about 0.5F, and the distance between adjacent word lines included in respective adjacent pairs may be two times the distance between the paired word lines.
EP06126309A 2005-12-20 2006-12-18 Dispositifs de mémoire non volatile multibit et leurs procédés de fabrication Withdrawn EP1801857A3 (fr)

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US20050260814A1 (en) * 2004-05-24 2005-11-24 Cho Eun-Suk Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same

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EP3823024A1 (fr) * 2019-11-15 2021-05-19 Renesas Electronics Corporation Dispositif à semiconducteur
WO2021194552A1 (fr) * 2020-03-24 2021-09-30 Silicon Storage Technology, Inc. Cellules de mémoire non volatile à grille divisée de finfet à grille flottante améliorée pour couplage capacitif de grille flottante
US11362100B2 (en) 2020-03-24 2022-06-14 Silicon Storage Technology, Inc. FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling

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US7842995B2 (en) 2010-11-30
US20070141781A1 (en) 2007-06-21
CN1988160A (zh) 2007-06-27
KR100668350B1 (ko) 2007-01-12
CN100590876C (zh) 2010-02-17
JP2007173800A (ja) 2007-07-05

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