EP1647053A2 - Verfahren zur herstellung eines anisotrop leitendes films - Google Patents

Verfahren zur herstellung eines anisotrop leitendes films

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Publication number
EP1647053A2
EP1647053A2 EP04767896A EP04767896A EP1647053A2 EP 1647053 A2 EP1647053 A2 EP 1647053A2 EP 04767896 A EP04767896 A EP 04767896A EP 04767896 A EP04767896 A EP 04767896A EP 1647053 A2 EP1647053 A2 EP 1647053A2
Authority
EP
European Patent Office
Prior art keywords
conductive
layer
inserts
manufacturing
conductive inserts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04767896A
Other languages
English (en)
French (fr)
Inventor
Jean Brun
Christiane Puget
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1647053A2 publication Critical patent/EP1647053A2/de
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01022Titanium [Ti]
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    • H01L2924/01023Vanadium [V]
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    • H01L2924/01024Chromium [Cr]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
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    • H01L2924/01057Lanthanum [La]
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    • H01L2924/01073Tantalum [Ta]
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    • H01L2924/01074Tungsten [W]
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Definitions

  • the invention relates to a method for manufacturing an anisotropic conductive film on a substrate.
  • the invention also relates to a method for manufacturing a semiconductor chip provided with an anisotropic conductive film.
  • the interconnection pads offer the ability to connect high density interconnection chips in a reduced volume, while maintaining or improving electrical performance, in particular by reducing the effects of self-inductance.
  • These techniques are used, for example, in cell phones and, more generally, in multimedia devices. In particular, these techniques allow high speed data transmission, compared to the wire bonding method.
  • the “flip-chip” type techniques the technology using fusible microbeads is the one that currently predominates. This technology is based on the implementation of a process on a complete wafer of semiconductor material requiring two levels of lithography: a first level to define the metallurgy for bonding microbeads and a second level dedicated to the electrolytic deposition of fusible materials.
  • the ACF technique relates to conductive films made of conductive particles incorporated in an insulating film or of metallic inserts included in an insulating film.
  • ACF films with conductive particles incorporated in an insulating film are the best known. This type of film is based on a random distribution of conductive particles in a polymer matrix. The conductive particles typically have a diameter of a few micrometers. These are either metal coated polymer beads, or metal beads which can be, for example, nickel or silver.
  • the interconnection is obtained by bonding the film between the substrate and the chip, bonding being followed by thermocompression.
  • FIG. 1A The interconnection of a chip and a substrate using a film with conductive particles is shown in FIG. 1A.
  • a chip 1 provided with conductive pads 5 is connected to a substrate 2 provided with conductive pads 7.
  • An ACF film consisting of an insulating film 3 in which are incorporated conductive particles 4 is placed between the chip and the substrate. Bosses 6 establish contact between the conductive pads and the ACF film.
  • This type of interconnection leads to a relatively high electrical contact resistance, which reduces the scope of its fields of application.
  • a known application is, for example, the field of flat screens.
  • the above-mentioned drawback has led to the design of ACF films with through metal inserts.
  • ACF film with through metal inserts is based on the orderly insertion of metallic microstructures into a sheet of polymer.
  • the interconnection of a chip and a substrate using a film with through metal inserts is shown in FIG. 1B.
  • the ACF film consists of an insulating film 8 in which are placed metal inserts 9.
  • a strong redundancy in the number of contacts per pad ensures a homogeneous contact with low resistivity and allowing high currents to pass.
  • the use of ACF films causes several problems, including that of the reliability of the electrical contact. Indeed, oxidized layers are formed on the ends of the metal inserts and on the interconnection pads of the chip, which leads to greatly reducing the quality of the electrical contacts.
  • the fusible material is liable to creep during its redesign and, on leaving, to short-circuit the metal inserts.
  • impurities can be reported between the film and the chip or between the film and its substrate during hybridization.
  • Another problem is related to the handling of thin ACF films. The films are produced on a rigid sacrificial support which must be separated from the ACF film before hybridization. It is then necessary to assemble three elements, the chip, the film and the substrate.
  • the present invention does not have the drawbacks mentioned above.
  • the invention relates to a method of manufacturing an anisotropic conductive film comprising a layer of electrically insulating material and through conductive inserts.
  • the process is characterized in that it comprises the following stages: a) formation on a substrate of at least one layer of material having through holes, said layer being called perforated layer, b) filling through holes to form conductive inserts , and being characterized in that it further comprises the production of a mask partially covering a first end of the conductive inserts and the etching of the unmasked part of the end of the conductive inserts so as to obtain conductive inserts with ends In tip.
  • step b) of filling being carried out by electrolysis comprises the deposition of a conductive layer on the substrate, prior to the formation of the perforated layer, this layer being etched after the production of conductive inserts.
  • This layer can be etched (generally wet or dry) at any possible time during the process once the conductive inserts have been made; the layer is not necessarily etched immediately after the step of filling the through holes.
  • the perforated layer of step a) is produced by depositing a layer of photosensitive resin, the exposure of this resin through a mask and the development of the latter to obtain the through holes.
  • the perforated layer can also be a layer of material deposited by serigraphy, for example a polymer or even a metal, or a layer produced by thermal oxidation and etched to obtain the through holes, or a preformed layer to produce the through holes and transferred onto the substrate.
  • the perforated layer of step a) is removed after filling step b) and a step of depositing an insulating layer is carried out on the substrate to form the insulating layer of the anisotropic conductive film.
  • a passivation layer covers the substrate in which accommodates at least one contact pad. This embodiment is used in particular when the conductive film is produced directly on the substrate which must be connected with another component.
  • the production of the mask partially covering one end of the conductive inserts and the etching of the non-masked part comprises the following steps:
  • the production of the mask partially covering one end of the conductive inserts and the etching of the non-masked part comprises the following steps:
  • the step of filling the through holes is carried out so that the first end of each conductive insert has the shape of a nail head.
  • the first end of each conductive insert may be in the form of a hat or a mound in the form of a nail head.
  • a protective layer is formed on the tips of the conductive inserts.
  • the protective layer is advantageously an antioxidant layer.
  • the antioxidant layer is preferably a gilding carried out by a technique chosen from an autocatalytic deposit, an electrolysis or a gold spray.
  • the transfer of the material capable of being transferred and intended to protect the end of the conductive inserts can advantageously be a polymer or a resin whose adhesive properties are better on the conductive inserts than on the buffer substrate on which the material is found before transfer.
  • the transfer of the material capable of being transferred to a first end of the conductive inserts can advantageously be carried out by exerting pressure on the buffer substrate on which the material is located before the transfer. This transfer can be done with or without heating.
  • the filling of the through holes is carried out by a technique chosen from an auto catalytic deposition, electrolytic growth, chemical or physical deposition, and impregnation.
  • prior to step a) is deposited on the substrate one or more layers capable of allowing, after obtaining the film, to separate it from the substrate and to ensure the mechanical rigidity of the assembly.
  • the invention also relates to a method for manufacturing a semiconductor chip. This method comprises a method of manufacturing an anisotropic conductive film on a semiconductor wafer according to the invention, as well as a step of cutting the structure thus obtained.
  • the anisotropic conductive film can be produced directly on a wafer of semiconductor material in which active and / or passive elements of the integrated circuit type are present.
  • the anisotropic conductive film obtained according to the method of the invention is able to connect at least two components, the conductive film can be produced on at least one of said components and said component can contain conductive zones or be completely driver.
  • the method according to the invention ensures an excellent electrical connection between the metals brought into contact.
  • the conductive inserts can be connected to the interconnection pads almost irreversibly thanks to a non-fusible hanging material.
  • the anisotropic conductive film according to the invention makes it possible to make contacts between chip and substrate having low electrical resistance, good mechanical solidity and good reliability.
  • FIG. 1A and 1B already described, show the interconnection of a chip and a substrate according to the prior art, using, respectively, an anisotropic conductive polymer film with conductive particles and a polymer film - anisotropic conductor with conductive inserts;
  • FIG. 2 shows a chip equipped with an anisotropic conductive polymer film according to the invention
  • FIG. 3A-3I show a method of manufacturing anisotropic conductive polymer film on semiconductor wafer according to the invention
  • the invention makes it possible to produce a semiconductor chip comprising, on one side, a passivation layer in which is formed at least one opening revealing a connection pad.
  • This chip includes, on the passivation layer and the connection pad, an anisotropic conductive film formed from conductive inserts enclosed in an electrically insulating material, each conductive insert having a first end projecting from the electrically insulating material and a second end being brought into contact with the passivation layer or the stud connection via a conductive element.
  • the first ends of the conductive inserts are in the form of points.
  • the electrically insulating material can be a polyimide, a thermoplastic material, a photosensitive resin or an adhesive.
  • the electrically insulating material can be a fusible glass.
  • FIG. 2 represents an example of a semiconductor chip equipped with an anisotropic conductive polymer film according to the invention.
  • a chip 10 is provided with an interconnection pad 11 placed in an opening of a passivation layer 12.
  • a conductive film 13 comprising a layer of electrically insulating material 14 in which are placed conductive inserts 15 covers the passivation layer 12 and the connection pad 11.
  • a conductive insert 15 (for example a metal insert) has a first end which projects out of the insulating film 14 and a second end connected by a conductive element 16 to the passivation layer 12 or to the stud driver 11.
  • the conductive element 16 consists of a metal chip 17 and a fastening element 18.
  • the process for manufacturing a conductive polymer film on a semiconductor wafer according to the invention will now be described with reference to FIGS. 3A -3I.
  • the method is implemented from a wafer of semiconductor material.
  • a semiconductor wafer T is covered, on one side, with a passivation layer 12 in which are made openings revealing connection pads 11 (cf. FIG. 3A).
  • the first step of the process is the deposition in full layer of a conductive and adherent material 19 on the passivation layer 12 and the connection pads 11 (cf. FIG. 3B).
  • the conductive and adherent material 19 is, for example, Ti, Cr, W, Ta, etc. This step is preferably carried out after pickling the surface of the pads.
  • the metal layer 20 is intended to serve as an electric current supply layer at the time of the electrolytic growth of the conductive inserts.
  • a layer of photosensitive polymer 21 of the resin type is then deposited on the metal layer 20 (cf. FIG. 3D).
  • the thickness of the photosensitive polymer layer 21 is between a few ⁇ m and several tens of ⁇ .
  • the layer 21 is then exposed through a mask in order to form through holes 22 (cf. FIG. 3E). Typically the holes can have a depth of a few ⁇ m to several tens of ⁇ m, depending on the thickness of the layer 21.
  • the layer in which the through holes are formed may be a layer of material deposited by screen printing, for example a polymer or even a metal, or a layer produced by thermal oxidation and etched to obtain the holes, or even a preformed layer for make the holes and transferred to the substrate.
  • the holes formed in the previous step are then filled with one or more conductive materials (Cu, Ni, Ti, Cr, W, SnPb, Au, Ag, etc.), for example electrolytically, to form conductive inserts 23 (cf. figure 3F).
  • the inserts can therefore be formed from a single conductive material or from several superimposed conductive materials. These holes can be filled electrolytically.
  • the plate on which was deposited layer 21 pierced with through holes 22 (that is to say layer 20) is connected to the cathode, and the voltage is of the order of 2V for a current of 10mA.
  • the electrolyte used is a mixture of sulfate and chloride of Ni.
  • the filling of the holes can also be done by electroless plating. In this case, we start by zincating the surfaces to be coated in basic medium, 26
  • the autocatalytic deposition is carried out in a specific bath.
  • the resin is then removed, for example by dissolution, (cf. FIG. 3G) and the metal layers deposited in full layer are selectively etched in the zones located between the inserts (cf. FIG. 3H). Note that these metal layers can be etched at any time during the process once the inserts have been made.
  • the connection pads 11 are then electrically isolated from each other. This step can be carried out dry or chemical, the latter being preferred.
  • An electrically insulating material 24 is then deposited on the plate, partially covering the metal inserts (cf. FIG. 31). In the case where the electrically insulating material completely covers the inserts, an engraving is carried out to update them.
  • This material is preferably a polymer such as a polyimide, a thermoplastic material, a photosensitive resin or any type of adhesive. It is also possible to spread a fusible glass commonly called "Spin On Glass". Recall that this step of isolating the conductive inserts is implemented in particular when the perforated layer is not compatible with the insulation of the inserts and / or obtaining their asymmetry by assembly.
  • the conductive inserts have a pointed end allowing an improvement in the electrical contact of the anisotropic conductive polymer film and of the substrates on which it is desired to transfer the chips.
  • the method according to the variant of the invention comprises additional steps between the step of forming the conductive inserts (cf. FIG. 3F) and the step of removing the photosensitive polymer layer (cf. FIG. 3G).
  • the step of forming the conductive inserts is followed here by the deposition of a photosensitive resin 25 on all of the inserts (cf. FIG. 4A).
  • the photosensitive resin is exposed through a mask so that only one resin pellet 26 remains at the top of each insert (cf. FIG. 4B). It is specified that the resin 21 is hardened by annealing at 150 ° C for 5 minutes before depositing the photosensitive resin. Isotropic etching, for example wet or dry (for example dilute nitric acid for nickel inserts), inserts are then produced (cf. FIG. 4C) until the resin pellets are removed (cf. FIG. 4D). A point 27 then appears at the end of each insert. The process then continues according to the steps mentioned above, namely, removal of the photosensitive polymer layer and selective etching of the metal layers deposited in full layer (cf. FIG. 4E).
  • the step of forming the conductive inserts is carried out according to the same method as that seen above, with the difference that the conductive material or materials forming the inserts extend beyond the top of the hole so that the ends of the inserts have a shape nail head (see Figure 5A).
  • a resin 25 on all of the inserts.
  • a substrate A Si, glass, metal or polymer
  • Resin can be a photosensitive resin used in microelectronics or any polymer whose adhesive properties will be better on the metal inserts than on the substrate A.
  • the resin 25 is transferred to the inserts, with or without heating, by exerting a pressure on the buffer substrate A (cf. Figure 5C). For example, if the substrate A has a diameter of 100 mm, a pressure of 10 kg will be exerted. And the substrate A is removed (cf. FIG. 5D). An isotropic etching of the end of the inserts is then carried out so as to form inserts with a pointed end (cf. FIG. 5E). Etching can be carried out, for example, wet or dry. For example, if the material constituting the inserts is made of nickel, the etching solution will consist for example of H 2 0 (DI) + H 2 S0 + (NH 4 ) 2S 2 0 8 .
  • a point 27 then appears at the end of each insert.
  • the presence of this pointed end on each conductive insert makes it possible to improve the electrical contact of the anisotropic conductive polymer film and of the substrates on which it is desired to transfer the chips.
  • the resin pellets on the inserts will peel off on their own or may be dissolved in a solvent for the resin 25 (cf. FIG. 5F).
  • Gilding 28 is carried out on the tips 27 of the inserts, for example by electroless plating or by electrolysis of gold (cf. FIG. 5G).
  • the photosensitive polymer layer is removed, for example by dissolution in a solvent or “posistrip LE” (see Figure 5H) and the metal layers deposited in full layer, that is to say layers 19 and 20, are selectively etched in the areas between the inserts (see figure 51).
  • the connection pads 11 are then electrically isolated from each other. This step can be carried out dry or chemical, the latter being preferred.
  • a layer of electrically insulating material 24 is thus obtained covering the inserts with the exception of the tips 27 (cf. FIG. 5J).
  • This material is preferably a polymer such as a polyimide, a thermoplastic material, a photosensitive resin or any type of adhesive. It is also possible to spread a fusible glass commonly called "Spin On Glass".
  • an anisotropic conductive polymer film produced directly on a chip considerably simplifies the process. hybridization of the chip on a substrate. Indeed, it is no longer necessary to manipulate a film to interpose it between the chip and the substrate. Only two elements are to be handled, the chip and the substrate. In addition, thanks to the bonding layer present under the inserts, the electrical contact of the anisotropic conductive polymer film on the chip is of very good quality. Other advantages of the method according to the invention can be emphasized. Thus, the production of an anisotropic conductive polymer film according to the method of the invention does not require a critical alignment step since the redundancy of the holes made during the etching step (cf. FIG.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
EP04767896A 2003-07-18 2004-07-15 Verfahren zur herstellung eines anisotrop leitendes films Withdrawn EP1647053A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0350352A FR2857780B1 (fr) 2003-07-18 2003-07-18 Procede de fabrication de film conducteur anisotrope sur un substrat
PCT/FR2004/050335 WO2005010926A2 (fr) 2003-07-18 2004-07-15 Procede de fabrication de film conducteur anisotrope

Publications (1)

Publication Number Publication Date
EP1647053A2 true EP1647053A2 (de) 2006-04-19

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JP (1) JP2007516595A (de)
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FR2925222B1 (fr) * 2007-12-17 2010-04-16 Commissariat Energie Atomique Procede de realisation d'une interconnexion electrique entre deux couches conductrices
BRPI0911188B1 (pt) 2008-04-07 2020-05-05 Koss Corp fone de ouvido sem fio que se transiciona entre redes sem fio
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DE102009017692B4 (de) * 2009-04-09 2020-08-27 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer Niedertemperaturkontaktierung für mikroelektronische Aufbauten

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FR2857780A1 (fr) 2005-01-21
WO2005010926A2 (fr) 2005-02-03
FR2857780B1 (fr) 2005-09-09
US20060160270A1 (en) 2006-07-20
JP2007516595A (ja) 2007-06-21
WO2005010926A3 (fr) 2005-09-09
US7510962B2 (en) 2009-03-31

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