Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/561—Batch processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01015—Phosphorus [P]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01047—Silver [Ag]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01058—Cerium [Ce]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01074—Tungsten [W]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01082—Lead [Pb]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• the present invention relates to the field of integrated circuit chips.
• the present invention relates more particularly to a method for protecting integrated circuit chips in order to isolate its flanks during connection of the chip with a connection terminal block.
• connection of integrated circuit chips with a connection terminal block of a card for example, can be carried out by traditional wired wiring or by other techniques using conductive polymer compounds in contact with the output pads of the chip.
• wire cabling technology for the connection of chips does not require any specific characteristic for the component constituting the integrated circuit.
• such technology is delicate and expensive. Indeed, wires, generally copper, nickel or gold, connect the output pads of the chip to the connecting tracks of the printed circuit by soldering.
• this wired cabling technique requires high-precision equipment to make the connections, which results in a slower production rate.
• conductive polymer compounds are used more and more often establishing contact between the output pads of the chip and the connection tracks of the connection terminal block.
• connection tracks 12 are brought close to the location provided for the chip 100.
• the latter is bonded by the rear face 104 to the connection tracks 12 of the connection terminal block using an insulating adhesive 50.
• This adhesive may for example be a crosslinking adhesive under the effect of exposure to ultraviolet radiation.
• the electrical connections between the output pads 120 of the chip 100 and the connection tracks 12 are then made by dispensing a conductive resin 40 which covers the output pads 120 of the chip 100 and the connection tracks 12 of the card .
• This conductive resin 40 can for example be a poly ⁇ nérisable adhesive loaded with conductive particles such as silver particles.
• FIG. 2 A second method using a conductive polymer compound to connect the chip to the bonding tracks is illustrated in FIG. 2. This method consists in transferring the chip according to a well-known "flip chip" arrangement.
• the chip 100 is turned upside down with the output pads 120 downwards.
• the chip 100 is then connected by placing the output pads 120 on the connecting tracks 12 printed at the location provided for the chip.
• the chip 100 is connected to the connecting tracks 12 by means of an adhesive 35 with isotropic electrical conduction well known and often used for mounting passive components on the surface.
• the conductive resin 40 covers the sides 106 of the chip 100. It has however been established that in some cases, a conductivity on the side 106 of the chip 100 can cause electrical malfunctions of the integrated circuit. Indeed, depending on the types of substrate used, the flank of the chip is insulating or conductive. If the side is insulating, there is no problem that the conductive resin 40 is in contact with the wafer.
• the conductive adhesive 35 can be brought up slightly on the edges of the chip 100 and thus cause an electrical malfunction of the integrated circuit.
• the conductivity of silicon is directly linked to the wafer manufacturing process and differs according to the manufacturers and the production lines.
• a user wishing to specify a particular conductivity of the substrate will then be linked to a given supplier and even to a given product range, which automatically results in additional costs and a limitation of the products that can be used.
• the object of the present invention is to solve the problems set out above.
• the object of the present invention is to eliminate the drawbacks linked to the connection of integrated circuit chips by technologies using conductive polymers.
• the present invention provides a method of protecting the sides of integrated circuit chips in order to isolate them from the conductive polymer components used for the connection of the output pads of the chips with the connection tracks of the connection terminal blocks.
• the present invention provides a method of protecting integrated circuit chips from a silicon wafer, the wafer comprising a front face on which the integrated circuit chips are arranged and an opposite rear face, characterized in that the method includes the following steps:
• the integrated circuit chip protection method according to the present invention is also characterized in that it further comprises a step of transferring the cut wafer, rear side up, on a support so as to ensure the cohesion of the chips when applying the insulating material.
• the application of the insulating material is carried out by spraying on the rear face of the chips.
• the application of the insulating material is carried out by screen printing using a doctor blade and a screen on the rear face of the chips.
• the application of the insulating material is carried out by casting on the rear face of the chips.
• the application of the insulating material is carried out by soaking the chips in a tank containing the insulating material.
• the application of the insulating material is carried out by dispensing the insulating material on the rear face of the chips, said chips being placed on a rotary turntable.
• the insulating material has a low viscosity so as to flow along the flanks of the chips.
• the insulating material consists of an Epoxy type resin having high hardness and good adhesion to silicon.
• the insulating material consists of an insulating varnish with low dry extract so as to obtain a thin insulating layer.
• the insulating material is constituted by a colored resin so as to allow control of the areas covered by the insulating material.
• control of the areas covered by the insulating material is carried out by computer-aided vision (VAO).
• VAO computer-aided vision
• the integrated circuit chip protection method according to the present invention is also characterized in that it comprises the following steps.
• the protection of the rear face of the silicon wafer is constituted by an adhesive degradable to ultraviolet, said adhesive being degraded after the step of cutting the wafer and removed by peeling.
• the support is a degradable adhesive exposed to ultraviolet radiation after application of the insulating material.
• the chips are ejected by breaking the insulating material deposited on the support between the chips.
• the chips are ejected by cutting the support.
• the insulating material consists of a photosensitive resin polymerized through a mask at the rear faces and the flanks of the chips.
• the chips are dissociated by exposure of the wafer to ultraviolet radiation through a mask so as to facilitate the ejection of the chips.
• the present invention also relates to an integrated circuit chip characterized in that it comprises an insulating material applied to its sides so as to constitute a protection.
• the insulating material covering the flanks of the chip consists of an Epoxy type resin and / or by an insulating varnish and / or by a polymerized photosensitive resin and / or by a colored resin.
• the method according to the invention has the advantage of allowing the systematic use of direct connection techniques between the output pads of a chip and the connection tracks of a terminal block with a conductive adhesive whatever the chip used.
• the method according to the present invention can advantageously be used with any type of chip whatever the substrate used, whatever the size and shape of the chip, whether it has bosses or not.
• the method according to the present invention is easy to implement. Although it requires an additional step preceding the connection of the chips, the protection method according to the invention does not entail any significant additional cost or extended manufacturing time.
• Figure 1 dice to described, is a sectional diagram of the connection of a chip with dispensing of conductive resin.
• Figure 2 is a sectional diagram of the connection of a chip according to a technique of "flip chip” with conductive adhesive.
• Figure 3 is a schematic sectional view of the cut silicon wafer.
• FIG. 4 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a first variant and implementation.
• FIG. 5 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a second implementation variant.
• FIG. 6 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a third implementation variant.
• FIG. 7 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a fourth variant of implementation.
• the method according to the present invention comprises several steps.
• a first step consists in cutting the silicon wafer 10 on which the integrated circuit chips 100 are arranged in order to separate them.
• the rear face 104 of the wafer is placed on an adhesive 115 degradable to ultraviolet for example.
• the silicon wafer is then cut according to known conventional methods and the separated chips 100 are held together by the adhesive 115.
• the degradable adhesive 115 is then exposed to ultraviolet radiation in order to reduce its adhesion strength.
• a second step, illustrated in FIG. 3, consists in placing the circuit chips 100, active face down, on a support 110.
• This support essentially has the function of keeping the circuit chips 100 in cohesion and allowing their manipulation for the next protection step.
• the adhesive 115 of the rear face is removed by peeling for example in order to leave the rear faces 104 of the chips 100 bare.
• the support 110 is constituted by another degradable adhesive.
• the support 110 also has the function of protecting the active face of the chip 100 during the application of insulating material.
• the third step of the method according to the invention consists in applying an insulating material 150 to the rear face 104 of the chips 100 placed on the support 110.
• the insulating material 150 consists of a resin of low viscosity so as to flow along the sides 106 of the chips 100 in order to cover and protect them.
• a first method is illustrated in FIG. 4 and consists in spraying the insulating material 150 using a spray nozzle 500.
• This rain of insulating material will advantageously spread over the rear face 104 and on the flanks 106 of the chips 100 to form an insulating film.
• a second method is illustrated in FIG. 5 and consists in spreading the insulating material 150 by screen printing using a doctor blade 200 and a screen 250. Screen printing makes it possible to deposit the insulating material 150 with a geometry well defined by the screen 250.
• a third method is illustrated in FIG. 6 and consists in applying the insulating material 150 by soaking the chips 100 in a tank 300 containing the insulating material 150.
• Another method consists in applying the insulating material 150 using a spinner by placing the chips 100 on a rotating turntable and dispensing insulating material.
• the centrifugal force makes it possible to level the varnish on the chips and to fill the interstices between the chips well.
• FIG. 7 Another method is illustrated in FIG. 7 and consists in applying a photosensitive insulating material 150.
• This photosensitive insulating resin 150 is deposited on the rear of the silicon wafer according to any of the methods mentioned. previously.
• a mask 400 is then placed on the back of the wafer 10 in order to mask the spaces between the chips 100.
• the back of the wafer 10 is then exposed to UV ultraviolet radiation in order to polynterize the resin 150 over the entire surface except between the chips 100.
• This method has the advantage of facilitating the step of ejecting the chips.
• the application of the insulating material can also be carried out by a combination of the various methods mentioned above.
• the insulating material 150 used to protect the sides 106 of the chips 100 can advantageously be an Epoxy type resin having a high hardness and good adhesion to silicon.
• the resin 150 will adhere to the sides 106 of the chips 100 and will break with a clear break when the chips are ejected.
• the insulating material can also consist of a diluted resin to form a varnish with a low dry extract making it possible to obtain a homogeneous insulating layer and of low thickness.
• the insulating material is a colored resin making it possible to control the covered areas using a suitable tool such as computer aided vision (VAO) for example.
• VAO computer aided vision
• the insulating material is constituted by a poly ⁇ nérisable photosensitive resin such as that has already been described with reference to FIG. 7.
• the chips 100 are ejected from the silicon wafer 10 so as to be connected in their place and place.
• the chips 100 can be ejected by cutting the support 110 between the chips 100 and / or by mechanical ejection by lifting the chips 100 and breaking the resin between the chips 100.
• the characteristics chosen for the insulating material are such that the break or the cut between the chips will be clear and will leave the sides 106 of the chips 100 covered by the protective resin 150.
• the support 110 used for handling the chips 100 consists of a degradable adhesive.
• the wafer 10 is exposed to ultraviolet radiation for example in order to degrade the support 110 and reduce its adhesion force.
• the polymerization by exposure to ultraviolet will also have made it possible to degrade the support 110.
• the resin has not been polymerized between the chips and can be washed.
• the chips 100 can therefore easily be detached from the support 110 and taken away to be connected in their module, which simplifies the step of ejecting the chips 100.
• the integrated circuit chips 100 are therefore detached from the wafer 10 and can be connected according to any type of electronic assembly or assembly using conductive polymer materials to make their connection to various connection points or to an antenna or communication interface. contacts, since the sides 106 of the chips 100 are protected by the insulating material 150.
• the thin layer of insulating material deposited on the flanks of the chip may have a thickness of between approximately 5 and 10 ⁇ m.
• the protection obtained is a continuous thin layer and homogeneous consisting of the same layer which covers the rear face and the flanks of the chips without filling the cutting path between the chips.
• the layer substantially matches and reproduces the outer surface of the chips.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=9540751

Family Applications (1)

Country Status (6)

Families Citing this family (24)

Family Cites Families (5)

• 1999
  • 1999-01-11 FR FR9900196A patent/FR2788375B1/fr not_active Expired - Fee Related
  • 1999-12-23 US US09/889,121 patent/US6420211B1/en not_active Expired - Fee Related
  • 1999-12-23 WO PCT/FR1999/003282 patent/WO2000042653A1/fr not_active Application Discontinuation
  • 1999-12-23 CN CN99815562A patent/CN1333919A/zh active Pending
  • 1999-12-23 EP EP99963627A patent/EP1151471A1/de not_active Withdrawn
  • 1999-12-23 AU AU19868/00A patent/AU1986800A/en not_active Abandoned

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events