EP1151471A1 - Method for protecting an integrated circuit chip - Google Patents

Method for protecting an integrated circuit chip

Info

Publication number
EP1151471A1
EP1151471A1 EP99963627A EP99963627A EP1151471A1 EP 1151471 A1 EP1151471 A1 EP 1151471A1 EP 99963627 A EP99963627 A EP 99963627A EP 99963627 A EP99963627 A EP 99963627A EP 1151471 A1 EP1151471 A1 EP 1151471A1
Authority
EP
European Patent Office
Prior art keywords
chips
integrated circuit
insulating material
rear face
circuit chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99963627A
Other languages
German (de)
French (fr)
Inventor
Olivier Brunet
Didier Elbaz
Bernard Calvas
Philippe Patrice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Publication of EP1151471A1 publication Critical patent/EP1151471A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to the field of integrated circuit chips.
  • the present invention relates more particularly to a method for protecting integrated circuit chips in order to isolate its flanks during connection of the chip with a connection terminal block.
  • connection of integrated circuit chips with a connection terminal block of a card for example, can be carried out by traditional wired wiring or by other techniques using conductive polymer compounds in contact with the output pads of the chip.
  • wire cabling technology for the connection of chips does not require any specific characteristic for the component constituting the integrated circuit.
  • such technology is delicate and expensive. Indeed, wires, generally copper, nickel or gold, connect the output pads of the chip to the connecting tracks of the printed circuit by soldering.
  • this wired cabling technique requires high-precision equipment to make the connections, which results in a slower production rate.
  • conductive polymer compounds are used more and more often establishing contact between the output pads of the chip and the connection tracks of the connection terminal block.
  • connection tracks 12 are brought close to the location provided for the chip 100.
  • the latter is bonded by the rear face 104 to the connection tracks 12 of the connection terminal block using an insulating adhesive 50.
  • This adhesive may for example be a crosslinking adhesive under the effect of exposure to ultraviolet radiation.
  • the electrical connections between the output pads 120 of the chip 100 and the connection tracks 12 are then made by dispensing a conductive resin 40 which covers the output pads 120 of the chip 100 and the connection tracks 12 of the card .
  • This conductive resin 40 can for example be a poly ⁇ nérisable adhesive loaded with conductive particles such as silver particles.
  • FIG. 2 A second method using a conductive polymer compound to connect the chip to the bonding tracks is illustrated in FIG. 2. This method consists in transferring the chip according to a well-known "flip chip" arrangement.
  • the chip 100 is turned upside down with the output pads 120 downwards.
  • the chip 100 is then connected by placing the output pads 120 on the connecting tracks 12 printed at the location provided for the chip.
  • the chip 100 is connected to the connecting tracks 12 by means of an adhesive 35 with isotropic electrical conduction well known and often used for mounting passive components on the surface.
  • the conductive resin 40 covers the sides 106 of the chip 100. It has however been established that in some cases, a conductivity on the side 106 of the chip 100 can cause electrical malfunctions of the integrated circuit. Indeed, depending on the types of substrate used, the flank of the chip is insulating or conductive. If the side is insulating, there is no problem that the conductive resin 40 is in contact with the wafer.
  • the conductive adhesive 35 can be brought up slightly on the edges of the chip 100 and thus cause an electrical malfunction of the integrated circuit.
  • the conductivity of silicon is directly linked to the wafer manufacturing process and differs according to the manufacturers and the production lines.
  • a user wishing to specify a particular conductivity of the substrate will then be linked to a given supplier and even to a given product range, which automatically results in additional costs and a limitation of the products that can be used.
  • the object of the present invention is to solve the problems set out above.
  • the object of the present invention is to eliminate the drawbacks linked to the connection of integrated circuit chips by technologies using conductive polymers.
  • the present invention provides a method of protecting the sides of integrated circuit chips in order to isolate them from the conductive polymer components used for the connection of the output pads of the chips with the connection tracks of the connection terminal blocks.
  • the present invention provides a method of protecting integrated circuit chips from a silicon wafer, the wafer comprising a front face on which the integrated circuit chips are arranged and an opposite rear face, characterized in that the method includes the following steps:
  • the integrated circuit chip protection method according to the present invention is also characterized in that it further comprises a step of transferring the cut wafer, rear side up, on a support so as to ensure the cohesion of the chips when applying the insulating material.
  • the application of the insulating material is carried out by spraying on the rear face of the chips.
  • the application of the insulating material is carried out by screen printing using a doctor blade and a screen on the rear face of the chips.
  • the application of the insulating material is carried out by casting on the rear face of the chips.
  • the application of the insulating material is carried out by soaking the chips in a tank containing the insulating material.
  • the application of the insulating material is carried out by dispensing the insulating material on the rear face of the chips, said chips being placed on a rotary turntable.
  • the insulating material has a low viscosity so as to flow along the flanks of the chips.
  • the insulating material consists of an Epoxy type resin having high hardness and good adhesion to silicon.
  • the insulating material consists of an insulating varnish with low dry extract so as to obtain a thin insulating layer.
  • the insulating material is constituted by a colored resin so as to allow control of the areas covered by the insulating material.
  • control of the areas covered by the insulating material is carried out by computer-aided vision (VAO).
  • VAO computer-aided vision
  • the integrated circuit chip protection method according to the present invention is also characterized in that it comprises the following steps.
  • the protection of the rear face of the silicon wafer is constituted by an adhesive degradable to ultraviolet, said adhesive being degraded after the step of cutting the wafer and removed by peeling.
  • the support is a degradable adhesive exposed to ultraviolet radiation after application of the insulating material.
  • the chips are ejected by breaking the insulating material deposited on the support between the chips.
  • the chips are ejected by cutting the support.
  • the insulating material consists of a photosensitive resin polymerized through a mask at the rear faces and the flanks of the chips.
  • the chips are dissociated by exposure of the wafer to ultraviolet radiation through a mask so as to facilitate the ejection of the chips.
  • the present invention also relates to an integrated circuit chip characterized in that it comprises an insulating material applied to its sides so as to constitute a protection.
  • the insulating material covering the flanks of the chip consists of an Epoxy type resin and / or by an insulating varnish and / or by a polymerized photosensitive resin and / or by a colored resin.
  • the method according to the invention has the advantage of allowing the systematic use of direct connection techniques between the output pads of a chip and the connection tracks of a terminal block with a conductive adhesive whatever the chip used.
  • the method according to the present invention can advantageously be used with any type of chip whatever the substrate used, whatever the size and shape of the chip, whether it has bosses or not.
  • the method according to the present invention is easy to implement. Although it requires an additional step preceding the connection of the chips, the protection method according to the invention does not entail any significant additional cost or extended manufacturing time.
  • Figure 1 dice to described, is a sectional diagram of the connection of a chip with dispensing of conductive resin.
  • Figure 2 is a sectional diagram of the connection of a chip according to a technique of "flip chip” with conductive adhesive.
  • Figure 3 is a schematic sectional view of the cut silicon wafer.
  • FIG. 4 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a first variant and implementation.
  • FIG. 5 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a second implementation variant.
  • FIG. 6 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a third implementation variant.
  • FIG. 7 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a fourth variant of implementation.
  • the method according to the present invention comprises several steps.
  • a first step consists in cutting the silicon wafer 10 on which the integrated circuit chips 100 are arranged in order to separate them.
  • the rear face 104 of the wafer is placed on an adhesive 115 degradable to ultraviolet for example.
  • the silicon wafer is then cut according to known conventional methods and the separated chips 100 are held together by the adhesive 115.
  • the degradable adhesive 115 is then exposed to ultraviolet radiation in order to reduce its adhesion strength.
  • a second step, illustrated in FIG. 3, consists in placing the circuit chips 100, active face down, on a support 110.
  • This support essentially has the function of keeping the circuit chips 100 in cohesion and allowing their manipulation for the next protection step.
  • the adhesive 115 of the rear face is removed by peeling for example in order to leave the rear faces 104 of the chips 100 bare.
  • the support 110 is constituted by another degradable adhesive.
  • the support 110 also has the function of protecting the active face of the chip 100 during the application of insulating material.
  • the third step of the method according to the invention consists in applying an insulating material 150 to the rear face 104 of the chips 100 placed on the support 110.
  • the insulating material 150 consists of a resin of low viscosity so as to flow along the sides 106 of the chips 100 in order to cover and protect them.
  • a first method is illustrated in FIG. 4 and consists in spraying the insulating material 150 using a spray nozzle 500.
  • This rain of insulating material will advantageously spread over the rear face 104 and on the flanks 106 of the chips 100 to form an insulating film.
  • a second method is illustrated in FIG. 5 and consists in spreading the insulating material 150 by screen printing using a doctor blade 200 and a screen 250. Screen printing makes it possible to deposit the insulating material 150 with a geometry well defined by the screen 250.
  • a third method is illustrated in FIG. 6 and consists in applying the insulating material 150 by soaking the chips 100 in a tank 300 containing the insulating material 150.
  • Another method consists in applying the insulating material 150 using a spinner by placing the chips 100 on a rotating turntable and dispensing insulating material.
  • the centrifugal force makes it possible to level the varnish on the chips and to fill the interstices between the chips well.
  • FIG. 7 Another method is illustrated in FIG. 7 and consists in applying a photosensitive insulating material 150.
  • This photosensitive insulating resin 150 is deposited on the rear of the silicon wafer according to any of the methods mentioned. previously.
  • a mask 400 is then placed on the back of the wafer 10 in order to mask the spaces between the chips 100.
  • the back of the wafer 10 is then exposed to UV ultraviolet radiation in order to polynterize the resin 150 over the entire surface except between the chips 100.
  • This method has the advantage of facilitating the step of ejecting the chips.
  • the application of the insulating material can also be carried out by a combination of the various methods mentioned above.
  • the insulating material 150 used to protect the sides 106 of the chips 100 can advantageously be an Epoxy type resin having a high hardness and good adhesion to silicon.
  • the resin 150 will adhere to the sides 106 of the chips 100 and will break with a clear break when the chips are ejected.
  • the insulating material can also consist of a diluted resin to form a varnish with a low dry extract making it possible to obtain a homogeneous insulating layer and of low thickness.
  • the insulating material is a colored resin making it possible to control the covered areas using a suitable tool such as computer aided vision (VAO) for example.
  • VAO computer aided vision
  • the insulating material is constituted by a poly ⁇ nérisable photosensitive resin such as that has already been described with reference to FIG. 7.
  • the chips 100 are ejected from the silicon wafer 10 so as to be connected in their place and place.
  • the chips 100 can be ejected by cutting the support 110 between the chips 100 and / or by mechanical ejection by lifting the chips 100 and breaking the resin between the chips 100.
  • the characteristics chosen for the insulating material are such that the break or the cut between the chips will be clear and will leave the sides 106 of the chips 100 covered by the protective resin 150.
  • the support 110 used for handling the chips 100 consists of a degradable adhesive.
  • the wafer 10 is exposed to ultraviolet radiation for example in order to degrade the support 110 and reduce its adhesion force.
  • the polymerization by exposure to ultraviolet will also have made it possible to degrade the support 110.
  • the resin has not been polymerized between the chips and can be washed.
  • the chips 100 can therefore easily be detached from the support 110 and taken away to be connected in their module, which simplifies the step of ejecting the chips 100.
  • the integrated circuit chips 100 are therefore detached from the wafer 10 and can be connected according to any type of electronic assembly or assembly using conductive polymer materials to make their connection to various connection points or to an antenna or communication interface. contacts, since the sides 106 of the chips 100 are protected by the insulating material 150.
  • the thin layer of insulating material deposited on the flanks of the chip may have a thickness of between approximately 5 and 10 ⁇ m.
  • the protection obtained is a continuous thin layer and homogeneous consisting of the same layer which covers the rear face and the flanks of the chips without filling the cutting path between the chips.
  • the layer substantially matches and reproduces the outer surface of the chips.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention concerns a method for protecting integrated circuit chips (100) of a silicon wafer (10) comprising the following steps: cutting out the silicon wafer (10) so as to disengage the chips from the integrated circuit; applying a fluid insulating material (150) on the rear surface (104) of the wafer so as to coat the flanks (106) of each chip (100) of the integrated circuit with a thin insulating layer. The insulating material may be applied by spraying, screen printing, dip coating, casting or any other means. The invention further concerns integrated circuit chips whereof the flanks are protected by an insulating material to prevent electrical malfunction caused by contact of a conductive material on the flanks of the chips.

Description

PROCEDE DE PROTECTION DE PUCE DE CIRCUIT INTEGRE INTEGRATED CIRCUIT CHIP PROTECTION METHOD
La présente invention concerne le domaine des puces de circuit intégré.The present invention relates to the field of integrated circuit chips.
La présente invention concerne plus particulièrement un procédé de protection de puces de circuit intégré afin d'isoler ses flancs lors de la connexion de la puce avec un bornier de connexion.The present invention relates more particularly to a method for protecting integrated circuit chips in order to isolate its flanks during connection of the chip with a connection terminal block.
La connexion des puces de circuit intégré avec un bornier de connexion d'une carte par exemple, peut être réalisée par câblage filaire traditionnel ou par d'autres techniques utilisant des composés polymères conducteurs en contact avec les plots de sortie de la puce .The connection of integrated circuit chips with a connection terminal block of a card for example, can be carried out by traditional wired wiring or by other techniques using conductive polymer compounds in contact with the output pads of the chip.
La technologie traditionnelle de câblage filaire pour la connexion des puces ne requière aucune caractéristique spécifique pour le composant constituant le circuit intégré. Cependant, une telle technologie est délicate et coûteuse. En effet, des fils, généralement en cuivre, en nickel ou en or, relient les plots de sortie de la puce aux pistes de liaison du circuit imprimé par soudure. De plus, cette technique du câblage filaire nécessite un appareillage de haute précision pour réaliser les connexions, ce qui entraîne un ralentissement de la cadence de fabrication.Traditional wire cabling technology for the connection of chips does not require any specific characteristic for the component constituting the integrated circuit. However, such technology is delicate and expensive. Indeed, wires, generally copper, nickel or gold, connect the output pads of the chip to the connecting tracks of the printed circuit by soldering. In addition, this wired cabling technique requires high-precision equipment to make the connections, which results in a slower production rate.
Pour pallier aux inconvénients de cette technologie traditionnelle, on utilise de plus en plus souvent des composés polymères conducteurs établissant un contact entre les plots de sortie de la puce et les pistes de liaison du bornier de connexion.To overcome the drawbacks of this traditional technology, conductive polymer compounds are used more and more often establishing contact between the output pads of the chip and the connection tracks of the connection terminal block.
Une première méthode utilisant un composé polymère conducteur pour connecter la puce aux pistes de liaison est illustrée sur la figure 1. Dans un tel cas, les pistes de liaison 12 sont amenées à proximité de l'emplacement prévu pour la puce 100. Cette dernière est collée par la face arrière 104 sur les pistes de liaison 12 du bornier de connexion en utilisant une colle isolante 50. Cette colle peut être par exemple un adhésif réticulant sous l'effet d'une exposition à un rayonnement ultra-violet.A first method using a conductive polymer compound to connect the chip to the binding tracks is illustrated in FIG. 1. In such a case, the connection tracks 12 are brought close to the location provided for the chip 100. The latter is bonded by the rear face 104 to the connection tracks 12 of the connection terminal block using an insulating adhesive 50. This adhesive may for example be a crosslinking adhesive under the effect of exposure to ultraviolet radiation.
Les connexions électriques entre les plots de sortie 120 de la puce 100 et les pistes de liaison 12 sont ensuite réalisées par dispense d'une résine conductrice 40 qui recouvre les plots de sortie 120 de la puce 100 et les pistes de liaison 12 de la carte. Cette résine conductrice 40 peut être par exemple une colle polyτnérisable chargée en particules conductrices telles que des particules d'argent.The electrical connections between the output pads 120 of the chip 100 and the connection tracks 12 are then made by dispensing a conductive resin 40 which covers the output pads 120 of the chip 100 and the connection tracks 12 of the card . This conductive resin 40 can for example be a polyτnérisable adhesive loaded with conductive particles such as silver particles.
Une seconde méthode utilisant un composé polymère conducteur pour connecter la puce aux pistes de liaison est illustrée sur la figure 2. Cette méthode consiste à reporter la puce selon un montage bien connu de type "flip chip" .A second method using a conductive polymer compound to connect the chip to the bonding tracks is illustrated in FIG. 2. This method consists in transferring the chip according to a well-known "flip chip" arrangement.
Dans un montage de type "flip chip", la puce 100 est retournée face active avec les plots de sortie 120 vers le bas. La puce 100 est alors connectée en plaçant les plots de sorties 120 sur les pistes de liaison 12 imprimées à l'emplacement prévu pour la puce.In an assembly of the "flip chip" type, the chip 100 is turned upside down with the output pads 120 downwards. The chip 100 is then connected by placing the output pads 120 on the connecting tracks 12 printed at the location provided for the chip.
Dans l'exemple illustré, la puce 100 est connectée aux pistes de liaison 12 au moyen d'une colle 35 à conduction électrique isotropique bien connue et souvent utilisée pour le montage de composants passifs en surface.In the example illustrated, the chip 100 is connected to the connecting tracks 12 by means of an adhesive 35 with isotropic electrical conduction well known and often used for mounting passive components on the surface.
Ces techniques de connexion de puce par des polymères conducteurs sont très efficaces et performantes. Elles présentent de nombreux avantages par rapport à la technique traditionnelle du câblage filaire et tendent à se généraliser chez les assembleurs de circuits intégrés. En effet, ces techniques utilisant un polymère conducteur permettent de réduire le nombre d'opérations de fabrication et de diminuer nettement le coût de fabrication des matériaux des circuits intégrés .These chip connection techniques using conductive polymers are very effective and efficient. They have many advantages over the traditional cabling technique wired and tend to become widespread among assemblers of integrated circuits. In fact, these techniques using a conductive polymer make it possible to reduce the number of manufacturing operations and to significantly reduce the cost of manufacturing materials for integrated circuits.
Néanmoins, les inventeurs ont décelé un problème particulier qui est directement lié à ces techniques de connexion lorsque le substrat utilisé présente un flanc conducteur.However, the inventors have detected a particular problem which is directly linked to these connection techniques when the substrate used has a conducting flank.
On voit clairement sur la figure 1 que la résine conductrice 40 couvre les flancs 106 de la puce 100. Il a cependant été établit que dans certains cas, une conductivité sur le flanc 106 de la puce 100 peut entraîner des dysfonctionnements électriques du circuit intégré. En effet, selon les types de substrat utilisé, le flanc de la puce est isolant ou conducteur. Si le flanc est isolant, il n'y a aucun problème à ce que la résine conductrice 40 soit en contact avec la tranche.It is clearly seen in Figure 1 that the conductive resin 40 covers the sides 106 of the chip 100. It has however been established that in some cases, a conductivity on the side 106 of the chip 100 can cause electrical malfunctions of the integrated circuit. Indeed, depending on the types of substrate used, the flank of the chip is insulating or conductive. If the side is insulating, there is no problem that the conductive resin 40 is in contact with the wafer.
Néanmoins, dans le cas où le substrat utilisé pour la fabrication de la puce de circuit intégré présente un flanc conducteur, cette technique n'est pas utilisable .However, in the case where the substrate used for the manufacture of the integrated circuit chip has a conductive flank, this technique cannot be used.
De même, on voit nettement sur la figure 2 que la colle 35 conductrice peut être amenée à remonter légèrement sur les bords de la puce 100 et entraîner ainsi un dysfonctionnement électrique du circuit intégré .Likewise, it is clearly seen in FIG. 2 that the conductive adhesive 35 can be brought up slightly on the edges of the chip 100 and thus cause an electrical malfunction of the integrated circuit.
La solution utilisée jusqu'à présent consistait tout simplement à ne pas utiliser ce type de technique de connexion avec des puces présentant des flancs conducteurs. Cette solution n'est cependant pas satisfaisante car elle limite fortement les possibilités de l'assembleur en l'obligeant à utiliser certains produits avec certaines techniques de montage.The solution used up to now consisted quite simply in not using this type of connection technique with chips having conductive sides. However, this solution is not satisfactory because it greatly limits the possibilities of the assembler by forcing him to use certain products with certain assembly techniques.
En effet, la conductivité du silicium est directement liée au procédé de fabrication des plaquettes et diffère selon les fabricants et les lignes de production. Un utilisateur désirant spécifier une conductivité particulière du substrat se verra alors lié à un fournisseur donné et même à une gamme de produit donné ce qui entraîne automatiquement un surcoût et une limitation des produits utilisables.Indeed, the conductivity of silicon is directly linked to the wafer manufacturing process and differs according to the manufacturers and the production lines. A user wishing to specify a particular conductivity of the substrate will then be linked to a given supplier and even to a given product range, which automatically results in additional costs and a limitation of the products that can be used.
La présente invention a pour but de résoudre les problèmes exposés ci-dessus.The object of the present invention is to solve the problems set out above.
Le but de la présente invention est de supprimer les inconvénients liés à la connexion des puces de circuit intégré par des technologies utilisant des polymères conducteurs .The object of the present invention is to eliminate the drawbacks linked to the connection of integrated circuit chips by technologies using conductive polymers.
A cet effet, la présente invention propose un procédé de protection des flancs des puces de circuit intégré afin de les isoler des composants polymères conducteurs utilisés pour la connexion des plots de sortie des puces avec les pistes de liaison des borniers de connexion.To this end, the present invention provides a method of protecting the sides of integrated circuit chips in order to isolate them from the conductive polymer components used for the connection of the output pads of the chips with the connection tracks of the connection terminal blocks.
En particulier, la présente invention propose un procédé de protection de puces de circuit intégré d'une plaquette de silicium, la plaquette comportant une face avant sur laquelle sont disposées les puces de circuit intégré et une face arrière opposée, caractérisé en ce que le procédé comprend les étapes suivantes :In particular, the present invention provides a method of protecting integrated circuit chips from a silicon wafer, the wafer comprising a front face on which the integrated circuit chips are arranged and an opposite rear face, characterized in that the method includes the following steps:
- découpe de la plaquette de silicium de manière à désolidariser les puces de circuit intégré;- Cutting the silicon wafer so as to separate the integrated circuit chips;
- application d'une matière isolante fluide sur la face arrière de la plaquette de manière à couvrir les flancs de chaque puce de circuit intégré d'une couche isolante de faible épaisseur. Le procédé de protection de puces de circuit intégré selon la présente invention est également caractérisé en ce qu'il comprend en outre une étape de report de la plaquette découpée, face arrière vers le haut, sur un support de manière à assurer la cohésion des puces lors de l'application de la matière isolante.- Application of a fluid insulating material on the rear face of the wafer so as to cover the sides of each integrated circuit chip with a thin insulating layer. The integrated circuit chip protection method according to the present invention is also characterized in that it further comprises a step of transferring the cut wafer, rear side up, on a support so as to ensure the cohesion of the chips when applying the insulating material.
Selon une caractéristique, l'application de la matière isolante est effectuée par pulvérisation sur la face arrière des puces.According to one characteristic, the application of the insulating material is carried out by spraying on the rear face of the chips.
Selon une autre caractéristique, l'application de la matière isolante est effectuée par sérigraphie au moyen d'une racle et d'un écran sur la face arrière des puces .According to another characteristic, the application of the insulating material is carried out by screen printing using a doctor blade and a screen on the rear face of the chips.
Selon une autre caractéristique, l'application de la matière isolante est effectuée par coulage sur la face arrière des puces.According to another characteristic, the application of the insulating material is carried out by casting on the rear face of the chips.
Selon une autre caractéristique, l'application de la matière isolante est effectuée par trempage des puces dans une cuve contenant la matière isolante.According to another characteristic, the application of the insulating material is carried out by soaking the chips in a tank containing the insulating material.
Selon une autre caractéristique, l'application de la matière isolante est effectuée par dispense de la matière isolante sur la face arrière des puces, lesdites puces étant placées sur un plateau tournant en rotation.According to another characteristic, the application of the insulating material is carried out by dispensing the insulating material on the rear face of the chips, said chips being placed on a rotary turntable.
Selon une caractéristique, la matière isolante présente une faible viscosité de manière à couler le long des flancs des puces.According to one characteristic, the insulating material has a low viscosity so as to flow along the flanks of the chips.
Selon une autre caractéristique, la matière isolante est constituée par une résine de type Epoxy présentant une forte dureté et une bonne adhérence sur le silicium.According to another characteristic, the insulating material consists of an Epoxy type resin having high hardness and good adhesion to silicon.
Selon une autre caractéristique, la matière isolante est constituée par un vernis isolant à faible extrait sec de manière à obtenir une couche isolante de faible épaisseur.According to another characteristic, the insulating material consists of an insulating varnish with low dry extract so as to obtain a thin insulating layer.
Selon une autre caractéristique, la matière isolante est constituée par une résine colorée de manière à permettre un contrôle des zones recouvertes par la matière isolante.According to another characteristic, the insulating material is constituted by a colored resin so as to allow control of the areas covered by the insulating material.
Selon une autre caractéristique, le contrôle des zones recouvertes par la matière isolante est effectué par vision assistée par ordinateur (VAO) .According to another characteristic, the control of the areas covered by the insulating material is carried out by computer-aided vision (VAO).
Le procédé de protection de puces de circuit intégré selon la présente invention est également caractérisé en ce qu'il comprend les étapes suivantes.The integrated circuit chip protection method according to the present invention is also characterized in that it comprises the following steps.
- dépôt d'une protection sur la face arrière de la plaquette de silicium;- deposit of protection on the rear face of the silicon wafer;
- découpe de la plaquette de silicium de manière à désolidariser chaque puce de circuit intégré; report des puces de circuit intégré désolidarisées, face arrière vers le haut, sur un support ;- Cutting the silicon wafer so as to separate each integrated circuit chip; transfer of the dissociated integrated circuit chips, rear side up, onto a support;
- retrait de la protection de la face arrière;- removal of the rear panel protection;
- application d'une matière isolante sur la face arrière et les flancs des puces;- application of an insulating material on the rear face and the flanks of the chips;
- éjection des puces du support;- ejection of the chips from the support;
- connexion des puces .- connection of chips.
Selon une caractéristique, la protection de la face arrière de la plaquette de silicium est constituée par un adhésif degradable aux ultraviolets, ledit adhésif étant dégradé après l'étape de découpe de la plaquette et retiré par pelage.According to one characteristic, the protection of the rear face of the silicon wafer is constituted by an adhesive degradable to ultraviolet, said adhesive being degraded after the step of cutting the wafer and removed by peeling.
Selon une autre caractéristique, le support est un adhésif degradable exposé à un rayonnement ultra-violet après application de la matière isolante. Selon une autre caractéristique, l'éjection des puces est réalisée par rupture de la matière isolante déposée sur le support entre les puces.According to another characteristic, the support is a degradable adhesive exposed to ultraviolet radiation after application of the insulating material. According to another characteristic, the chips are ejected by breaking the insulating material deposited on the support between the chips.
Selon une autre caractéristique, l'éjection des puces est réalisée par découpe du support.According to another characteristic, the chips are ejected by cutting the support.
Selon une autre caractéristique, la matière isolante est constituée par une résine photosensible polymérisée à travers un masque au niveau des faces arrières et des flancs des puces.According to another characteristic, the insulating material consists of a photosensitive resin polymerized through a mask at the rear faces and the flanks of the chips.
Selon cette caractéristique, les puces sont dissociées par exposition de la plaquette à un rayonnement ultra-violet à travers un masque de manière à faciliter l'éjection des puces.According to this characteristic, the chips are dissociated by exposure of the wafer to ultraviolet radiation through a mask so as to facilitate the ejection of the chips.
La présente invention concerne également une puce de circuit intégré caractérisée en ce qu'elle comprend une matière isolante appliquée sur ses flancs de manière à constituer une protection.The present invention also relates to an integrated circuit chip characterized in that it comprises an insulating material applied to its sides so as to constitute a protection.
Selon une autre caractéristique, la matière isolante recouvrant les flancs de la puce est constituée par une résine de type Epoxy et/ou par un vernis isolant et/ou par une résine photosensible polymérisée et/ou par une résine colorée.According to another characteristic, the insulating material covering the flanks of the chip consists of an Epoxy type resin and / or by an insulating varnish and / or by a polymerized photosensitive resin and / or by a colored resin.
Le procédé selon l'invention présente l'avantage de permettre l'utilisation systématique des techniques de connexion directe entre les plots de sortie d'une puce et les pistes de liaison d'un bornier avec une colle conductrice quelque soit la puce utilisée.The method according to the invention has the advantage of allowing the systematic use of direct connection techniques between the output pads of a chip and the connection tracks of a terminal block with a conductive adhesive whatever the chip used.
Le procédé selon la présente invention peut avantageusement être utilisé avec tout type de puce quelque soit le substrat utilisé, quelque soit la taille et la forme de la puce, qu'elle présente des bossages ou non. Le procédé selon la présente invention est facile à mettre en oeuvre. Bien qu'il nécessite une étape supplémentaire précédant la connexion des puces, le procédé de protection selon l'invention n'entraîne pas de surcoût significatif ni de temps de fabrication rallongé .The method according to the present invention can advantageously be used with any type of chip whatever the substrate used, whatever the size and shape of the chip, whether it has bosses or not. The method according to the present invention is easy to implement. Although it requires an additional step preceding the connection of the chips, the protection method according to the invention does not entail any significant additional cost or extended manufacturing time.
D'autres particularités et avantages de la présente invention apparaîtront au cours de la description qui suit donnée à titre d'exemple illustr tif et non limitatif en référence aux figures dans lesquelles:Other particularities and advantages of the present invention will appear during the description which follows given by way of illustrative and nonlimiting example with reference to the figures in which:
La figure 1, dé à décrite, est un schéma en coupe de la connexion d'une puce avec dispense de résine conductrice.Figure 1, dice to described, is a sectional diagram of the connection of a chip with dispensing of conductive resin.
La figure 2, déjà décrite, est un schéma en coupe de la connexion d'une puce selon une technique de "flip chip" avec colle conductrice.Figure 2, already described, is a sectional diagram of the connection of a chip according to a technique of "flip chip" with conductive adhesive.
La figure 3 est une vue schématique en coupe de la plaque de silicium découpée.Figure 3 is a schematic sectional view of the cut silicon wafer.
La figure 4 illustre l'étape d'application d'une matière isolante sur l'arrière et les flancs des puces selon une première variante e mise en oeuvre.FIG. 4 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a first variant and implementation.
La figure 5 illustre l'étape d'application d'une matière isolante sur l'arrière et les flancs des puces selon une deuxième variante de mise en oeuvre.FIG. 5 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a second implementation variant.
La figure 6 illustre l'étape d'application d'une matière isolante sur l'arrière et les flancs des puces selon une troisième variante de mise en oeuvre.FIG. 6 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a third implementation variant.
La figure 7 illustre l'étape d'application d'une matière isolante sur l'arrière et les flancs des puces selon une quatrième variante de mise en oeuvre.FIG. 7 illustrates the step of applying an insulating material to the rear and the flanks of the chips according to a fourth variant of implementation.
Le procédé selon la présente invention comporte plusieurs étapes. Une première étape consiste à découper la plaquette de silicium 10 sur laquelle sont disposées les puces de circuit intégré 100 afin de les désolidariser.The method according to the present invention comprises several steps. A first step consists in cutting the silicon wafer 10 on which the integrated circuit chips 100 are arranged in order to separate them.
A cette fin, la face arrière 104 de la plaquette, opposée à la face avant sur laquelle sont disposées les puces, est placée sur un adhésif 115 degradable aux ultraviolets par exemple. La plaquette de silicium est alors découpée selon des méthodes classiques connues et les puces 100 désolidarisées sont maintenues ensemble par 1 'adhésif 115.To this end, the rear face 104 of the wafer, opposite the front face on which the chips are arranged, is placed on an adhesive 115 degradable to ultraviolet for example. The silicon wafer is then cut according to known conventional methods and the separated chips 100 are held together by the adhesive 115.
L'adhésif degradable 115 est alors exposé à un rayonnement ultraviolet afin de réduire sa force d' adhérence.The degradable adhesive 115 is then exposed to ultraviolet radiation in order to reduce its adhesion strength.
Une deuxième étape, illustrée sur la figure 3, consiste à placer les puces de circuit 100, face active vers le bas, sur un support 110. Ce support a essentiellement pour fonction de maintenir les puces de circuit 100 en cohésion et de permettre leur manipulation pour l'étape de protection qui suit.A second step, illustrated in FIG. 3, consists in placing the circuit chips 100, active face down, on a support 110. This support essentially has the function of keeping the circuit chips 100 in cohesion and allowing their manipulation for the next protection step.
L'adhésif 115 de la face arrière, déjà dégradé par le rayonnement ultraviolet, est retiré par pelage par exemple afin de laisser nues les faces arrières 104 des puces 100.The adhesive 115 of the rear face, already degraded by ultraviolet radiation, is removed by peeling for example in order to leave the rear faces 104 of the chips 100 bare.
Selon un mode de réalisation préférentiel, le support 110 est constitué par un autre adhésif degradable .According to a preferred embodiment, the support 110 is constituted by another degradable adhesive.
Le support 110 a en outre pour fonction de protéger la face active de la puce 100 lors de l'application de matière isolante.The support 110 also has the function of protecting the active face of the chip 100 during the application of insulating material.
La troisième étape du procédé selon l'invention consiste à appliquer une matière isolante 150 sur la face arrière 104 des puces 100 placées sur le support 110. Avantageusement, la matière isolante 150 est constituée par une résine de faible viscosité de manière à couler le long des flancs 106 des puces 100 afin de les recouvrir et de les protéger.The third step of the method according to the invention consists in applying an insulating material 150 to the rear face 104 of the chips 100 placed on the support 110. Advantageously, the insulating material 150 consists of a resin of low viscosity so as to flow along the sides 106 of the chips 100 in order to cover and protect them.
Différents moyens peuvent être utilisés pour l'application de cette matière isolante 150.Different means can be used for the application of this insulating material 150.
Une première méthode est illustrée sur la figure 4 et consiste à pulvériser la matière isolante 150 à l'aide d'une buse de pulvérisation 500. Cette pluie de matière isolante va avantageusement se répandre sur la face arrière 104 et sur les flancs 106 des puces 100 afin de former une pellicule isolante.A first method is illustrated in FIG. 4 and consists in spraying the insulating material 150 using a spray nozzle 500. This rain of insulating material will advantageously spread over the rear face 104 and on the flanks 106 of the chips 100 to form an insulating film.
Une deuxième méthode est illustrée sur la figure 5 et consiste à répandre la matière isolante 150 par sérigraphie à l'aide d'une racle 200 et d'un écran 250. La sérigraphie permet d'assurer un dépôt de la matière isolante 150 avec une géométrie bien définie par 1 ' écran 250.A second method is illustrated in FIG. 5 and consists in spreading the insulating material 150 by screen printing using a doctor blade 200 and a screen 250. Screen printing makes it possible to deposit the insulating material 150 with a geometry well defined by the screen 250.
Une troisième méthode est illustrée sur la figure 6 et consiste à appliquer la matière isolante 150 par trempage des puces 100 dans une cuve 300 contenant la matière isolante 150.A third method is illustrated in FIG. 6 and consists in applying the insulating material 150 by soaking the chips 100 in a tank 300 containing the insulating material 150.
Une autre méthode, non illustrée, consiste à appliquer la matière isolante 150 à l'aide d'une tournette en plaçant les puces 100 sur un plateau tournant en rotation et en dispensant de la matière isolante. La force centrifuge permet de niveler le vernis sur les puces et de bien remplir les interstices entre les puces .Another method, not illustrated, consists in applying the insulating material 150 using a spinner by placing the chips 100 on a rotating turntable and dispensing insulating material. The centrifugal force makes it possible to level the varnish on the chips and to fill the interstices between the chips well.
Une autre méthode est illustrée sur la figure 7 et consiste à appliquer une matière isolante 150 photosensible. Cette résine isolante photosensible 150 est déposée sur l'arrière αe la plaquette de silicium selon l'une quelconque des méthodes citées précédemment. Un masque 400 est ensuite placé sur l'arrière de la plaquette 10 afin de masquer les espaces entre les puces 100. L'arrière de la plaquette 10 est alors exposé à un rayonnement ultraviolet UV afin de polyτnériser la résine 150 sur toute la surface excepté entre les puces 100. Cette méthode présente l'avantage de faciliter l'étape d'éjection des puces.Another method is illustrated in FIG. 7 and consists in applying a photosensitive insulating material 150. This photosensitive insulating resin 150 is deposited on the rear of the silicon wafer according to any of the methods mentioned. previously. A mask 400 is then placed on the back of the wafer 10 in order to mask the spaces between the chips 100. The back of the wafer 10 is then exposed to UV ultraviolet radiation in order to polynterize the resin 150 over the entire surface except between the chips 100. This method has the advantage of facilitating the step of ejecting the chips.
L'application de la matière isolante peut également être effectuée par une combinaison des différentes méthodes citées ci-dessus.The application of the insulating material can also be carried out by a combination of the various methods mentioned above.
La matière isolante 150 utilisée pour protéger les flancs 106 des puces 100 peut avantageusement être une résine de type Epoxy ayant une forte dureté et une bonne adhérence sur le silicium. Ainsi, la résine 150 adhérera aux flancs 106 des puces 100 et se brisera avec une cassure nette lors de l'éjection des puces.The insulating material 150 used to protect the sides 106 of the chips 100 can advantageously be an Epoxy type resin having a high hardness and good adhesion to silicon. Thus, the resin 150 will adhere to the sides 106 of the chips 100 and will break with a clear break when the chips are ejected.
La matière isolante peut également être constituée par une résine diluée pour former un vernis à faible extrait sec permettant d'obtenir une couche isolante homogène et de faible épaisseur.The insulating material can also consist of a diluted resin to form a varnish with a low dry extract making it possible to obtain a homogeneous insulating layer and of low thickness.
Avantageusement, la matière isolante est une résine colorée permettant de contrôler les zones recouvertes à l'aide d'un outil adapté tel que la vision assistée par ordinateur (VAO) par exemple.Advantageously, the insulating material is a colored resin making it possible to control the covered areas using a suitable tool such as computer aided vision (VAO) for example.
Selon une autre variante, la matière isolante est constituée par une résine photosensible polyτnérisable tel que cela a déjà été décrit en référence à la figure 7.According to another variant, the insulating material is constituted by a polyτnérisable photosensitive resin such as that has already been described with reference to FIG. 7.
Après application de la matière isolante 150, les puces 100 sont éjectées de la plaquette 10 de silicium afin d'être connectées en leur lieu et place.After application of the insulating material 150, the chips 100 are ejected from the silicon wafer 10 so as to be connected in their place and place.
L'éjection des puces 100 peut être réalisée par découpe du support 110 entre les puces 100 -et/ou par éjection mécanique en soulevant les puces 100 et en brisant la résine entre les puces 100.The chips 100 can be ejected by cutting the support 110 between the chips 100 and / or by mechanical ejection by lifting the chips 100 and breaking the resin between the chips 100.
Les caractéristiques choisies pour la matière isolante sont telles que la brisure ou la découpe entre les puces sera nette et laissera les flancs 106 des puces 100 recouverts par la résine de protection 150.The characteristics chosen for the insulating material are such that the break or the cut between the chips will be clear and will leave the sides 106 of the chips 100 covered by the protective resin 150.
Selon un mode de réalisation préférentiel, le support 110 utilisé pour la manipulation des puces 100 est constitué par un adhésif degradable. Dans un tel cas, après application de la matière isolante, la plaquette 10 est exposée à un rayonnement ultra-violet par exemple afin de dégrader le support 110 et de réduire sa force d'adhérence.According to a preferred embodiment, the support 110 used for handling the chips 100 consists of a degradable adhesive. In such a case, after application of the insulating material, the wafer 10 is exposed to ultraviolet radiation for example in order to degrade the support 110 and reduce its adhesion force.
Dans le cas où une résine photosensible a été utilisée, la polymérisation par exposition aux ultraviolet aura également permis de dégrader le support 110. De plus, dans cette méthode, la résine n'a pas été polymérisée entre les puces et peut être lavée. Les puces 100 peuvent donc facilement être détachées du support 110 et emportées pour être connectées dans leur module, ce qui simplifie l'étape d'éjection des puces 100.In the case where a photosensitive resin was used, the polymerization by exposure to ultraviolet will also have made it possible to degrade the support 110. In addition, in this method, the resin has not been polymerized between the chips and can be washed. The chips 100 can therefore easily be detached from the support 110 and taken away to be connected in their module, which simplifies the step of ejecting the chips 100.
Les puces 100 de circuit intégré sont donc détachées de la plaquette 10 et peuvent être connectées selon tout type de montage ou assemblage électronique utilisant des matériaux polymères conducteurs pour réaliser leur connexion à des points de connexion divers ou à une interface de communication à antenne ou à contacts, étant donné que les flancs 106 des puces 100 sont protégés par la matière isolante 150.The integrated circuit chips 100 are therefore detached from the wafer 10 and can be connected according to any type of electronic assembly or assembly using conductive polymer materials to make their connection to various connection points or to an antenna or communication interface. contacts, since the sides 106 of the chips 100 are protected by the insulating material 150.
A titre d'exemple, la couche fine de matière isolante déposée sur les ' flancs de la puce peut avoir une épaisseur comprise entre environ 5 et 10 μm. La protection obtenue est une couche fine continue et homogène constituée d'une même couche qui couvre la face arrière et les flancs des puces sans remplir le chemin de découpe entre les puces . La couche épouse et reproduit sensiblement la surface extérieure des puces. For example, the thin layer of insulating material deposited on the flanks of the chip may have a thickness of between approximately 5 and 10 μm. The protection obtained is a continuous thin layer and homogeneous consisting of the same layer which covers the rear face and the flanks of the chips without filling the cutting path between the chips. The layer substantially matches and reproduces the outer surface of the chips.

Claims

REVENDICATIONS
1. Procédé de protection de puces de circuit intégré (100) d'une plaquette de silicium (10), la plaquette comportant une face avant sur laquelle sont disposées les puces de circuit intégré et une face arrière opposée, caractérisé en ce que le procédé comprend les étapes suivantes : découpe de la plaquette de silicium (10) de manière à désolidariser les puces de circuit intégré (100) ;1. A method for protecting integrated circuit chips (100) from a silicon wafer (10), the wafer comprising a front face on which the integrated circuit chips are arranged and an opposite rear face, characterized in that the method includes the following steps: cutting the silicon wafer (10) so as to separate the integrated circuit chips (100);
- application d'une matière isolante fluide (150) sur la face arrière (104) de la plaquette de manière à couvrir les flancs *106) de chaque puce de circuit intégré (100) d'une couche isolante de faible épaisseur.- Application of a fluid insulating material (150) on the rear face (104) of the wafer so as to cover the sides * 106) of each integrated circuit chip (100) with a thin insulating layer.
2. Procédé de protection de puces de circuit intégré (100) selon la revendication 1, caractérisé en ce qu'il comprend en outre une étape de report de la plaquette (10) découpée, face arrière (104) vers le haut, sur un support (110) de manière à assurer la cohésion des puces (100) lors de l'application de la matière isolante (150) .2. A method for protecting integrated circuit chips (100) according to claim 1, characterized in that it further comprises a step of transferring the cut-out wafer (10), rear face (104) upwards, onto a support (110) so as to ensure the cohesion of the chips (100) during the application of the insulating material (150).
3. Procédé de protection de puces de circuit intégré (100) selon la revendication 1 ou la revendication 2, caractérisé en ce que l'application de la matière isolante (150) est effectuée par pulvérisation sur la face arrière (104) des puces3. A method of protecting integrated circuit chips (100) according to claim 1 or claim 2, characterized in that the application of the insulating material (150) is carried out by spraying on the rear face (104) of the chips
(100) .(100).
4. Procédé αe protection de puces de circuit intégré (100) selon la revendication 1 ou la revendication 2, caractérisé en ce que l'application de la matière isolante (150) est effectuée par sérigraphie au moyen d'une racle (200) et d'un écran (250) sur la face arrière (104) des puces (100) .4. Ae protection method of integrated circuit chips (100) according to claim 1 or claim 2, characterized in that the application of the insulating material (150) is produced by screen printing by means of a doctor blade (200) and a screen (250) on the rear face (104) of the chips (100).
5. Procédé de protection de puces de circuit intégré (100) selon la revendication 1 ou la revendication 2, caractérisé en ce que l'application de la matière isolante (150) est effectuée par coulage sur la face arrière (104) des puces (100) .5. A method of protecting integrated circuit chips (100) according to claim 1 or claim 2, characterized in that the application of the insulating material (150) is carried out by casting on the rear face (104) of the chips ( 100).
6. Procédé de protection de puces de circuit intégré (100) selon la revendications 1 ou la revendication 2, caractérisé en ce que l'application de la matière isolante (150) est effectuée par trempage des puces (100) dans une cuve (300) contenant la matière isolante (150) .6. A method of protecting integrated circuit chips (100) according to claim 1 or claim 2, characterized in that the application of the insulating material (150) is carried out by soaking the chips (100) in a tank (300 ) containing the insulating material (150).
7. Procédé de protection de puces de circuit intégré (100) selon la revendication 1 ou la revendication 2, caractérisé en ce que l'application de la matière isolante (150) est effectuée par dispense de la matière isolante (150) sur la face arrière (104) des puces ' (100) , lesdites puces étant placées sur un plateau tournant en rotation.7. A method of protecting integrated circuit chips (100) according to claim 1 or claim 2, characterized in that the application of the insulating material (150) is carried out by dispensing the insulating material (150) on the face. rear (104) of the chips ' (100), said chips being placed on a rotating turntable.
8. Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications 1 à 7, caractérisé en ce que la matière isolante (150) présente une faible viscosité de manière à couler le long des flancs (106) des puces (100) .8. A method of protecting integrated circuit chips (100) according to any one of claims 1 to 7, characterized in that the insulating material (150) has a low viscosity so as to flow along the sides (106) of the chips (100).
9._ Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications 1 à 8, caractérisé en ce que la matière isolante (150) est constituée par une résine de type Epoxy présentant une forte dureté et une bonne adhérence sur le silicium.9._ Method for protecting integrated circuit chips (100) according to any one of claims 1 to 8, characterized in that the insulating material (150) consists of an Epoxy type resin with high hardness and good adhesion to silicon.
10. Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications 1 à 9, caractérisé en ce que la matière isolante (150) est constituée par un vernis isolant à faible extrait sec de manière à obtenir une couche isolante de faible épaisseur.10. A method of protecting integrated circuit chips (100) according to any one of claims 1 to 9, characterized in that the insulating material (150) consists of an insulating varnish with a low dry extract so as to obtain a layer insulating thin.
11. Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications 1 à 10, caractérisé en ce que la matière isolante (150) est constituée par une résine colorée de manière à permettre un contrôle des zones recouvertes par la matière isolante (150) .11. A method of protecting integrated circuit chips (100) according to any one of claims 1 to 10, characterized in that the insulating material (150) consists of a colored resin so as to allow control of the areas covered by the insulating material (150).
12. Procédé de protection de puces de circuit intégré (100) selon la revendication 11, caractérisé en ce que le contrôle des zones recouvertes par la matière isolante (150) est effectué par vision assistée par ordinateur (VAO) .12. Method for protecting integrated circuit chips (100) according to claim 11, characterized in that the control of the areas covered by the insulating material (150) is carried out by computer-aided vision (VAO).
13. Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications précédentes, caractérisé en ce qu'il comprend les étapes suivantes :13. Method for protecting integrated circuit chips (100) according to any one of the preceding claims, characterized in that it comprises the following steps:
- dépôt d'une protection (115) sur la face arrière (104) de la plaquette de silicium (10) ; découpe de la plaquette de silicium (10) de manière à désolidariser chaque puce de circuit intégré (100) ; report des puces de circuit intégré (100) désolidarisées, face arrière (104) vers le haut, sur un support (110) ;- depositing a protection (115) on the rear face (104) of the silicon wafer (10); cutting the silicon wafer (10) so as to separate each integrated circuit chip (100); transfer of the integrated circuit chips (100) separated, rear face (104) upwards, on a support (110);
- retrait de la protection (115) de la face arrière (104) ;- removal of the protection (115) from the rear face (104);
- application d'une matière isolante (150) sur la face arrière (104) et les flancs des puces (100);- Application of an insulating material (150) on the rear face (104) and the flanks of the chips (100);
- éjection des puces (100) du support (110);- Ejection of the chips (100) from the support (110);
- connexion des puces (100) .- connection of chips (100).
14. Procédé de protection de puce de circuit intégré (100) selon la revendication 13, caractérisé en ce que la protection (115) de la face arrière de la plaquette de silicium (10) est constituée par un adhésif degradable aux ultraviolets, ledit adhésif étant dégradé après l'étape de découpe de la plaquette (10) et retiré par pelage.14. Integrated circuit chip protection method (100) according to claim 13, characterized in that the protection (115) of the rear face of the silicon wafer (10) consists of an adhesive degradable to ultraviolet, said adhesive being degraded after the step of cutting the wafer (10) and removed by peeling.
15. Procédé de protection de puces de circuit intégré (100) selon la revendication 13, caractérisé en ce que le support (110) est un adhésif degradable exposé à un rayonnement ultraviolet après application de la matière isolante (150) .15. Integrated circuit chip protection method (100) according to claim 13, characterized in that the support (110) is a degradable adhesive exposed to ultraviolet radiation after application of the insulating material (150).
16. Procédé de protection de puces de circuit intégré (100) selon la revendication 13, caractérisé en ce que l'éjection des puces (100) est réalisée par rupture de la matière isolante (150) déposée sur le support (110) entre les puces (100)..16. A method of protecting integrated circuit chips (100) according to claim 13, characterized in that the ejection of the chips (100) is carried out by rupture of the insulating material (150) deposited on the support (110) between the chips (100) ..
17. Procédé de protection de puces de circuit intégré (100) selon la revendication 13, caractérisé en ce que l'éjection des puces (100) est réalisée par découpe du support (110) . 17. A method of protecting integrated circuit chips (100) according to claim 13, characterized in that the ejection of the chips (100) is carried out by cutting the support (110).
18. Procédé de protection de puces de circuit intégré (100) selon l'une quelconque des revendications 1 à 15, caractérisé en ce que la matière isolante (150) est constituée par une résine photosensible polymérisée à travers un masque (400) au niveau des faces arrières (104) et des flancs (106) des puces (100) .18. A method of protecting integrated circuit chips (100) according to any one of claims 1 to 15, characterized in that the insulating material (150) consists of a photosensitive resin polymerized through a mask (400) at the level rear faces (104) and flanks (106) of the chips (100).
19. Procédé de protection de puces de circuit intégré (100) selon la revendication 18, caractérisé en ce que les puces (100) sont dissociées par exposition de la plaquette (10) à un rayonnement ultra-violet à travers un masque (400) de manière à faciliter l'éjection des puces (100).19. A method of protecting integrated circuit chips (100) according to claim 18, characterized in that the chips (100) are dissociated by exposure of the wafer (10) to ultraviolet radiation through a mask (400) so as to facilitate the ejection of the chips (100).
20. Puce (100) de circuit intégré, caractérisé en ce qu'elle comprend une protection appliquée sur ses flancs (106) et sa face arrière (104) constituée par une couche de matière isolante continue et de faible épaisseur.20. Integrated circuit chip (100), characterized in that it includes protection applied to its sides (106) and its rear face (104) constituted by a layer of continuous insulating material and of small thickness.
21. Puce (100) de circuit intégré selon la revendication 20, caractérisée en ce que la matière isolante recouvrant ses flancs est constituée par une résine de type Epoxy et/ou par un vernis isolant et/ou par une résine photosensible polymérisée et/ou par une résine colorée.21. Integrated circuit chip (100) according to claim 20, characterized in that the insulating material covering its sides is constituted by an Epoxy type resin and / or by an insulating varnish and / or by a polymerized photosensitive resin and / or with colored resin.
22. Puce (100) de circuit intégré selon la revendication 20 ou 21, caractérisé en ce que la couche présente une épaisseur comprise entre environ 5 et 10 μm.22. Integrated circuit chip (100) according to claim 20 or 21, characterized in that the layer has a thickness of between approximately 5 and 10 μm.
23. Montage électronique comportant une puce de circuit intégré selon l'une des revendications 20 à 22, ladite puce étant connectée par un matériau polymère conducteur. 23. Electronic assembly comprising an integrated circuit chip according to one of claims 20 to 22, said chip being connected by a conductive polymer material.
EP99963627A 1999-01-11 1999-12-23 Method for protecting an integrated circuit chip Withdrawn EP1151471A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9900196 1999-01-11
FR9900196A FR2788375B1 (en) 1999-01-11 1999-01-11 INTEGRATED CIRCUIT CHIP PROTECTION METHOD
PCT/FR1999/003282 WO2000042653A1 (en) 1999-01-11 1999-12-23 Method for protecting an integrated circuit chip

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EP1151471A1 true EP1151471A1 (en) 2001-11-07

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US (1) US6420211B1 (en)
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CN (1) CN1333919A (en)
AU (1) AU1986800A (en)
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WO (1) WO2000042653A1 (en)

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CN1333919A (en) 2002-01-30
FR2788375B1 (en) 2003-07-18
FR2788375A1 (en) 2000-07-13
AU1986800A (en) 2000-08-01
US6420211B1 (en) 2002-07-16

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