WO2005010926A3 - Procede de fabrication de film conducteur anisotrope - Google Patents

Procede de fabrication de film conducteur anisotrope Download PDF

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Publication number
WO2005010926A3
WO2005010926A3 PCT/FR2004/050335 FR2004050335W WO2005010926A3 WO 2005010926 A3 WO2005010926 A3 WO 2005010926A3 FR 2004050335 W FR2004050335 W FR 2004050335W WO 2005010926 A3 WO2005010926 A3 WO 2005010926A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive inserts
anisotrope
procede
fabrication
Prior art date
Application number
PCT/FR2004/050335
Other languages
English (en)
Other versions
WO2005010926A2 (fr
Inventor
Jean Brun
Christiane Puget
Original Assignee
Commissariat Energie Atomique
Jean Brun
Christiane Puget
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Jean Brun, Christiane Puget filed Critical Commissariat Energie Atomique
Priority to JP2006519977A priority Critical patent/JP2007516595A/ja
Priority to US10/563,627 priority patent/US7510962B2/en
Priority to EP04767896A priority patent/EP1647053A2/fr
Publication of WO2005010926A2 publication Critical patent/WO2005010926A2/fr
Publication of WO2005010926A3 publication Critical patent/WO2005010926A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01024—Chromium [Cr]
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    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01073—Tantalum [Ta]
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    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Manufacturing Of Electric Cables (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un film conducteur anisotrope comprenant une couche de matériau électriquement isolant et des inserts conducteurs traversants, ledit procédé comportant les étapes suivantes : a) formation sur un substrat (T) d'au moins une couche (21) de matériau présentant des trous traversants (22), ladite couche étant appelée couche ajourée, b) remplissage des trous traversants (22) pour former des inserts conducteurs (23). Le procédé comporte en outre la réalisation d'un masque (26) recouvrant partiellement une première extrémité des inserts conducteurs (23) et la gravure de la partie non masquée de l'extrémité des inserts conducteurs (23) de façon à obtenir des inserts conducteurs (23) à extrémités en pointe. L'invention s'applique à la formation de composants (puces, circuits intégrés) à haute densité d'interconnexions.
PCT/FR2004/050335 2003-07-18 2004-07-15 Procede de fabrication de film conducteur anisotrope WO2005010926A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006519977A JP2007516595A (ja) 2003-07-18 2004-07-15 基板上に異方的導電性フィルムを形成するための方法
US10/563,627 US7510962B2 (en) 2003-07-18 2004-07-15 Method for producing an anisotropic conductive film on a substrate
EP04767896A EP1647053A2 (fr) 2003-07-18 2004-07-15 Procede de fabrication de film conducteur anisotrope

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0350352 2003-07-18
FR0350352A FR2857780B1 (fr) 2003-07-18 2003-07-18 Procede de fabrication de film conducteur anisotrope sur un substrat

Publications (2)

Publication Number Publication Date
WO2005010926A2 WO2005010926A2 (fr) 2005-02-03
WO2005010926A3 true WO2005010926A3 (fr) 2005-09-09

Family

ID=33548342

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2004/050335 WO2005010926A2 (fr) 2003-07-18 2004-07-15 Procede de fabrication de film conducteur anisotrope

Country Status (5)

Country Link
US (1) US7510962B2 (fr)
EP (1) EP1647053A2 (fr)
JP (1) JP2007516595A (fr)
FR (1) FR2857780B1 (fr)
WO (1) WO2005010926A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8518304B1 (en) 2003-03-31 2013-08-27 The Research Foundation Of State University Of New York Nano-structure enhancements for anisotropic conductive material and thermal interposers
FR2866753B1 (fr) * 2004-02-25 2006-06-09 Commissariat Energie Atomique Dispositif microelectronique d'interconnexion a tiges conductrices localisees
FR2925222B1 (fr) * 2007-12-17 2010-04-16 Commissariat Energie Atomique Procede de realisation d'une interconnexion electrique entre deux couches conductrices
EP2498509B1 (fr) 2008-04-07 2018-08-15 Koss Corporation Écouteur sans fil qui effectue des transitions entre des réseaux sans fil
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
DE102009017692B4 (de) * 2009-04-09 2020-08-27 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer Niedertemperaturkontaktierung für mikroelektronische Aufbauten

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5135606A (en) * 1989-12-08 1992-08-04 Canon Kabushiki Kaisha Process for preparing electrical connecting member
JPH07320543A (ja) * 1994-04-01 1995-12-08 Whitaker Corp:The 異方導電性接着構造物及びその製造方法
US6228689B1 (en) * 1998-04-18 2001-05-08 United Microelectronics Corp. Trench style bump and application of the same
US20010002044A1 (en) * 1999-08-27 2001-05-31 Ball Michael B. Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed
US6453553B1 (en) * 1997-07-22 2002-09-24 Commissariat A L'energie Atomique Method for making an anisotropic conductive coating with conductive inserts
WO2002093991A1 (fr) * 2001-05-15 2002-11-21 International Business Machines Corporation Procede destine au depot autocatalytique d'un metal sur un substrat et a la formation de motifs sur ce metal
EP1270694A1 (fr) * 2000-01-13 2003-01-02 Nitto Denko Corporation Feuille adhesive poreuse, plaquette a semi-conducteurs munie de la feuille adhesive poreuse, et procede de fabrication associe

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57207362A (en) * 1981-06-16 1982-12-20 Mitsubishi Electric Corp Semiconductor device
FR2842943B1 (fr) * 2002-07-24 2005-07-01 Commissariat Energie Atomique Procede de fabrication de film polymere conducteur anisotrope sur tranche de semi-conducteur

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5135606A (en) * 1989-12-08 1992-08-04 Canon Kabushiki Kaisha Process for preparing electrical connecting member
JPH07320543A (ja) * 1994-04-01 1995-12-08 Whitaker Corp:The 異方導電性接着構造物及びその製造方法
US6453553B1 (en) * 1997-07-22 2002-09-24 Commissariat A L'energie Atomique Method for making an anisotropic conductive coating with conductive inserts
US6228689B1 (en) * 1998-04-18 2001-05-08 United Microelectronics Corp. Trench style bump and application of the same
US20010002044A1 (en) * 1999-08-27 2001-05-31 Ball Michael B. Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed
EP1270694A1 (fr) * 2000-01-13 2003-01-02 Nitto Denko Corporation Feuille adhesive poreuse, plaquette a semi-conducteurs munie de la feuille adhesive poreuse, et procede de fabrication associe
WO2002093991A1 (fr) * 2001-05-15 2002-11-21 International Business Machines Corporation Procede destine au depot autocatalytique d'un metal sur un substrat et a la formation de motifs sur ce metal

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 07 31 March 1999 (1999-03-31) *
See also references of EP1647053A2 *
SOURIAU J-C ET AL: "Electrical conductive film for Flip-Chip interconnection based on z-axis conductors", 2002, 2002 PROCEEDINGS 52ND. ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE. ECTC 2002. SAN DIEGO, CA, MAY 28 - 31, 2002, PROCEEDINGS OF THE ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, NEW YORK, NY: IEEE, US, VOL. CONF. 52, PAGE(S) 1151-1153, ISBN: 0-7803-7430-4, XP002244362 *

Also Published As

Publication number Publication date
FR2857780A1 (fr) 2005-01-21
US20060160270A1 (en) 2006-07-20
EP1647053A2 (fr) 2006-04-19
US7510962B2 (en) 2009-03-31
JP2007516595A (ja) 2007-06-21
WO2005010926A2 (fr) 2005-02-03
FR2857780B1 (fr) 2005-09-09

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