WO2004057667A2 - Procede de reroutage de dispositifs microelectroniques sans lithographie - Google Patents
Procede de reroutage de dispositifs microelectroniques sans lithographie Download PDFInfo
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- WO2004057667A2 WO2004057667A2 PCT/FR2003/050188 FR0350188W WO2004057667A2 WO 2004057667 A2 WO2004057667 A2 WO 2004057667A2 FR 0350188 W FR0350188 W FR 0350188W WO 2004057667 A2 WO2004057667 A2 WO 2004057667A2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a method of manufacturing a package the size of an electronic chip produced on the scale of the substrate (in English "Wafer Levai Chip Scale Package” or WLCSP).
- WLCSP Wafer Levai Chip Scale Package
- the package according to the invention will be called a chip-box.
- the second problem relating to this manufacturing method is that, if the CSP boxes or chip boxes are mounted on the printed circuits without resin interposition (called “underfill” in the technique concerned), the connections will then be of low reliability: the Differences in thermal expansion between the CSP box and the printed circuit indeed induce stresses in the peripheral balls, especially if the integrated circuits are large.
- underfill in the technique concerned
- the problem is that the use of this resin is not necessarily desired depending on the applications and this generally adds at least one additional step.
- the use of this resin makes the repair of a component more delicate since it requires the replacement of a defective housing with a new one.
- the second innovative WLCSP box manufacturing process was presented by A. Kazama (see document [2] referenced at the end of this description).
- the deposition of a conductive material which has been mentioned previously is a metallization.
- a metallization we will proceed by spraying, evaporation, electrodeposition or chemical deposition of one or more metals.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03809999A EP1573805A2 (fr) | 2002-12-18 | 2003-12-17 | Procede de reroutage de dispositifs microelectroniques sans lithographie |
US10/538,889 US20060128134A1 (en) | 2002-12-18 | 2003-12-17 | Method for re-routing lithography-free microelectronic devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0216117A FR2849270A1 (fr) | 2002-12-18 | 2002-12-18 | Procede de reroutage de dispositifs microelectroniques sans lithographie |
FR02/16117 | 2002-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004057667A2 true WO2004057667A2 (fr) | 2004-07-08 |
WO2004057667A3 WO2004057667A3 (fr) | 2004-08-12 |
Family
ID=32406169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2003/050188 WO2004057667A2 (fr) | 2002-12-18 | 2003-12-17 | Procede de reroutage de dispositifs microelectroniques sans lithographie |
Country Status (4)
Country | Link |
---|---|
US (1) | US20060128134A1 (fr) |
EP (1) | EP1573805A2 (fr) |
FR (1) | FR2849270A1 (fr) |
WO (1) | WO2004057667A2 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009514602A (ja) * | 2005-11-02 | 2009-04-09 | セカンド サイト メディカル プロダクツ インコーポレイテッド | 植え込み型マイクロ電子デバイス及びその作製方法 |
US8143173B2 (en) * | 2006-11-22 | 2012-03-27 | Seiko Epson Corporation | Method for manufacturing semiconductor device |
WO2009146373A1 (fr) * | 2008-05-28 | 2009-12-03 | Mvm Technoloiges, Inc. | Procédé de production de perles de soudure sans masque |
CN103065985B (zh) * | 2011-10-21 | 2015-04-22 | 中国科学院上海微系统与信息技术研究所 | 双面布线封装的圆片级大厚度光敏bcb背面制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6396148B1 (en) * | 2000-02-10 | 2002-05-28 | Epic Technologies, Inc. | Electroless metal connection structures and methods |
US20020063332A1 (en) * | 2000-09-19 | 2002-05-30 | Yoshihide Yamaguchi | Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure |
US20020076911A1 (en) * | 2000-12-15 | 2002-06-20 | Lin Charles W.C. | Semiconductor chip assembly with bumped molded substrate |
US20020185721A1 (en) * | 1999-09-30 | 2002-12-12 | Chan Seung Hwang | Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same |
-
2002
- 2002-12-18 FR FR0216117A patent/FR2849270A1/fr active Pending
-
2003
- 2003-12-17 EP EP03809999A patent/EP1573805A2/fr not_active Withdrawn
- 2003-12-17 WO PCT/FR2003/050188 patent/WO2004057667A2/fr not_active Application Discontinuation
- 2003-12-17 US US10/538,889 patent/US20060128134A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020185721A1 (en) * | 1999-09-30 | 2002-12-12 | Chan Seung Hwang | Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same |
US6396148B1 (en) * | 2000-02-10 | 2002-05-28 | Epic Technologies, Inc. | Electroless metal connection structures and methods |
US20020063332A1 (en) * | 2000-09-19 | 2002-05-30 | Yoshihide Yamaguchi | Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure |
US20020076911A1 (en) * | 2000-12-15 | 2002-06-20 | Lin Charles W.C. | Semiconductor chip assembly with bumped molded substrate |
Also Published As
Publication number | Publication date |
---|---|
US20060128134A1 (en) | 2006-06-15 |
FR2849270A1 (fr) | 2004-06-25 |
EP1573805A2 (fr) | 2005-09-14 |
WO2004057667A3 (fr) | 2004-08-12 |
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