EP1719173A1 - Dispositif microelectronique d'interconnexion a tiges conductrices localisees - Google Patents
Dispositif microelectronique d'interconnexion a tiges conductrices localiseesInfo
- Publication number
- EP1719173A1 EP1719173A1 EP05717721A EP05717721A EP1719173A1 EP 1719173 A1 EP1719173 A1 EP 1719173A1 EP 05717721 A EP05717721 A EP 05717721A EP 05717721 A EP05717721 A EP 05717721A EP 1719173 A1 EP1719173 A1 EP 1719173A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductive
- holes
- layer
- masking layer
- rods
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Definitions
- the present invention relates to the assembly of electronic components (chips, integrated circuits, electromechanical components, optoelectronic components).
- electronic components chips, integrated circuits, electromechanical components, optoelectronic components.
- the present invention is similar to the ACF technique and relates to a microelectronic device comprising an electronic component provided with conductive rods located on certain zones of the latter and capable of ensuring an electrical connection with another electronic component with which said component is brought to be assembled. .
- the present invention also relates to a method for producing said microelectronic device.
- FIG. 1 illustrates the assembly between a chip 10 and an interconnection substrate 20.
- the substrate noted 20 is provided with connection pads 21 based on metal and covered with glue 30 in order to be assembled with the chip 10.
- connection pads 21 based on metal and covered with glue 30 in order to be assembled with the chip 10.
- the electrical connection between the chip 10 and the substrate 20 will be made by means of an anisotropic conductive film 15 according to the prior art, formed directly on the chip 10, and resting on the passivation layer 11.
- This anisotropic conductive film 15 is formed of a plurality of conductive rods 16 passing through an insulating layer 17.
- the conductive rods 16 will allow after assembly, to electrically connect each conductive pad of the chip 10 to one or more connection pads of the substrate 20.
- the anisotropic conductive film 15 is suitable for connections of pads in high density tee and allows avoid welding between the substrate connection pads and the conductive pads of the chip. With this type of film, it is not necessary to locate the studs of the chip and those of the substrate that one wishes to interconnect. Due in particular to the rigidity of the conductive rods, an anisotropic conductive film can however prove to be difficult to adapt to the assembly of components having significant variations in contact height. Thus, using an anisotropic conductive film to interconnect electronic components having significant flatness defects, can cause difficulties during the assembly of said components.
- An anisotropic conductive film may also prove to be unsuitable for interconnecting electronic components comprising one or more sensitive or fragile zones, which it is desired to protect from possible shocks or even from any contact.
- An anisotropic conductive film as described above has conductive rods incorporated regularly throughout the extent of an insulating layer. Thus, in the case where an anisotropic conductive film is formed on a component having one or more sensitive zones, conductive rods of the anisotropic conductive film can come into contact with one or more of the sensitive zones of the component and cause their deterioration.
- the present invention does not have the drawbacks of traditional anisotropic conductive films. It aims to provide a microelectronic device, which unlike ACF films according to the prior art, adapts well to the interconnection of electronic components having a rugged topography. The present invention also makes it possible to be able to interconnect an electronic component with another electronic component while preserving any sensitive zones located on said component and / and on said other electronic component.
- the present invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive background on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode , in order to form the conductive rods, - removal of the masking layer.
- the invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, comprising the steps of: - depositing a conductive background on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer, the method further comprising: at least one step of isolating the conductive bottom, outside of zones located opposite the conductive pads.
- the present invention relates, in particular to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the rods conductive being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive bottom on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer a plurality of holes, each hole being at least partially located opposite a conductive pad, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer.
- the masking layer may be formed from at least one layer of photosensitive resin or polymer.
- the step of forming holes in the masking layer can be carried out by means of at least one photolithography process during which the masking layer is exposed to radiation, for example ultraviolet, through a mask comprising one or more patterns opaque to said radiation.
- the mask patterns can then be placed depending on the location of the conductive pads on the component.
- the conductive bottom may be formed of a conductive layer or of a stack of at least two different conductive layers, one of the two layers, for example a Ti-based layer which can serve, for example, as an adhesion adaptation layer.
- an at least partial step of removing the conductive bottom can be provided.
- the method can further comprise, after the step of filling holes, an additional step of chemical deposition based on noble metal on the conductive rods.
- This step can make it possible to form conductive rods having improved conductance.
- the present invention also relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component comprising the steps of: - depositing a conductive bottom on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, at least one conductive pad among said conductive pads being located opposite a or several holes, at least one hole among said holes having none of said conductive studs facing each other, - etching of the conductive bottom through the holes, - filling holes with a conductive material, by electrolysis and using the conductive bottom as an electrode, to form the conductive rods, - removal of the masking layer.
- the step of forming holes in the masking layer can be carried out by a photolithography process during which the masking layer, for example based on photosensitive resin is exposed to radiation, for example ultraviolet through a mask comprising one or more several patterns, some of which are opaque to said radiation.
- the patterns of the mask can possibly be placed relative to said component, without taking account of the location of the conductive pads on said component.
- an alignment of the mask patterns with the conductive pads of the component, carried out directly or indirectly by means of marks or drawings on the electronic component is not compulsory.
- the mask used in the step of forming holes in the masking layer can then be optionally chosen independently of said electronic component and can be used for several electronic components of different topographies or of different types or the distribution of the conductive pads of which is different.
- Said conductive base may be formed of a conductive layer for example based on copper or of a stack of at least two different conductive layers.
- the etching step of the conductive bottom may optionally be extended so that the holes have a first part at the level of the masking layer and a second part at the level of the conductive bottom, said second part then being wider than said first part.
- an over-etching of the conductive bottom through the holes can make it difficult or even prevent the growth of conductive rods in certain holes which are not located opposite conductive pads.
- the method may optionally further comprise, after the step of removing the masking layer, a step of removing said etched conductive bottom.
- the present invention also relates to a method for manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing 'a conductive bottom on said component, - deposition of a thin insulating layer, for example based on photosensitive resin or of polymer on the conductive bottom, - formation of a plurality of openings in said thin insulating layer, each opening being located next to a conductive pad.
- This variant of the process may also include, after the step of removing the masking layer, a step of selective etching or of selective removal of the conductive bottom.
- the electronic component from which the process according to the invention is carried out may for example be a chip or an integrated circuit or a MEMS (electromechanical system) and may optionally be covered with a passivation layer or with a dielectric layer in which said conductive pads are incorporated on which the conductive rods are formed.
- the invention further relates to a microelectronic device capable of being obtained from the method according to the invention.
- the invention also relates to a microelectronic device comprising: - an electronic component covered with one or more conductive pads and provided with one or more conductive rods or conductive projections of cylindrical shapes or conductive protrusions of cylindrical shapes each attached to said electronic component by a end in at least partial contact with one of said conductive pads, the other end being able to come into contact with a contact area or a connection pad of another electronic component placed opposite one of said conductive studs.
- the conductive rods can be straight. They can have a diameter of, for example, between 1 ⁇ m and 15 ⁇ m. The latter can have a length of, for example, between 4 ⁇ m and 30 ⁇ m. The number of rods per conductive pad of the component can for example be between 5 and 1000.
- the electronic component can comprise at least one conductive pad in at least partial contact with not less than 2 rods.
- FIG. 1 already described represents the interconnection of a chip and a substrate according to the known art using an anisotropic conductive film
- FIGS. 2A-2F represent different stages of a manufacturing process according to the invention
- FIGS. 3A-3C represent a variant of the manufacturing process according to the invention
- FIGS. 4A-4E show advantageous variants of the manufacturing method according to the invention
- FIG. 5 represents the assembly of a microelectronic device according to the invention with an interconnection substrate
- Identical, similar or equivalent parts of the different figures have the same reference numerals so as to facilitate the passage from one figure to another.
- the different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
- the microelectronic device implemented according to the invention is formed from a support which can be an integrated circuit, a chip, an interconnection substrate, or any type of electronic component which it is desired to interconnect with another component.
- electronic In the term electronic component, it is also desired to include electromechanical components such as for example MEMS (electromechanical microsystems) or optoelectronic components.
- FIGS. 2A to 2F A first example of a method for manufacturing a microelectronic device implemented according to the present invention is illustrated in FIGS. 2A to 2F.
- the first step of this process (FIG. 2A) consists in depositing a conductive layer or a conductive bottom 105 on a support, for example a chip or an interconnection substrate 100 provided with one or more conductive pads 102 on the surface.
- the pads conductors 102 can be formed from a conductive metal such as, for example, nickel, aluminum, tungsten, copper.
- the conductive layer 105 can be produced by depositing a layer based on metallic material such as, for example, titanium, copper, nickel, tungsten, etc. The latter is intended in particular to serve as an electric current supply layer at the time of the electrolytic growth of conductive rods formed subsequently.
- a layer of photosensitive resin 106 (for example a polyimide layer of about ten micrometers thick) is then deposited on the conductive layer 105.
- the layer of photosensitive resin 106 is exposed through a mask 150 comprising openings 151 and opaque parts 152, the openings 151 and the opaque parts 152 forming a drawing ( Figure 2B). During the insolation step, the openings 151 and the opaque parts 152 of the mask 150 are arranged as a function of the location of the conductive pads 102.
- the resin layer is then developed.
- the holes 107 are grouped into zones arranged opposite the conductive pads 102 of the substrate 100. Each hole is located at least partially opposite a conductive pad. Then, for example by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive layer 105 as an electrode, the holes 107 are filled with the perforated layer 106 so as to form conductive rods 110 from the bottom of the holes 107 located at the conductive layer 105 to the surface of the openwork layer 106 ( Figure 2D).
- metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc.
- the perforated layer 106 is then removed (FIG. 2E), for example by dissolving the photosensitive resin layer. Then, the conductive layer 105 is etched selectively with the exception of under the conductive rods 110 (FIG. 2F).
- the conductive rods 110 thus formed on the chip 100 are therefore grouped into zones and are located on the conductive pads 102, so that each conductive rod is in at least partial contact with a conductive pad.
- a thin insulating layer 103 for example based on resin or photosensitive polymer and of the order of 1 to 3 micrometers thick.
- the thin layer of photosensitive resin 103 is then exposed to radiation, for example ultraviolet radiation, through a first mask (not shown) making it possible to expose only the parts of the thin layer of resin 103 situated opposite the pads 102, in the case where the resin is developing positively, or exposing the entire layer 103 except the parts located opposite the pads 102, in the case where the resin is developing negatively.
- the thin layer of resin 103 is then developed so as to produce lights or openings 104 situated opposite the conductive pads 102 and revealing the conductive layer 105 (FIG. 3A).
- FIG. 3B For example a polyimide layer of ten micrometers thick
- the photosensitive resin layer 106 is exposed through a second mask (not shown) comprising openings and opaque parts arranged as a function of the location of the conductive pads 102.
- the resin layer 106 is then developed so as to produce a layer openwork with holes 107 grouped in areas arranged above the conductive pads. Some holes 107b are located in look of the pads and update the conductive layer 105. Some other holes 107a, the bottom of which reveals the thin layer 103 of resin are not located opposite any of the pads 102 ( Figure 3C).
- Figure 3C We then follow the steps of the example process previously described illustrated in Figures 2D to 2F.
- the holes 107b are filled by electrolysis using the conductive bottom 105 as an electrode to form conductive rods.
- the thin layer of resin 103 and the other layer of resin 106 are removed.
- the conductive layer 105 is selectively etched, so that the latter is only stored under the conductive rods 110.
- the microelectronic device according to the invention is this time formed from a chip 300, provided with conductive pads 302 based on metal such as for example copper, inserted in a passivation layer 304 based on a dielectric such as for example Si0 2 .
- a continuous conductive bottom 305 is firstly deposited on the chip 300 and covers the conductive pads 302 as well as the passivation layer 304.
- the continuous conductive bottom 305 can be formed of a conductive layer or of a stack of several conductive layers.
- Such a stack can be formed for example of a first conductive layer, for example a layer based on titanium with a thickness of the order of 300 Angstrom, covered with a second conductive layer, for example based on copper and d thickness of the order of 2500 Angstroms.
- a layer 306 based on resin or a photosensitive polymer is deposited, for example a layer of resin SJR 5740 (registered trademark) from the company Chipley, about ten micrometers thick, on the support. 300.
- a photolithography process is then carried out in order to form a plurality of holes in the layer 306.
- the layer 306 is first exposed to radiation, for example ultraviolet radiation and through a mask (not shown) comprising patterns opaque to said radiation.
- Said patterns can be identical and regularly distributed over the mask.
- the latter are preferably spaced apart by a constant pitch.
- the exposure of the layer 306 can be carried out without aligning the patterns of the mask with one or more any drawings, reference points, or alignment marks located on the chip 300. Thus, an alignment performed directly or indirectly of the patterns of the mask with the conductive pads 302 of the chip 300, for example is not necessary.
- Layer 306 is then revealed. The latter then comprises a set of transverse holes 307 revealing the conductive bottom 300 and the distribution of which in the layer 306 depends on that of the patterns of the mask. This distribution can be uniform.
- the holes 307 can for example have a diameter of the order of 3 micrometers and can be spaced apart from each other for example by a pitch of 6 micrometers (FIG. 4A).
- An etching of the conductive bottom 305 is then carried out through the holes 307, so as to extend the latter.
- certain holes denoted 307a among all of the holes 307 reveal the passivation layer 304
- certain others denoted 307b reveal the conductive pads 302.
- the conductive bottom 305 may possibly be over-etched so that the holes 307 each comprise a first part denoted 308 located at the level of the layer 306 and a second part denoted 309 with an enlarged bottom, in the extension of the first part 308 (FIG. 4B).
- the holes 307 are filled, by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive bottom 301 as an electrode.
- the holes 307b revealing the conductive pads 302 are preferably filled from their bottom to the surface of the layer 306 so as to form conductive rods 310.
- the holes 307a which reveal the passivation layer, 304 fill up generally little and slower than holes 307b.
- Conductive rods said to be “parasitic” in size generally much smaller than that of rods 310 or deposits “parasitic” can possibly form in the holes 307a (FIG. 4C).
- the method can further comprise a step of chemical deposition based on noble metal on the conductive rods 310.
- This step of anelectrolytic plating / autocatalytic deposition based on noble metal on the conductive rods 310 can improve the overall conductance of the latter.
- the layer 306 is removed by means of an etching process, for example using a solvent such as acetone. At least some of the possible “parasitic” deposits that are not very adherent with respect to the passivation layer 304, then disappear at least partially (FIG. 4D).
- the conductive bottom 305 is removed by an appropriate cleaning process.
- the cleaning process can comprise a step of removing the titanium-based layer, for example using a first bath based on ammonia and hydrogen peroxide, and another step of removing the layer copper base for example at using a second hydrofluoric acid-based bath.
- a “lift-off” type process can complete this cleaning process. Any “parasitic” stems or “parasitic” deposits then disappear completely ( Figure 4E).
- the microelectronic device thus obtained from the previously described method is formed by a chip 300 provided with conductive pads 302 inserted in a passivation layer 304.
- FIG. 5 illustrates the assembly between the chip 300 and an interconnection substrate 500.
- the chip 300 is provided with conductive rods 310 formed from the method described above and located on its conductive pads 302.
- the conductive pads of the chip 300 and connection pads 501 of the interconnection substrate 500 are arranged opposite.
- the substrate 500 is covered with adhesive 400 in order to be assembled with the chip 300. After assembly, the electrical connection between the substrate 500 and the chip 300 will be ensured by an interconnection technique implemented according to the invention.
- a method according to the invention for manufacturing conductive rods on an electronic component provided with one or more conductive pads, implements at least one step of isolating a conductive bottom, outside of zones located opposite the pads conductors. This insulation comprises for example the production of holes, in a masking layer deposited on the conductive bottom, only facing or above the studs (FIG. 2C).
- this insulation implements the production of a thin insulating layer which is etched above the studs (FIG. 3A).
- this insulation implements the etching of the conductive bottom through the holes of a masking, before the filling of these holes with a conductive material (FIG. 4B).
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Multi-Conductor Connections (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0450349A FR2866753B1 (fr) | 2004-02-25 | 2004-02-25 | Dispositif microelectronique d'interconnexion a tiges conductrices localisees |
PCT/FR2005/050123 WO2005086232A1 (fr) | 2004-02-25 | 2005-02-24 | Dispositif microelectronique d'interconnexion a tiges conductrices localisees |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1719173A1 true EP1719173A1 (fr) | 2006-11-08 |
Family
ID=34834240
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05717721A Withdrawn EP1719173A1 (fr) | 2004-02-25 | 2005-02-24 | Dispositif microelectronique d'interconnexion a tiges conductrices localisees |
Country Status (4)
Country | Link |
---|---|
US (1) | US7563703B2 (fr) |
EP (1) | EP1719173A1 (fr) |
FR (1) | FR2866753B1 (fr) |
WO (1) | WO2005086232A1 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101485105B1 (ko) * | 2008-07-15 | 2015-01-23 | 삼성전자주식회사 | 반도체 패키지 |
DE102009017692B4 (de) * | 2009-04-09 | 2020-08-27 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung einer Niedertemperaturkontaktierung für mikroelektronische Aufbauten |
US7923304B2 (en) * | 2009-09-10 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with conductive pillars and method of manufacture thereof |
US9583470B2 (en) * | 2013-12-19 | 2017-02-28 | Intel Corporation | Electronic device with solder pads including projections |
US20160093583A1 (en) * | 2014-09-25 | 2016-03-31 | Micron Technology, Inc. | Bond pad with micro-protrusions for direct metallic bonding |
CN111799241A (zh) * | 2020-06-24 | 2020-10-20 | 霸州市云谷电子科技有限公司 | 邦定结构及其制作方法和显示面板 |
FR3118285B1 (fr) | 2020-12-22 | 2023-01-13 | Commissariat Energie Atomique | Dispositif à tige d’insert de connexion électrique semi-enterrée |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5550068A (en) * | 1990-11-05 | 1996-08-27 | Nippon Telegraph And Telephone Corporation | Process of fabricating a circuit element for transmitting microwave signals |
US5610371A (en) * | 1994-03-15 | 1997-03-11 | Fujitsu Limited | Electrical connecting device and method for making same |
US5457879A (en) * | 1994-01-04 | 1995-10-17 | Motorola, Inc. | Method of shaping inter-substrate plug and receptacles interconnects |
KR100206866B1 (ko) * | 1995-10-19 | 1999-07-01 | 구본준 | 반도체 장치 |
US5977642A (en) * | 1997-08-25 | 1999-11-02 | International Business Machines Corporation | Dendrite interconnect for planarization and method for producing same |
US6300575B1 (en) * | 1997-08-25 | 2001-10-09 | International Business Machines Corporation | Conductor interconnect with dendrites through film |
US6537854B1 (en) * | 1999-05-24 | 2003-03-25 | Industrial Technology Research Institute | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed |
KR100386081B1 (ko) * | 2000-01-05 | 2003-06-09 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조 방법 |
US6605525B2 (en) * | 2001-05-01 | 2003-08-12 | Industrial Technologies Research Institute | Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed |
US6547124B2 (en) * | 2001-06-14 | 2003-04-15 | Bae Systems Information And Electronic Systems Integration Inc. | Method for forming a micro column grid array (CGA) |
FR2828334A1 (fr) * | 2001-08-03 | 2003-02-07 | Schlumberger Systems & Service | Procede pour rendre connectable electriquement et mecaniquement un dispositif electrique ayant une face munie de plots de contacts |
DE10157205A1 (de) * | 2001-11-22 | 2003-06-12 | Fraunhofer Ges Forschung | Kontakthöcker mit profilierter Oberflächenstruktur sowie Verfahren zur Herstellung |
FR2842943B1 (fr) | 2002-07-24 | 2005-07-01 | Commissariat Energie Atomique | Procede de fabrication de film polymere conducteur anisotrope sur tranche de semi-conducteur |
US6959856B2 (en) * | 2003-01-10 | 2005-11-01 | Samsung Electronics Co., Ltd. | Solder bump structure and method for forming a solder bump |
US7015590B2 (en) * | 2003-01-10 | 2006-03-21 | Samsung Electronics Co., Ltd. | Reinforced solder bump structure and method for forming a reinforced solder bump |
FR2857780B1 (fr) | 2003-07-18 | 2005-09-09 | Commissariat Energie Atomique | Procede de fabrication de film conducteur anisotrope sur un substrat |
KR100585104B1 (ko) * | 2003-10-24 | 2006-05-30 | 삼성전자주식회사 | 초박형 플립칩 패키지의 제조방법 |
-
2004
- 2004-02-25 FR FR0450349A patent/FR2866753B1/fr not_active Expired - Fee Related
-
2005
- 2005-02-24 WO PCT/FR2005/050123 patent/WO2005086232A1/fr active Application Filing
- 2005-02-24 US US10/590,412 patent/US7563703B2/en not_active Expired - Fee Related
- 2005-02-24 EP EP05717721A patent/EP1719173A1/fr not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO2005086232A1 * |
Also Published As
Publication number | Publication date |
---|---|
US7563703B2 (en) | 2009-07-21 |
FR2866753B1 (fr) | 2006-06-09 |
US20070166978A1 (en) | 2007-07-19 |
FR2866753A1 (fr) | 2005-08-26 |
WO2005086232A1 (fr) | 2005-09-15 |
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