EP1719173A1 - Microelectronic interconnect device comprising localised conductive pins - Google Patents

Microelectronic interconnect device comprising localised conductive pins

Info

Publication number
EP1719173A1
EP1719173A1 EP05717721A EP05717721A EP1719173A1 EP 1719173 A1 EP1719173 A1 EP 1719173A1 EP 05717721 A EP05717721 A EP 05717721A EP 05717721 A EP05717721 A EP 05717721A EP 1719173 A1 EP1719173 A1 EP 1719173A1
Authority
EP
European Patent Office
Prior art keywords
conductive
holes
layer
masking layer
rods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05717721A
Other languages
German (de)
French (fr)
Inventor
Jean Brun
Rémi FRANIATTE
Christiane Puget
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1719173A1 publication Critical patent/EP1719173A1/en
Withdrawn legal-status Critical Current

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Classifications

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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Definitions

  • the present invention relates to the assembly of electronic components (chips, integrated circuits, electromechanical components, optoelectronic components).
  • electronic components chips, integrated circuits, electromechanical components, optoelectronic components.
  • the present invention is similar to the ACF technique and relates to a microelectronic device comprising an electronic component provided with conductive rods located on certain zones of the latter and capable of ensuring an electrical connection with another electronic component with which said component is brought to be assembled. .
  • the present invention also relates to a method for producing said microelectronic device.
  • FIG. 1 illustrates the assembly between a chip 10 and an interconnection substrate 20.
  • the substrate noted 20 is provided with connection pads 21 based on metal and covered with glue 30 in order to be assembled with the chip 10.
  • connection pads 21 based on metal and covered with glue 30 in order to be assembled with the chip 10.
  • the electrical connection between the chip 10 and the substrate 20 will be made by means of an anisotropic conductive film 15 according to the prior art, formed directly on the chip 10, and resting on the passivation layer 11.
  • This anisotropic conductive film 15 is formed of a plurality of conductive rods 16 passing through an insulating layer 17.
  • the conductive rods 16 will allow after assembly, to electrically connect each conductive pad of the chip 10 to one or more connection pads of the substrate 20.
  • the anisotropic conductive film 15 is suitable for connections of pads in high density tee and allows avoid welding between the substrate connection pads and the conductive pads of the chip. With this type of film, it is not necessary to locate the studs of the chip and those of the substrate that one wishes to interconnect. Due in particular to the rigidity of the conductive rods, an anisotropic conductive film can however prove to be difficult to adapt to the assembly of components having significant variations in contact height. Thus, using an anisotropic conductive film to interconnect electronic components having significant flatness defects, can cause difficulties during the assembly of said components.
  • An anisotropic conductive film may also prove to be unsuitable for interconnecting electronic components comprising one or more sensitive or fragile zones, which it is desired to protect from possible shocks or even from any contact.
  • An anisotropic conductive film as described above has conductive rods incorporated regularly throughout the extent of an insulating layer. Thus, in the case where an anisotropic conductive film is formed on a component having one or more sensitive zones, conductive rods of the anisotropic conductive film can come into contact with one or more of the sensitive zones of the component and cause their deterioration.
  • the present invention does not have the drawbacks of traditional anisotropic conductive films. It aims to provide a microelectronic device, which unlike ACF films according to the prior art, adapts well to the interconnection of electronic components having a rugged topography. The present invention also makes it possible to be able to interconnect an electronic component with another electronic component while preserving any sensitive zones located on said component and / and on said other electronic component.
  • the present invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive background on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode , in order to form the conductive rods, - removal of the masking layer.
  • the invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, comprising the steps of: - depositing a conductive background on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer, the method further comprising: at least one step of isolating the conductive bottom, outside of zones located opposite the conductive pads.
  • the present invention relates, in particular to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the rods conductive being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive bottom on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer a plurality of holes, each hole being at least partially located opposite a conductive pad, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer.
  • the masking layer may be formed from at least one layer of photosensitive resin or polymer.
  • the step of forming holes in the masking layer can be carried out by means of at least one photolithography process during which the masking layer is exposed to radiation, for example ultraviolet, through a mask comprising one or more patterns opaque to said radiation.
  • the mask patterns can then be placed depending on the location of the conductive pads on the component.
  • the conductive bottom may be formed of a conductive layer or of a stack of at least two different conductive layers, one of the two layers, for example a Ti-based layer which can serve, for example, as an adhesion adaptation layer.
  • an at least partial step of removing the conductive bottom can be provided.
  • the method can further comprise, after the step of filling holes, an additional step of chemical deposition based on noble metal on the conductive rods.
  • This step can make it possible to form conductive rods having improved conductance.
  • the present invention also relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component comprising the steps of: - depositing a conductive bottom on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, at least one conductive pad among said conductive pads being located opposite a or several holes, at least one hole among said holes having none of said conductive studs facing each other, - etching of the conductive bottom through the holes, - filling holes with a conductive material, by electrolysis and using the conductive bottom as an electrode, to form the conductive rods, - removal of the masking layer.
  • the step of forming holes in the masking layer can be carried out by a photolithography process during which the masking layer, for example based on photosensitive resin is exposed to radiation, for example ultraviolet through a mask comprising one or more several patterns, some of which are opaque to said radiation.
  • the patterns of the mask can possibly be placed relative to said component, without taking account of the location of the conductive pads on said component.
  • an alignment of the mask patterns with the conductive pads of the component, carried out directly or indirectly by means of marks or drawings on the electronic component is not compulsory.
  • the mask used in the step of forming holes in the masking layer can then be optionally chosen independently of said electronic component and can be used for several electronic components of different topographies or of different types or the distribution of the conductive pads of which is different.
  • Said conductive base may be formed of a conductive layer for example based on copper or of a stack of at least two different conductive layers.
  • the etching step of the conductive bottom may optionally be extended so that the holes have a first part at the level of the masking layer and a second part at the level of the conductive bottom, said second part then being wider than said first part.
  • an over-etching of the conductive bottom through the holes can make it difficult or even prevent the growth of conductive rods in certain holes which are not located opposite conductive pads.
  • the method may optionally further comprise, after the step of removing the masking layer, a step of removing said etched conductive bottom.
  • the present invention also relates to a method for manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing 'a conductive bottom on said component, - deposition of a thin insulating layer, for example based on photosensitive resin or of polymer on the conductive bottom, - formation of a plurality of openings in said thin insulating layer, each opening being located next to a conductive pad.
  • This variant of the process may also include, after the step of removing the masking layer, a step of selective etching or of selective removal of the conductive bottom.
  • the electronic component from which the process according to the invention is carried out may for example be a chip or an integrated circuit or a MEMS (electromechanical system) and may optionally be covered with a passivation layer or with a dielectric layer in which said conductive pads are incorporated on which the conductive rods are formed.
  • the invention further relates to a microelectronic device capable of being obtained from the method according to the invention.
  • the invention also relates to a microelectronic device comprising: - an electronic component covered with one or more conductive pads and provided with one or more conductive rods or conductive projections of cylindrical shapes or conductive protrusions of cylindrical shapes each attached to said electronic component by a end in at least partial contact with one of said conductive pads, the other end being able to come into contact with a contact area or a connection pad of another electronic component placed opposite one of said conductive studs.
  • the conductive rods can be straight. They can have a diameter of, for example, between 1 ⁇ m and 15 ⁇ m. The latter can have a length of, for example, between 4 ⁇ m and 30 ⁇ m. The number of rods per conductive pad of the component can for example be between 5 and 1000.
  • the electronic component can comprise at least one conductive pad in at least partial contact with not less than 2 rods.
  • FIG. 1 already described represents the interconnection of a chip and a substrate according to the known art using an anisotropic conductive film
  • FIGS. 2A-2F represent different stages of a manufacturing process according to the invention
  • FIGS. 3A-3C represent a variant of the manufacturing process according to the invention
  • FIGS. 4A-4E show advantageous variants of the manufacturing method according to the invention
  • FIG. 5 represents the assembly of a microelectronic device according to the invention with an interconnection substrate
  • Identical, similar or equivalent parts of the different figures have the same reference numerals so as to facilitate the passage from one figure to another.
  • the different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
  • the microelectronic device implemented according to the invention is formed from a support which can be an integrated circuit, a chip, an interconnection substrate, or any type of electronic component which it is desired to interconnect with another component.
  • electronic In the term electronic component, it is also desired to include electromechanical components such as for example MEMS (electromechanical microsystems) or optoelectronic components.
  • FIGS. 2A to 2F A first example of a method for manufacturing a microelectronic device implemented according to the present invention is illustrated in FIGS. 2A to 2F.
  • the first step of this process (FIG. 2A) consists in depositing a conductive layer or a conductive bottom 105 on a support, for example a chip or an interconnection substrate 100 provided with one or more conductive pads 102 on the surface.
  • the pads conductors 102 can be formed from a conductive metal such as, for example, nickel, aluminum, tungsten, copper.
  • the conductive layer 105 can be produced by depositing a layer based on metallic material such as, for example, titanium, copper, nickel, tungsten, etc. The latter is intended in particular to serve as an electric current supply layer at the time of the electrolytic growth of conductive rods formed subsequently.
  • a layer of photosensitive resin 106 (for example a polyimide layer of about ten micrometers thick) is then deposited on the conductive layer 105.
  • the layer of photosensitive resin 106 is exposed through a mask 150 comprising openings 151 and opaque parts 152, the openings 151 and the opaque parts 152 forming a drawing ( Figure 2B). During the insolation step, the openings 151 and the opaque parts 152 of the mask 150 are arranged as a function of the location of the conductive pads 102.
  • the resin layer is then developed.
  • the holes 107 are grouped into zones arranged opposite the conductive pads 102 of the substrate 100. Each hole is located at least partially opposite a conductive pad. Then, for example by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive layer 105 as an electrode, the holes 107 are filled with the perforated layer 106 so as to form conductive rods 110 from the bottom of the holes 107 located at the conductive layer 105 to the surface of the openwork layer 106 ( Figure 2D).
  • metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc.
  • the perforated layer 106 is then removed (FIG. 2E), for example by dissolving the photosensitive resin layer. Then, the conductive layer 105 is etched selectively with the exception of under the conductive rods 110 (FIG. 2F).
  • the conductive rods 110 thus formed on the chip 100 are therefore grouped into zones and are located on the conductive pads 102, so that each conductive rod is in at least partial contact with a conductive pad.
  • a thin insulating layer 103 for example based on resin or photosensitive polymer and of the order of 1 to 3 micrometers thick.
  • the thin layer of photosensitive resin 103 is then exposed to radiation, for example ultraviolet radiation, through a first mask (not shown) making it possible to expose only the parts of the thin layer of resin 103 situated opposite the pads 102, in the case where the resin is developing positively, or exposing the entire layer 103 except the parts located opposite the pads 102, in the case where the resin is developing negatively.
  • the thin layer of resin 103 is then developed so as to produce lights or openings 104 situated opposite the conductive pads 102 and revealing the conductive layer 105 (FIG. 3A).
  • FIG. 3B For example a polyimide layer of ten micrometers thick
  • the photosensitive resin layer 106 is exposed through a second mask (not shown) comprising openings and opaque parts arranged as a function of the location of the conductive pads 102.
  • the resin layer 106 is then developed so as to produce a layer openwork with holes 107 grouped in areas arranged above the conductive pads. Some holes 107b are located in look of the pads and update the conductive layer 105. Some other holes 107a, the bottom of which reveals the thin layer 103 of resin are not located opposite any of the pads 102 ( Figure 3C).
  • Figure 3C We then follow the steps of the example process previously described illustrated in Figures 2D to 2F.
  • the holes 107b are filled by electrolysis using the conductive bottom 105 as an electrode to form conductive rods.
  • the thin layer of resin 103 and the other layer of resin 106 are removed.
  • the conductive layer 105 is selectively etched, so that the latter is only stored under the conductive rods 110.
  • the microelectronic device according to the invention is this time formed from a chip 300, provided with conductive pads 302 based on metal such as for example copper, inserted in a passivation layer 304 based on a dielectric such as for example Si0 2 .
  • a continuous conductive bottom 305 is firstly deposited on the chip 300 and covers the conductive pads 302 as well as the passivation layer 304.
  • the continuous conductive bottom 305 can be formed of a conductive layer or of a stack of several conductive layers.
  • Such a stack can be formed for example of a first conductive layer, for example a layer based on titanium with a thickness of the order of 300 Angstrom, covered with a second conductive layer, for example based on copper and d thickness of the order of 2500 Angstroms.
  • a layer 306 based on resin or a photosensitive polymer is deposited, for example a layer of resin SJR 5740 (registered trademark) from the company Chipley, about ten micrometers thick, on the support. 300.
  • a photolithography process is then carried out in order to form a plurality of holes in the layer 306.
  • the layer 306 is first exposed to radiation, for example ultraviolet radiation and through a mask (not shown) comprising patterns opaque to said radiation.
  • Said patterns can be identical and regularly distributed over the mask.
  • the latter are preferably spaced apart by a constant pitch.
  • the exposure of the layer 306 can be carried out without aligning the patterns of the mask with one or more any drawings, reference points, or alignment marks located on the chip 300. Thus, an alignment performed directly or indirectly of the patterns of the mask with the conductive pads 302 of the chip 300, for example is not necessary.
  • Layer 306 is then revealed. The latter then comprises a set of transverse holes 307 revealing the conductive bottom 300 and the distribution of which in the layer 306 depends on that of the patterns of the mask. This distribution can be uniform.
  • the holes 307 can for example have a diameter of the order of 3 micrometers and can be spaced apart from each other for example by a pitch of 6 micrometers (FIG. 4A).
  • An etching of the conductive bottom 305 is then carried out through the holes 307, so as to extend the latter.
  • certain holes denoted 307a among all of the holes 307 reveal the passivation layer 304
  • certain others denoted 307b reveal the conductive pads 302.
  • the conductive bottom 305 may possibly be over-etched so that the holes 307 each comprise a first part denoted 308 located at the level of the layer 306 and a second part denoted 309 with an enlarged bottom, in the extension of the first part 308 (FIG. 4B).
  • the holes 307 are filled, by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive bottom 301 as an electrode.
  • the holes 307b revealing the conductive pads 302 are preferably filled from their bottom to the surface of the layer 306 so as to form conductive rods 310.
  • the holes 307a which reveal the passivation layer, 304 fill up generally little and slower than holes 307b.
  • Conductive rods said to be “parasitic” in size generally much smaller than that of rods 310 or deposits “parasitic” can possibly form in the holes 307a (FIG. 4C).
  • the method can further comprise a step of chemical deposition based on noble metal on the conductive rods 310.
  • This step of anelectrolytic plating / autocatalytic deposition based on noble metal on the conductive rods 310 can improve the overall conductance of the latter.
  • the layer 306 is removed by means of an etching process, for example using a solvent such as acetone. At least some of the possible “parasitic” deposits that are not very adherent with respect to the passivation layer 304, then disappear at least partially (FIG. 4D).
  • the conductive bottom 305 is removed by an appropriate cleaning process.
  • the cleaning process can comprise a step of removing the titanium-based layer, for example using a first bath based on ammonia and hydrogen peroxide, and another step of removing the layer copper base for example at using a second hydrofluoric acid-based bath.
  • a “lift-off” type process can complete this cleaning process. Any “parasitic” stems or “parasitic” deposits then disappear completely ( Figure 4E).
  • the microelectronic device thus obtained from the previously described method is formed by a chip 300 provided with conductive pads 302 inserted in a passivation layer 304.
  • FIG. 5 illustrates the assembly between the chip 300 and an interconnection substrate 500.
  • the chip 300 is provided with conductive rods 310 formed from the method described above and located on its conductive pads 302.
  • the conductive pads of the chip 300 and connection pads 501 of the interconnection substrate 500 are arranged opposite.
  • the substrate 500 is covered with adhesive 400 in order to be assembled with the chip 300. After assembly, the electrical connection between the substrate 500 and the chip 300 will be ensured by an interconnection technique implemented according to the invention.
  • a method according to the invention for manufacturing conductive rods on an electronic component provided with one or more conductive pads, implements at least one step of isolating a conductive bottom, outside of zones located opposite the pads conductors. This insulation comprises for example the production of holes, in a masking layer deposited on the conductive bottom, only facing or above the studs (FIG. 2C).
  • this insulation implements the production of a thin insulating layer which is etched above the studs (FIG. 3A).
  • this insulation implements the etching of the conductive bottom through the holes of a masking, before the filling of these holes with a conductive material (FIG. 4B).

Abstract

The invention relates to a method of producing localised conductive pins (310) on the conductive studs of an electronic component (300).

Description

DISPOSITIF MICROELECTRONIQUE D'INTERCONNEXION A TIGES CONDUCTRICES LOCALISEES MICROELECTRONIC INTERCONNECTION DEVICE WITH LOCALIZED CONDUCTIVE RODS
DESCRIPTIONDESCRIPTION
DOMAINE TECHNIQUETECHNICAL AREA
La présente invention se rapporte à l'assemblage de composants électroniques (puces, circuits intégrés, composants électromécaniques, composants optoélectroniques) . Il existe plusieurs familles de techniques pour connecter des puces ou des circuits intégrés à des substrats d'interconnexion: le " ire-bonding" ou micro-câblage, la technique de connexion par billes dite technique "flip-chip" et la technique ACF concernant les films conducteurs anisotropes. La présente invention se rapproche de la technique ACF et concerne un dispositif microélectronique comprenant un composant électronique doté de tiges conductrices localisées sur certaines zones de ce dernier et aptes à assurer une connexion électrique avec un autre composant électronique avec lequel ledit composant est amené à être assemblé. La présente invention concerne également un procédé de réalisation dudit dispositif microélectronique.The present invention relates to the assembly of electronic components (chips, integrated circuits, electromechanical components, optoelectronic components). There are several families of techniques for connecting chips or integrated circuits to interconnection substrates: "ire-bonding" or micro-wiring, the ball connection technique known as the "flip-chip" technique and the ACF technique concerning anisotropic conductive films. The present invention is similar to the ACF technique and relates to a microelectronic device comprising an electronic component provided with conductive rods located on certain zones of the latter and capable of ensuring an electrical connection with another electronic component with which said component is brought to be assembled. . The present invention also relates to a method for producing said microelectronic device.
ÉTAT DE LA TECHNIQUE ANTÉRIEUREPRIOR STATE OF THE ART
Il est connu d'assurer la connexion électrique entre des plots conducteurs d'un composant électronique, par exemple une puce et d'autres plots conducteurs d'un autre composant électronique, par exemple un substrat d'interconnexion, en utilisant un film conducteur anisotrope ou film ACF (ACF pour « Anisotropic Conductive Film » selon la terminologie anglo-saxonne), que l'on place entre le composant électronique et l'autre composant électronique. Un film conducteur anisotrope est généralement formé de particules conductrices incorporées dans une couche isolante ou de tiges métalliques traversant un film isolant. Ce type de film permet de réaliser un contact électrique généralement dans une direction orthogonale à son plan principal, tout en assurant un isolement électrique dans des directions parallèles audit plan principal. La figure 1 illustre l'assemblage entre une puce 10 et un substrat d'interconnexion 20. Le substrat noté 20 est doté de plots de connexion 21 à base de métal et recouvert de colle 30 en vue d'être assemblé avec la puce 10. La puce 10 est quand à elle recouverte sur une face d'une couche de passivatioη 11 présentant des ouvertures qui laissent apparaître des plots conducteurs 12. La connexion électrique entre la puce 10 et le substrat 20 sera réalisée au moyen d'un film conducteur anisotrope 15 suivant l'art antérieur, formé directement sur la puce 10, et reposant sur la couche de passivation 11. Ce film conducteur anisotrope 15 est formé d'une pluralité de tiges conductrices 16 traversants une couche isolante 17. Les tiges conductrices 16 permettront après assemblage, de relier électriquement chaque plot conducteur de la puce 10 à un ou plusieurs plots de connexion du substrat 20. Le film conducteur anisotrope 15 est adapté à des connexions de plots en forte densité et permet d'éviter la réalisation de soudures entre plots de connexion du substrat et plots conducteurs de la puce. Avec ce type de film, il n'est pas nécessaire de localiser les plots de la puce et ceux du substrat que l'on souhaite interconnecter. En raison notamment de la rigidité des tiges conductrices, un film conducteur anisotrope peut s'avérer cependant difficilement adaptable à l'assemblage de composants présentant des variations importantes de hauteur de contact. Ainsi, employer un film conducteur anisotrope pour interconnecter des composants électroniques comportant des défauts de planéité importants, peut entraîner des difficultés lors de l'assemblage desdits composants. Un film conducteur anisotrope peut s'avérer également inadapté pour interconnecter des composants électroniques comportant une ou plusieurs zones sensibles ou fragiles, que l'on souhaite préserver d'éventuels chocs voire de tout contact. Un film conducteur anisotrope tel que décrit plus haut présente des tiges conductrices incorporées régulièrement dans toute l'étendue d'une couche isolante. Ainsi, dans le cas où un film conducteur anisotrope est formé sur un composant présentant une ou plusieurs zones sensibles, des tiges conductrices du film conducteur anisotrope peuvent entrer en contact avec une ou plusieurs des zones sensibles du composant et provoquer leur détérioration. Dans un autre cas où un film conducteur anisotrope est formé sur un composant et assemblé avec un autre composant présentant une ou plusieurs autres zones sensibles, des tiges conductrices du film conducteur anisotrope peuvent entrer en contact avec une ou plusieurs desdites autres zones sensibles du composant et provoquer leur détérioration. Il se pose le problème de pouvoir interconnecter des composants électroniques présentant des défauts de planéité importants ou/et des composants électroniques comportant certaines zones sensibles ou fragiles à préserver.It is known to provide the electrical connection between conductive pads of an electronic component, for example a chip and other conductive pads of another electronic component, for example an interconnection substrate, using a anisotropic conductive film or ACF film (ACF for “Anisotropic Conductive Film” according to English terminology), which is placed between the electronic component and the other electronic component. An anisotropic conductive film is generally formed of conductive particles incorporated in an insulating layer or of metal rods passing through an insulating film. This type of film makes it possible to make electrical contact generally in a direction orthogonal to its main plane, while ensuring electrical isolation in directions parallel to said main plane. FIG. 1 illustrates the assembly between a chip 10 and an interconnection substrate 20. The substrate noted 20 is provided with connection pads 21 based on metal and covered with glue 30 in order to be assembled with the chip 10. When the chip 10 is covered on one side with a passivatioη layer 11 having openings which reveal conductive pads 12. The electrical connection between the chip 10 and the substrate 20 will be made by means of an anisotropic conductive film 15 according to the prior art, formed directly on the chip 10, and resting on the passivation layer 11. This anisotropic conductive film 15 is formed of a plurality of conductive rods 16 passing through an insulating layer 17. The conductive rods 16 will allow after assembly, to electrically connect each conductive pad of the chip 10 to one or more connection pads of the substrate 20. The anisotropic conductive film 15 is suitable for connections of pads in high density tee and allows avoid welding between the substrate connection pads and the conductive pads of the chip. With this type of film, it is not necessary to locate the studs of the chip and those of the substrate that one wishes to interconnect. Due in particular to the rigidity of the conductive rods, an anisotropic conductive film can however prove to be difficult to adapt to the assembly of components having significant variations in contact height. Thus, using an anisotropic conductive film to interconnect electronic components having significant flatness defects, can cause difficulties during the assembly of said components. An anisotropic conductive film may also prove to be unsuitable for interconnecting electronic components comprising one or more sensitive or fragile zones, which it is desired to protect from possible shocks or even from any contact. An anisotropic conductive film as described above has conductive rods incorporated regularly throughout the extent of an insulating layer. Thus, in the case where an anisotropic conductive film is formed on a component having one or more sensitive zones, conductive rods of the anisotropic conductive film can come into contact with one or more of the sensitive zones of the component and cause their deterioration. In another case where an anisotropic conductive film is formed on a component and assembled with another component having one or more other sensitive zones, conductive rods of the film anisotropic conductor can come into contact with one or more of said other sensitive areas of the component and cause their deterioration. The problem arises of being able to interconnect electronic components having significant flatness defects and / or electronic components comprising certain sensitive or fragile areas to be preserved.
EXPOSÉ DE L'INVENTION La présente invention ne présente pas les inconvénients des films conducteurs anisotropes traditionnels . Elle a pour but de proposer un dispositif microélectronique, qui contrairement aux films ACF selon l'art antérieur, s'adapte bien à l'interconnexion de composants électroniques présentant une topographie accidentée. La présente invention permet également de pouvoir interconnecter un composant électronique avec un autre composant électronique tout en préservant d'éventuelles zones sensibles situées sur ledit composant ou/et sur ledit autre composant électronique. La présente invention concerne un procédé de fabrication de tiges conductrices sur un composant électronique doté d'un ou plusieurs plots conducteurs, chacune des tiges conductrices étant en contact au moins partiel avec un plot du composant électronique, comportant les étapes de : - dépôt d'un fond conducteur sur ledit composant, - dépôt d'une couche de masquage sur ledit fond conducteur, - formation dans ladite couche de masquage d'une pluralité de trous, - remplissage de trous à base d'un matériau conducteur, par electrolyse et en se servant du fond conducteur comme électrode, afin de former les tiges conductrices, - retrait de la couche de masquage . Selon une autre définition, l'invention concerne un procédé de fabrication de tiges conductrices sur un composant électronique doté d'un, ou plusieurs plots conducteurs, comportant les étapes de : - dépôt d' un fond conducteur sur ledit composant, - dépôt d'une couche de masquage sur ledit fond conducteur, - formation dans ladite couche de masquage d'une pluralité de trous, - remplissage de trous à base d'un matériau conducteur, par electrolyse et en se servant du fond conducteur comme électrode, afin de former les tiges conductrices , - retrait de la couche de masquage, le procédé comprenant en outre : au moins une étape d'isolation du fond conducteur, en dehors de zones situées en regard des plots conducteurs. La présente invention concerne, en particulier un procédé de fabrication de tiges conductrices sur un composant électronique doté d'un ou plusieurs plots conducteurs, chacune des tiges conductrices étant en contact au moins partiel avec un plot du composant électronique, comportant les étapes de: - dépôt d'un fond conducteur sur ledit composant, - dépôt d'une couche de masquage sur ledit fond conducteur, - formation dans ladite couche de masquage d'une pluralité de trous, chaque trou étant au moins partiellement situé en regard d'un plot conducteur, - remplissage de trous à base d'un matériau conducteur, par electrolyse et en se servant du fond conducteur comme électrode, afin de former les tiges conductrices, - retrait de la couche de masquage. La couche de masquage peut être formée d' au moins une couche de résine ou de polymère photosensible . L'étape de formation de trous dans la couche de masquage peut être réalisée au moyen d'au moins un procédé de photolithographie durant lequel la couche de masquage est exposée à un rayonnement, par exemple ultraviolet, à travers un masque comportant un ou plusieurs motifs opaques audit rayonnement. Durant l'étape d'exposition, les motifs du masque peuvent être alors placés en fonction de l'emplacement des plots conducteurs sur le composant. Le fond conducteur peut être formé d' une couche conductrice ou d' un empilement d' au moins deux couches conductrices différentes, une des deux couches, par exemple une couche à base de Ti pouvant servir par exemple de couche d'adaptation d'adhérence. Après l'étape de retrait de la couche de masquage, une étape de retrait au moins partiel du fond conducteur peut être prévue. Selon un mode de réalisation particulier, le procédé peut comprendre en outre, après l'étape de remplissage de trous, une étape supplémentaire de dépôt chimique à base de métal noble sur les tiges conductrices. Cette étape peut permettre de former des tiges conductrices présentant une conductance améliorée. La présente invention concerne également un procédé de fabrication de tiges conductrices sur un composant électronique doté d'un ou plusieurs plots conducteurs, chacune des tiges conductrices étant en contact au moins partiel avec un plot du composant électronique comportant les étapes de: - dépôt d'un fond conducteur sur ledit composant, - dépôt d'une couche de masquage sur ledit fond conducteur, - formation dans ladite couche de masquage d'une pluralité de trous, au moins un plot conducteur parmi lesdits plots conducteurs étant situé en regard d'un ou plusieurs trous, au moins un trou parmi lesdits trous n'ayant aucun desdits plots conducteurs en regard, - gravure du fond conducteur à travers les trous, - remplissage de trous à base d'un matériau conducteur, par electrolyse et en se servant du fond conducteur comme électrode, afin de former les tiges conductrices, - retrait de la couche de masquage . L'étape de formation de trous dans la couche de masquage peut être réalisée par un procédé de photolithographie durant lequel la couche de masquage, par exemple à base de résine photosensible est exposée à un rayonnement, par exemple ultraviolet à travers un masque comportant un ou plusieurs motifs dont certains sont opaques audit rayonnement. De manière avantageuse, durant l'étape d'exposition de la couche de masquage, les motifs du masque peuvent être éventuellement placés par rapport audit composant, sans tenir compte de l'emplacement des plots conducteurs sur ledit composant. Ainsi, un alignement des motifs du masque avec les plots conducteurs du composant, réalisé de manière directe ou indirecte par l'intermédiaire de marques ou de dessins sur le composant électronique n'est pas obligatoire. Le masque utilisé à l'étape de formation de trous dans la couche de masquage peut être alors éventuellement choisi indépendamment dudit composant électronique et peut servir pour plusieurs composants électroniques de topographies différentes ou de type différents ou dont la répartition des plots conducteurs est différente. Ledit fond conducteur peut être formé d'une couche conductrice par exemple à base de cuivre ou d'un empilement d'au moins deux couches conductrices différentes . L'étape de gravure du fond conducteur peut éventuellement être prolongée de manière à ce que les trous comportent une première partie au niveau de la couche de masquage et une seconde partie au niveau du fond conducteur, ladite seconde partie étant alors plus large que ladite première partie. Ainsi, une surgravure du fond conducteur à travers les trous peut permettre de rendre difficile voire d'empêcher la croissance de tiges conductrices dans certains trous qui ne sont pas situés en regard de plots conducteurs. Le procédé peut éventuellement comporter en outre, après l'étape de retrait de la couche de masquage, une étape de retrait dudit fond conducteur gravé . La présente invention concerne également un procédé de fabrication de tiges conductrices sur un composant électronique doté d'un ou plusieurs plots conducteurs, chacune des tiges conductrices étant en contact au moins partiel avec un plot du composant électronique, comportant les étapes de : - dépôt d'un fond conducteur sur ledit composant, - dépôt d'une fine couche isolante, par exemple à base de résine photosensible ou de polymère sur le fond conducteur, - formation d'une pluralité d'ouvertures dans ladite fine couche isolante, chaque ouverture étant située en regard d'un plot conducteur. - dépôt d'une couche de masquage, - formation dans ladite couche de masquage d'une pluralité de trous, au moins un plot conducteur parmi lesdits plots conducteurs étant situé en regard d'un ou plusieurs trous, au moins un trou parmi lesdits trous n'ayant aucun desdits plots conducteurs en regard, - remplissage par electrolyse de trous, base d'un matériau conducteur, en se servant du fond conducteur comme électrode, afin de former les tiges conductrices, - retrait de la couche de masquage. Selon cette variante de procédé, parmi la pluralité de trous formés à l'étape de formation de trous dans la couche de masquage, certains trous peuvent dévoiler la fine couche isolante, certains autres trous peuvent dévoiler le fond conducteur. Cette variante de procédé peut comporter en outre après l'étape de retrait de la couche de masquage, une étape de gravure sélective ou de retrait sélectif du fond conducteur. Le composant électronique à partir duquel est réalisé le procédé suivant l'invention peut être par exemple une puce ou un circuit intégré ou un MEMS (système électromécanique) et peut être éventuellement recouvert d'une couche de passivation ou d'une couche diélectrique dans laquelle sont incorporés lesdits plots conducteurs sur lesquels sont formées les tiges conductrices . L'invention concerne en outre un dispositif microélectronique susceptible d'être obtenu à partir du procédé suivant l'invention. L' invention concerne également un dispositif microélectronique comprenant : - un composant électronique recouvert d'un ou plusieurs plots conducteurs et doté d'une ou plusieurs tiges conductrices ou saillies conductrices de formes cylindriques ou protubérances conductrices de formes cylindriques chacune rattachée audit composant électronique par une extrémité en contact au moins partiel avec un desdits plot conducteurs, l'autre extrémité étant apte à entrer en contact avec une zone de contact ou un plot de connexion d'un autre composant électronique placé en vis-à-vis d'un des dits plots conducteur. Les tiges conductrices peuvent être rectilignes. Elles peuvent avoir un diamètre compris par exemple entre 1 μm et 15 μm. Ces dernières peuvent avoir une longueur comprise par exemple entre 4 μm et 30 μm. Le nombre de tiges par plot conducteur du composant peut être par exemple compris entre 5 et 1000. Selon un mode de réalisation avantageux de la présente invention, le composant électronique peut comporter au moins un plot conducteur en contact au moins partiel avec pas moins de 2 tiges.PRESENTATION OF THE INVENTION The present invention does not have the drawbacks of traditional anisotropic conductive films. It aims to provide a microelectronic device, which unlike ACF films according to the prior art, adapts well to the interconnection of electronic components having a rugged topography. The present invention also makes it possible to be able to interconnect an electronic component with another electronic component while preserving any sensitive zones located on said component and / and on said other electronic component. The present invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive background on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode , in order to form the conductive rods, - removal of the masking layer. According to another definition, the invention relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, comprising the steps of: - depositing a conductive background on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer, the method further comprising: at least one step of isolating the conductive bottom, outside of zones located opposite the conductive pads. The present invention relates, in particular to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the rods conductive being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing a conductive bottom on said component, - depositing a masking layer on said conductive bottom, - formation in said masking layer a plurality of holes, each hole being at least partially located opposite a conductive pad, - filling of holes based on a conductive material, by electrolysis and using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer. The masking layer may be formed from at least one layer of photosensitive resin or polymer. The step of forming holes in the masking layer can be carried out by means of at least one photolithography process during which the masking layer is exposed to radiation, for example ultraviolet, through a mask comprising one or more patterns opaque to said radiation. During the exposure step, the mask patterns can then be placed depending on the location of the conductive pads on the component. The conductive bottom may be formed of a conductive layer or of a stack of at least two different conductive layers, one of the two layers, for example a Ti-based layer which can serve, for example, as an adhesion adaptation layer. After the step of removing the masking layer, an at least partial step of removing the conductive bottom can be provided. According to a particular embodiment, the method can further comprise, after the step of filling holes, an additional step of chemical deposition based on noble metal on the conductive rods. This step can make it possible to form conductive rods having improved conductance. The present invention also relates to a method of manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component comprising the steps of: - depositing a conductive bottom on said component, - deposition of a masking layer on said conductive bottom, - formation in said masking layer of a plurality of holes, at least one conductive pad among said conductive pads being located opposite a or several holes, at least one hole among said holes having none of said conductive studs facing each other, - etching of the conductive bottom through the holes, - filling holes with a conductive material, by electrolysis and using the conductive bottom as an electrode, to form the conductive rods, - removal of the masking layer. The step of forming holes in the masking layer can be carried out by a photolithography process during which the masking layer, for example based on photosensitive resin is exposed to radiation, for example ultraviolet through a mask comprising one or more several patterns, some of which are opaque to said radiation. Advantageously, during the step of exposing the masking layer, the patterns of the mask can possibly be placed relative to said component, without taking account of the location of the conductive pads on said component. Thus, an alignment of the mask patterns with the conductive pads of the component, carried out directly or indirectly by means of marks or drawings on the electronic component is not compulsory. The mask used in the step of forming holes in the masking layer can then be optionally chosen independently of said electronic component and can be used for several electronic components of different topographies or of different types or the distribution of the conductive pads of which is different. Said conductive base may be formed of a conductive layer for example based on copper or of a stack of at least two different conductive layers. The etching step of the conductive bottom may optionally be extended so that the holes have a first part at the level of the masking layer and a second part at the level of the conductive bottom, said second part then being wider than said first part. Thus, an over-etching of the conductive bottom through the holes can make it difficult or even prevent the growth of conductive rods in certain holes which are not located opposite conductive pads. The method may optionally further comprise, after the step of removing the masking layer, a step of removing said etched conductive bottom. The present invention also relates to a method for manufacturing conductive rods on an electronic component provided with one or more conductive pads, each of the conductive rods being in at least partial contact with a pad of the electronic component, comprising the steps of: - depositing 'a conductive bottom on said component, - deposition of a thin insulating layer, for example based on photosensitive resin or of polymer on the conductive bottom, - formation of a plurality of openings in said thin insulating layer, each opening being located next to a conductive pad. - deposit of a masking layer, - Formation in said masking layer of a plurality of holes, at least one conductive pad among said conductive pads being located opposite one or more holes, at least one hole among said holes having none of said conductive pads facing , - filling by electrolysis of holes, base of a conductive material, using the conductive bottom as an electrode, in order to form the conductive rods, - removal of the masking layer. According to this variant of the method, among the plurality of holes formed in the step of forming holes in the masking layer, certain holes can reveal the fine insulating layer, certain other holes can reveal the conductive bottom. This variant of the process may also include, after the step of removing the masking layer, a step of selective etching or of selective removal of the conductive bottom. The electronic component from which the process according to the invention is carried out may for example be a chip or an integrated circuit or a MEMS (electromechanical system) and may optionally be covered with a passivation layer or with a dielectric layer in which said conductive pads are incorporated on which the conductive rods are formed. The invention further relates to a microelectronic device capable of being obtained from the method according to the invention. The invention also relates to a microelectronic device comprising: - an electronic component covered with one or more conductive pads and provided with one or more conductive rods or conductive projections of cylindrical shapes or conductive protrusions of cylindrical shapes each attached to said electronic component by a end in at least partial contact with one of said conductive pads, the other end being able to come into contact with a contact area or a connection pad of another electronic component placed opposite one of said conductive studs. The conductive rods can be straight. They can have a diameter of, for example, between 1 μm and 15 μm. The latter can have a length of, for example, between 4 μm and 30 μm. The number of rods per conductive pad of the component can for example be between 5 and 1000. According to an advantageous embodiment of the present invention, the electronic component can comprise at least one conductive pad in at least partial contact with not less than 2 rods.
BRÈVE DESCRIPTION DES DESSINSBRIEF DESCRIPTION OF THE DRAWINGS
La présente invention sera mieux comprise à la lecture de la description d'exemples de réalisation donnés, à titre purement indicatif et nullement limitatif, en faisant référence aux dessins annexés sur lesquels : La figure 1 déjà décrite représente l'interconnexion d'une puce et d'un substrat selon l'art connu à l'aide d'un film conducteur anisotrope ; Les figures 2A-2F représentent différentes étapes d'un procédé de fabrication selon l'invention ; Les figures 3A-3C représentent une variante de procédé de fabrication selon l'invention ; Les figures 4A-4E représentent des variantes avantageuses de procédé de fabrication selon 1 ' invention ; La figure 5 représente l'assemblage d'un dispositif microélectronique suivant l'invention avec un substrat d'interconnexion ; Des parties identiques, similaires ou équivalentes des différentes figures portent les mêmes références numériques de façon à faciliter le passage d'une figure à l'autre. Les différentes parties représentées sur les figures ne le sont pas nécessairement selon une échelle uniforme, pour rendre les figures plus lisibles.The present invention will be better understood on reading the description of examples of embodiments given, purely for information and in no way limiting, with reference to the appended drawings in which: FIG. 1 already described represents the interconnection of a chip and a substrate according to the known art using an anisotropic conductive film; FIGS. 2A-2F represent different stages of a manufacturing process according to the invention; FIGS. 3A-3C represent a variant of the manufacturing process according to the invention; FIGS. 4A-4E show advantageous variants of the manufacturing method according to the invention; FIG. 5 represents the assembly of a microelectronic device according to the invention with an interconnection substrate; Identical, similar or equivalent parts of the different figures have the same reference numerals so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
EXPOSÉ DÉTAILLÉ DE MODES DE RÉALISATION PARTICULIERSDETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
Le dispositif microélectronique mis en œuvre suivant l'invention est formé à partir d'un support qui peut être un circuit intégré, une puce, un substrat d'interconnexion, ou tout type de composant électronique que l'on souhaite interconnecter avec un autre composant électronique. Dans le terme composant électronique, on souhaite également inclure les composants électromécaniques tels que par exemple les MEMS (microsystèmes électromécaniques) ou les composants optoélectroniques. Un premier exemple de procédé de fabrication d'un dispositif microélectronique mis en œuvre suivant la présente invention est illustré sur les figures 2A à 2F. La première étape de ce procédé (figure 2A) consiste à déposer une couche conductrice ou un fond conducteur 105 sur un support, par exemple une puce ou un substrat d'interconnexion 100 dotée en surface d'un ou plusieurs plots conducteurs 102. Les plots conducteurs 102 peuvent être formés à base d'un métal conducteur comme par exemple le nickel, l'aluminium, le tungstène, le cuivre. La couche conductrice 105 peut être quand à elle réalisée par un dépôt d'une couche à base de matériau métallique comme par exemple le titane, le cuivre, le nickel, le tungstène, etc. Cette dernière est destinée notamment à servir de couche d'apport de courant électrique au moment de la croissance électrolytique de tiges conductrices formées ultérieurement . Une couche de résine photosensible 106 (par exemple une couche de polyimide d'une dizaine de micromètres d'épaisseur) est ensuite déposée sur la couche conductrice 105. On insole la couche de résine photosensible 106 à travers un masque 150 comprenant des ouvertures 151 et des parties opaques 152, les ouvertures 151 et les parties opaques 152 formant un dessin (figure 2B) . Lors de l'étape d'insolation, les ouvertures 151 et les parties opaques 152 du masque 150 sont disposées en fonction de l'emplacement des plots conducteurs 102. On développe ensuite la couche de résineThe microelectronic device implemented according to the invention is formed from a support which can be an integrated circuit, a chip, an interconnection substrate, or any type of electronic component which it is desired to interconnect with another component. electronic. In the term electronic component, it is also desired to include electromechanical components such as for example MEMS (electromechanical microsystems) or optoelectronic components. A first example of a method for manufacturing a microelectronic device implemented according to the present invention is illustrated in FIGS. 2A to 2F. The first step of this process (FIG. 2A) consists in depositing a conductive layer or a conductive bottom 105 on a support, for example a chip or an interconnection substrate 100 provided with one or more conductive pads 102 on the surface. The pads conductors 102 can be formed from a conductive metal such as, for example, nickel, aluminum, tungsten, copper. The conductive layer 105 can be produced by depositing a layer based on metallic material such as, for example, titanium, copper, nickel, tungsten, etc. The latter is intended in particular to serve as an electric current supply layer at the time of the electrolytic growth of conductive rods formed subsequently. A layer of photosensitive resin 106 (for example a polyimide layer of about ten micrometers thick) is then deposited on the conductive layer 105. The layer of photosensitive resin 106 is exposed through a mask 150 comprising openings 151 and opaque parts 152, the openings 151 and the opaque parts 152 forming a drawing (Figure 2B). During the insolation step, the openings 151 and the opaque parts 152 of the mask 150 are arranged as a function of the location of the conductive pads 102. The resin layer is then developed.
106 par exemple à l'aide d'une base forte de manière à réaliser des trous 107 transversaux dans cette couche de résine 106, les trous 107 mettant à jour le fond conducteur 105 (figure 2C) . Les trous 107 sont regroupés en zones disposées en regard des plots conducteurs 102 du substrat 100. Chaque trou est situé au moins partiellement en regard d'un plot conducteur. Ensuite, par exemple par croissance électrolytique de métal tel que le cuivre, le nickel, le titane, le tungstène, un alliage SnPb, l'or, etc. en se servant de la couche conductrice 105 comme électrode, on remplit les trous 107 de la couche 106 ajourée de manière à former des tiges conductrices 110 depuis le fond des trous 107 situé au niveau de la couche conductrice 105 jusqu'à la surface de la couche 106 ajourée (figure 2D) . On retire ensuite la couche 106 ajourée (figure 2E) par exemple par dissolution de la couche de résine photosensible. Puis, on grave la couche conductrice 105 de façon sélective à l'exception de sous les tiges conductrices 110 (figure 2F) . Les tiges conductrices 110 ainsi formées sur la puce 100 sont donc regroupées en zones et sont localisées sur les plots conducteurs 102, de manière à ce que chaque tige conductrice soit en contact au moins partiel avec un plot conducteur. Selon une variante de l'exemple de réalisation précédemment décrit, après l'étape de dépôt de la couche conductrice 105 illustrée sur la figure 2A, on peut effectuer le dépôt d'une fine couche 103 isolante, par exemple à base de résine ou de polymère photosensible et de l'ordre de 1 à 3 micromètre d'épaisseur. On expose alors la fine couche de résine photosensible 103 à un rayonnement par exemple ultraviolet à travers un premier masque (non représenté) permettant d' insoler uniquement les parties de la fine couche de résine 103 situées en regard des plots 102, dans le cas où la résine est à développement positif, ou d' insoler toute la couche 103 sauf les parties situées en regard des plots 102, dans le cas ou la résine est à développement négatif. On développe ensuite la fine couche de résine 103 de manière à réaliser des lumières ou des ouvertures 104 situées en regard des plots conducteurs 102 et dévoilant la couche conductrice 105 (figure 3A) . Une autre couche de résine photosensible106 for example using a strong base so as to make transverse holes 107 in this resin layer 106, the holes 107 updating the conductive bottom 105 (FIG. 2C). The holes 107 are grouped into zones arranged opposite the conductive pads 102 of the substrate 100. Each hole is located at least partially opposite a conductive pad. Then, for example by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive layer 105 as an electrode, the holes 107 are filled with the perforated layer 106 so as to form conductive rods 110 from the bottom of the holes 107 located at the conductive layer 105 to the surface of the openwork layer 106 (Figure 2D). The perforated layer 106 is then removed (FIG. 2E), for example by dissolving the photosensitive resin layer. Then, the conductive layer 105 is etched selectively with the exception of under the conductive rods 110 (FIG. 2F). The conductive rods 110 thus formed on the chip 100 are therefore grouped into zones and are located on the conductive pads 102, so that each conductive rod is in at least partial contact with a conductive pad. According to a variant of the embodiment previously described, after the step of depositing the conductive layer 105 illustrated in FIG. 2A, it is possible to deposit a thin insulating layer 103, for example based on resin or photosensitive polymer and of the order of 1 to 3 micrometers thick. The thin layer of photosensitive resin 103 is then exposed to radiation, for example ultraviolet radiation, through a first mask (not shown) making it possible to expose only the parts of the thin layer of resin 103 situated opposite the pads 102, in the case where the resin is developing positively, or exposing the entire layer 103 except the parts located opposite the pads 102, in the case where the resin is developing negatively. The thin layer of resin 103 is then developed so as to produce lights or openings 104 situated opposite the conductive pads 102 and revealing the conductive layer 105 (FIG. 3A). Another layer of photosensitive resin
106 (par exemple une couche de polyimide d'une dizaine de micromètres d'épaisseur) est ensuite déposée sur la fine couche 103 ajourée (figure 3B) . On insole la couche de résine photosensible 106 à travers un second masque (non représenté) comprenant des ouvertures et des parties opaques disposées en fonction de l'emplacement des plots conducteurs 102. On développe ensuite la couche de résine 106 de manière à réaliser une couche ajourée dotée de trous 107 regroupés en zones disposées au dessus des plots conducteurs. Certains trous 107b sont situés en regard des plots et mettent à jour la couche conductrice 105. Certains autres trous 107a, dont le fond dévoile la fine couche 103 de résine ne sont situés en regard d'aucun des plots 102 (figure 3C) . On suit alors les étapes de l'exemple de procédé précédemment décrit illustrées sur les figures 2D à 2F. Les trous 107b sont remplis par electrolyse en se servant du fond conducteur 105 comme électrode pour former des tiges conductrices. Les trous 107a, dont le fond dévoile la fine couche de résine 103 ne se remplissent pas. Puis la fine couche de résine 103 et l'autre couche de résine 106 sont retirées. Enfin, la couche conductrice 105 est gravée de manière sélective, de manière à ce que cette dernière ne soit conservée que sous les tiges conductrices 110. Un autre exemple de procédé de fabrication d'un dispositif microélectronique mis en œuvre suivant la présente invention va à présent être décrit en liaison avec les figures 4A-4E. Dans cette variante, le dispositif microélectronique suivant l'invention est cette fois formé à partir d'une puce 300, dotée de plots conducteurs 302 à base de métal tel que par exemple du cuivre, insérés dans une couche de passivation 304 à base d'un diélectrique tel que par exemple du Si02. Dans cet exemple de procédé, un fond conducteur 305 continu est tout d'abord déposé sur la puce 300 et recouvre les plots conducteurs 302 ainsi que la couche de passivation 304. Le fond conducteur 305 continu peut être formé d'une couche conductrice ou d'un empilement de plusieurs couches conductrices. Un tel empilement peut être formé par exemple d'une première couche conductrice, par exemple une couche à base de titane d'épaisseur de l'ordre de 300 Angstrom, recouverte d'une seconde couche conductrice, par exemple à base de cuivre et d'épaisseur de l'ordre de 2500 Angstrom. On réalise ensuite le dépôt d'une couche 306 à base de résine ou d'un polymère photosensible, par exemple une couche de résine SJR 5740 (marque déposée) de la société Chipley d'une dizaine de micromètres d'épaisseur, sur le support 300. On effectue ensuite un procédé de photolithographie afin de former une pluralité de trous dans la couche 306. Au cours de ce procédé de photolithographie, on expose tout d'abord la couche 306 à un rayonnement par exemple ultraviolet et au travers d'un masque (non représenté) comportant des motifs opaques audit rayonnement. Lesdits motifs peuvent être identiques et régulièrement répartis sur le masque. Ces derniers sont de préférence espacés entre eux d'un pas constant . L'exposition de la couche 306 peut être effectuée sans alignement des motifs du masque avec un ou plusieurs quelconques dessins, points de références, ou marques d'alignements situés sur la puce 300. Ainsi, un alignement réalisé de manière directe ou indirecte des motifs du masque avec les plots conducteurs 302 de la puce 300, n'est par exemple pas nécessaire. La couche 306 est ensuite révélée. Cette dernière comporte alors un ensemble de trous 307 transversaux dévoilant le fond conducteur 300 et dont la répartition dans la couche 306 dépend de celle des motifs du masque. Cette répartition peut être uniforme. Les trous 307 peuvent avoir par exemple un diamètre de l'ordre de 3 micromètres et peuvent être espacés entre eux par exemple d'un pas de 6 micromètres (figure 4A) . On réalise ensuite une gravure du fond conducteur 305 à travers les trous 307, de manière à prolonger ces derniers. Après gravure du fond conducteur, certains trous notés 307a parmi l'ensemble des trous 307 dévoilent la couche de passivation 304, certains autres notés 307b dévoilent les plots conducteurs 302. Le fond conducteur 305 peut être éventuellement surgravé de manière à ce que les trous 307 comportent chacun une première partie notée 308 située au niveau de la couche 306 et une seconde partie notée 309 à fond élargi, dans le prolongement de la première partie 308 (figure 4B) . Puis, on effectue le remplissage des trous 307, par croissance électrolytique de métal tel que le cuivre, le nickel, le titane, le tungstène, un alliage SnPb, l'or, etc. en se servant du fond conducteur 301 comme électrode. Les trous 307b dévoilant les plots conducteurs 302 sont remplis de préférence depuis leur fond jusqu'à la surface de la couche 306 de manière à former des tiges conductrices 310. Dans le même temps, étant donné la nature de leur fond, les trous 307a qui dévoilent la couche de passivation, 304 se remplissent généralement peu et de manière moins rapide que les trous 307b. Des tiges conductrices dites « parasites » de taille généralement très inférieures à celle des tiges 310 ou des dépôts 312 « parasites » peuvent éventuellement se former dans les trous 307a (figure 4C) . L'adhérence de ces tiges ou de ces dépôts « parasites » 312 sera généralement faible. Selon une variante de réalisation, le procédé peut comprendre en outre après le remplissage des trous 307, une étape de dépôt chimique à base de métal noble sur les tiges conductrices 310. Cette étape de placage anélectrolytique/dépôt autocatalytique à base de métal noble sur les tiges conductrices 310 peut permettre d' améliorer la conductance globale de ces dernières . Ensuite, on retire la couche 306 au moyen d'un procédé de décapage, par exemple à l'aide d'un solvant tel que l'acétone. Au moins certains des éventuels dépôts « parasites » peu adhérents vis-à-vis de la couche de passivation 304, disparaissent alors au moins partiellement (figure 4D) . Enfin, on effectue le retrait du fond conducteur 305 par un procédé de nettoyage approprié, Dans le cas où le fond conducteur 305 est formé d'un empilement d'une couche à base de titane et d'une couche à base de cuivre, le procédé de nettoyage peut comprendre une étape de retrait de la couche à base de titane par exemple à l'aide d'un premier bain à base d'ammoniac et d'eau oxygénée, et d'une autre étape de retrait de la couche à base de cuivre par exemple à l'aide d'un second bain à base d'acide fluorhydrique. Un procédé de type « lift-off », peut compléter ce procédé de nettoyage. D'éventuelles tiges « parasites » ou dépôts « parasites » disparaissent alors complètement (figure 4E) . Le dispositif microélectronique ainsi obtenu à partir du procédé précédemment décrit est formé d'une puce 300 dotée de plots conducteurs 302 insérés dans une couche de passivation 304. Sur chacun des plots conducteurs 302 sont localisés une pluralité de tiges conductrices, présentant un angle non nul avec un plan principal de la puce . La figure 5 illustre l'assemblage entre la puce 300 et un substrat d'interconnexion 500. La puce 300 est dotée des tiges conductrices 310 formées à partir du procédé précédemment décrit et localisées sur ses plots conducteurs 302. Les plots conducteurs de la puce 300 et des plots de connexion 501 du substrat d'interconnexion 500 sont disposés en vis-à-vis. Le substrat 500 est recouvert de colle 400 en vue d'être assemblé avec la puce 300. Après assemblage, la connexion électrique entre le substrat 500 et la puce 300 sera assurée par une technique d' interconnexion mise en oeuvre suivant l'invention. Cette technique permet de réaliser l'assemblage de composants présentant des défauts de planéité importants lorsque lesdits composants sont munis des tiges conductrices localisées plutôt que recouverts d'un film conducteur anisotrope comme celui décrit dans l'art antérieur. Par ailleurs, l'emploi de tiges conductrices localisées uniquement sur des plots d'un composant, permet de préserver d'éventuelles zones sensibles situées sur ledit composant ou sur un autre composant avec lequel ce dernier est amené à d'être assemblé . Un procédé suivant l'invention, de fabrication de tiges conductrices sur un composant électronique doté d'un ou plusieurs plots conducteurs, met en oeuvre au moins une étape d'isolation d'un fond conducteur, en dehors de zones situées en regard des plots conducteurs. Cette isolation comporte par exemple la réalisation de trous, dans une couche de masquage déposée sur le fond conducteur, uniquement en regard ou au dessus des plots (figure 2C) . Selon un autre exemple, cette isolation met en œuvre la réalisation d'une fine couche isolante que l'on grave au dessus des plots (figure 3A) . Selon un troisième exemple, cette isolation met en œuvre la gravure du fond conducteur à travers les trous d'un masquage, préalablement au remplissage de ces trous par un matériau conducteur (figure 4B) . 106 (for example a polyimide layer of ten micrometers thick) is then deposited on the thin perforated layer 103 (FIG. 3B). The photosensitive resin layer 106 is exposed through a second mask (not shown) comprising openings and opaque parts arranged as a function of the location of the conductive pads 102. The resin layer 106 is then developed so as to produce a layer openwork with holes 107 grouped in areas arranged above the conductive pads. Some holes 107b are located in look of the pads and update the conductive layer 105. Some other holes 107a, the bottom of which reveals the thin layer 103 of resin are not located opposite any of the pads 102 (Figure 3C). We then follow the steps of the example process previously described illustrated in Figures 2D to 2F. The holes 107b are filled by electrolysis using the conductive bottom 105 as an electrode to form conductive rods. The holes 107a, the bottom of which reveals the thin layer of resin 103 do not fill. Then the thin layer of resin 103 and the other layer of resin 106 are removed. Finally, the conductive layer 105 is selectively etched, so that the latter is only stored under the conductive rods 110. Another example of a method of manufacturing a microelectronic device implemented according to the present invention goes to present be described in connection with Figures 4A-4E. In this variant, the microelectronic device according to the invention is this time formed from a chip 300, provided with conductive pads 302 based on metal such as for example copper, inserted in a passivation layer 304 based on a dielectric such as for example Si0 2 . In this exemplary method, a continuous conductive bottom 305 is firstly deposited on the chip 300 and covers the conductive pads 302 as well as the passivation layer 304. The continuous conductive bottom 305 can be formed of a conductive layer or of a stack of several conductive layers. Such a stack can be formed for example of a first conductive layer, for example a layer based on titanium with a thickness of the order of 300 Angstrom, covered with a second conductive layer, for example based on copper and d thickness of the order of 2500 Angstroms. Next, a layer 306 based on resin or a photosensitive polymer is deposited, for example a layer of resin SJR 5740 (registered trademark) from the company Chipley, about ten micrometers thick, on the support. 300. A photolithography process is then carried out in order to form a plurality of holes in the layer 306. During this photolithography process, the layer 306 is first exposed to radiation, for example ultraviolet radiation and through a mask (not shown) comprising patterns opaque to said radiation. Said patterns can be identical and regularly distributed over the mask. The latter are preferably spaced apart by a constant pitch. The exposure of the layer 306 can be carried out without aligning the patterns of the mask with one or more any drawings, reference points, or alignment marks located on the chip 300. Thus, an alignment performed directly or indirectly of the patterns of the mask with the conductive pads 302 of the chip 300, for example is not necessary. Layer 306 is then revealed. The latter then comprises a set of transverse holes 307 revealing the conductive bottom 300 and the distribution of which in the layer 306 depends on that of the patterns of the mask. This distribution can be uniform. The holes 307 can for example have a diameter of the order of 3 micrometers and can be spaced apart from each other for example by a pitch of 6 micrometers (FIG. 4A). An etching of the conductive bottom 305 is then carried out through the holes 307, so as to extend the latter. After etching the conductive bottom, certain holes denoted 307a among all of the holes 307 reveal the passivation layer 304, certain others denoted 307b reveal the conductive pads 302. The conductive bottom 305 may possibly be over-etched so that the holes 307 each comprise a first part denoted 308 located at the level of the layer 306 and a second part denoted 309 with an enlarged bottom, in the extension of the first part 308 (FIG. 4B). Then, the holes 307 are filled, by electrolytic growth of metal such as copper, nickel, titanium, tungsten, an SnPb alloy, gold, etc. using the conductive bottom 301 as an electrode. The holes 307b revealing the conductive pads 302 are preferably filled from their bottom to the surface of the layer 306 so as to form conductive rods 310. At the same time, given the nature of their bottom, the holes 307a which reveal the passivation layer, 304 fill up generally little and slower than holes 307b. Conductive rods said to be “parasitic” in size generally much smaller than that of rods 310 or deposits “parasitic” can possibly form in the holes 307a (FIG. 4C). The adhesion of these rods or of these “parasitic” deposits 312 will generally be weak. According to an alternative embodiment, after the filling of the holes 307, the method can further comprise a step of chemical deposition based on noble metal on the conductive rods 310. This step of anelectrolytic plating / autocatalytic deposition based on noble metal on the conductive rods 310 can improve the overall conductance of the latter. Then, the layer 306 is removed by means of an etching process, for example using a solvent such as acetone. At least some of the possible “parasitic” deposits that are not very adherent with respect to the passivation layer 304, then disappear at least partially (FIG. 4D). Finally, the conductive bottom 305 is removed by an appropriate cleaning process. In the case where the conductive bottom 305 is formed by a stack of a layer based on titanium and a layer based on copper, the cleaning process can comprise a step of removing the titanium-based layer, for example using a first bath based on ammonia and hydrogen peroxide, and another step of removing the layer copper base for example at using a second hydrofluoric acid-based bath. A “lift-off” type process can complete this cleaning process. Any “parasitic” stems or “parasitic” deposits then disappear completely (Figure 4E). The microelectronic device thus obtained from the previously described method is formed by a chip 300 provided with conductive pads 302 inserted in a passivation layer 304. On each of the conductive pads 302 are located a plurality of conductive rods, having a non-zero angle with a main plane of the chip. FIG. 5 illustrates the assembly between the chip 300 and an interconnection substrate 500. The chip 300 is provided with conductive rods 310 formed from the method described above and located on its conductive pads 302. The conductive pads of the chip 300 and connection pads 501 of the interconnection substrate 500 are arranged opposite. The substrate 500 is covered with adhesive 400 in order to be assembled with the chip 300. After assembly, the electrical connection between the substrate 500 and the chip 300 will be ensured by an interconnection technique implemented according to the invention. This technique allows the assembly of components having significant flatness defects when said components are provided with localized conductive rods rather than covered with an anisotropic conductive film like that described in the prior art. Furthermore, the use of conductive rods located only on the pads of a component, makes it possible to preserve any sensitive zones located on said component or on another component with which the latter is brought to be assembled. A method according to the invention, for manufacturing conductive rods on an electronic component provided with one or more conductive pads, implements at least one step of isolating a conductive bottom, outside of zones located opposite the pads conductors. This insulation comprises for example the production of holes, in a masking layer deposited on the conductive bottom, only facing or above the studs (FIG. 2C). According to another example, this insulation implements the production of a thin insulating layer which is etched above the studs (FIG. 3A). According to a third example, this insulation implements the etching of the conductive bottom through the holes of a masking, before the filling of these holes with a conductive material (FIG. 4B).

Claims

REVENDICATIONS
1. Procédé de fabrication de tiges conductrices (210,310) sur un composant électronique (200,300) doté d'un ou plusieurs plots conducteurs (202,302), chacune des tiges conductrices étant en contact au moins partiel avec un plot du composant électronique comportant les étapes de : - dépôt d'un fond conducteur (105,305) sur ledit composant, - dépôt d'une couche de masquage (106, 206, 306) sur ledit fond conducteur (105,305), - formation dans ladite couche de masquage d'une pluralité de trous (207, 307, 107), au moins un plot conducteur parmi lesdits plots conducteurs étant situé en regard d'un ou plusieurs trous, - remplissage par electrolyse de trous à base d'un matériau conducteur afin de former les tiges conductrices (210,310), - retrait de la couche de masquage (206,306) .1. A method of manufacturing conductive rods (210,310) on an electronic component (200,300) provided with one or more conductive pads (202,302), each of the conductive rods being in at least partial contact with a pad of the electronic component comprising the steps of : - deposition of a conductive base (105.305) on said component, - deposition of a masking layer (106, 206, 306) on said conductive base (105.305), - formation in said masking layer of a plurality of holes (207, 307, 107), at least one conductive pad among said conductive pads being located opposite one or more holes, - electrolysis filling of holes based on a conductive material to form the conductive rods (210,310 ), - removal of the masking layer (206,306).
2. Procédé de fabrication de tiges conductrices (210,310) sur un composant électronique (200,300) selon la revendication 1, dans lequel, à l'étape de formation dans ladite couche de masquage d'une pluralité de trous (207, 307, 107), au moins un plot conducteur parmi lesdits plots conducteurs est situé en regard d'un ou plusieurs trous, au moins un trou parmi lesdits trous n'a aucun desdits plots conducteur en regard, le procédé comprenant en outre, après l'étape de formation de la pluralité de trous et préalablement au remplissage par electrolyse : - la gravure du fond conducteur (305) à travers les trous (307) .2. A method of manufacturing conductive rods (210,310) on an electronic component (200,300) according to claim 1, wherein, in the step of forming in said masking layer a plurality of holes (207, 307, 107) , at least one conductive pad among said conductive pads is located opposite one or more holes, at least one hole among said holes has none of said conductive pads facing, the method further comprising, after the step of forming the plurality of holes and prior to filling by electrolysis: - the etching of the conductive bottom (305) through the holes (307).
3. Procédé de fabrication de tiges conductrices (210,310) sur un composant électronique (200,300) selon la revendication 1, dans lequel, à l'étape de formation dans ladite couche de masquage d'une pluralité de trous (207, 307, 107), au moins un plot conducteur parmi lesdits plots conducteurs est situé en regard d'un ou plusieurs trous, au moins un trou parmi lesdits trous n'a aucun desdits plots conducteur en regard, le procédé comportant en outre : entre le dépôt du fond conducteur (105,305) sur ledit composant et le dépôt de la couche de masquage (106, 206, 306) sur ledit fond conducteur, les étapes de : - dépôt d'une fine couche isolante (103) sur le fond conducteur (105) , - formation d'une pluralité d'ouvertures3. A method of manufacturing conductive rods (210,310) on an electronic component (200,300) according to claim 1, wherein, in the step of forming in said masking layer a plurality of holes (207, 307, 107) , at least one conductive pad among said conductive pads is located opposite one or more holes, at least one hole among said holes has none of said conductive pads facing, the method further comprising: between the deposition of the conductive bottom (105,305) on said component and the deposition of the masking layer (106, 206, 306) on said conductive bottom, the steps of: - depositing a thin insulating layer (103) on the conductive bottom (105), - formation of a plurality of openings
(104) dans ladite fine couche isolante, chaque ouverture étant située en regard d'un plot conducteur.(104) in said thin insulating layer, each opening being located opposite a conductive pad.
4. Procédé selon la revendication 3, caractérisé en ce que parmi la pluralité de trous (107) formés à l'étape de formation des trous dans la couche de masquage, certains trous (107a) dévoilent la fine couche isolante (103) , certains autres trous (107b) dévoilent le fond conducteur. 4. Method according to claim 3, characterized in that among the plurality of holes (107) formed in the step of forming holes in the masking layer, some holes (107a) reveal the thin insulating layer (103), some other holes (107b) reveal the conductive bottom.
5. Procédé de fabrication de tiges conductrices (110) sur un composant électronique (100) selon la revendication 1, dans lequel, à l'étape de formation dans ladite couche de masquage d'une pluralité de trous (107) , chaque trou est au moins partiellement situé en regard d'un plot conducteur.5. A method of manufacturing conductive rods (110) on an electronic component (100) according to claim 1, wherein, in the step of forming in said masking layer a plurality of holes (107), each hole is at least partially located opposite a conductive pad.
6. Procédé selon la revendication 5, comprenant en outre, après l'étape de formation dans ladite couche de masquage d'une pluralité de trous et préalablement à l'étape de remplissage par electrolyse : - la gravure du fond conducteur à travers les trous .6. The method of claim 5, further comprising, after the step of forming in said masking layer a plurality of holes and prior to the step of filling by electrolysis: - the etching of the conductive bottom through the holes .
7. Procédé selon l'une des revendications 1 à 6, ladite couche de masquage comprenant au moins une couche de polymère photosensible. 7. Method according to one of claims 1 to 6, said masking layer comprising at least one layer of photosensitive polymer.
8. Procédé selon l'une des revendications 1 à 7, dans lequel lesdits plots conducteurs sont insérés dans une couche de passivation (304) recouvrant ledit composant électronique . 8. Method according to one of claims 1 to 7, wherein said conductive pads are inserted in a passivation layer (304) covering said electronic component.
9. Procédé selon l'une des revendications9. Method according to one of claims
1 à 8, le fond conducteur (105,305) étant formé d'un empilement d' au moins deux couches conductrices dif érentes . 1 to 8, the conductive bottom (105,305) being formed of a stack of at least two different conductive layers.
10. Procédé selon l'une des revendications10. Method according to one of claims
1 à 9, comportant en outre après l'étape de retrait de la couche de masquage, une étape de retrait au moins partiel du fond conducteur ou de gravure sélective du fond conducteur.1 to 9, further comprising after the step of removing the masking layer, a step of at least partial removal of the conductive background or selective etching of the conductive background.
11. Procédé selon l'une des revendications 1 à 10, comprenant en outre après l'étape de remplissage par electrolyse, une étape supplémentaire de dépôt chimique à base de métal noble sur les tiges conductrices (310) .11. Method according to one of claims 1 to 10, further comprising after the step of filling by electrolysis, an additional step of chemical deposition based on noble metal on the conductive rods (310).
12. Dispositif microélectronique susceptible d'être obtenu par le procédé selon l'une des revendications 1 à 11. 12. Microelectronic device capable of being obtained by the method according to one of claims 1 to 11.
EP05717721A 2004-02-25 2005-02-24 Microelectronic interconnect device comprising localised conductive pins Withdrawn EP1719173A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0450349A FR2866753B1 (en) 2004-02-25 2004-02-25 MICROELECTRONIC INTERCONNECTION DEVICE WITH LOCALIZED CONDUCTIVE RODS
PCT/FR2005/050123 WO2005086232A1 (en) 2004-02-25 2005-02-24 Microelectronic interconnect device comprising localised conductive pins

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EP (1) EP1719173A1 (en)
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US20070166978A1 (en) 2007-07-19
WO2005086232A1 (en) 2005-09-15
US7563703B2 (en) 2009-07-21
FR2866753A1 (en) 2005-08-26

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