WO2004057667A3 - Procede de reroutage de dispositifs microelectroniques sans lithographie - Google Patents

Procede de reroutage de dispositifs microelectroniques sans lithographie Download PDF

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Publication number
WO2004057667A3
WO2004057667A3 PCT/FR2003/050188 FR0350188W WO2004057667A3 WO 2004057667 A3 WO2004057667 A3 WO 2004057667A3 FR 0350188 W FR0350188 W FR 0350188W WO 2004057667 A3 WO2004057667 A3 WO 2004057667A3
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WIPO (PCT)
Prior art keywords
wafer
contact pads
output contact
input
chip
Prior art date
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PCT/FR2003/050188
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English (en)
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WO2004057667A2 (fr
Inventor
Francois Baleras
Fanny Delaguillaumie
Marc Zussy
Original Assignee
Commissariat Energie Atomique
Francois Baleras
Fanny Delaguillaumie
Marc Zussy
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Application filed by Commissariat Energie Atomique, Francois Baleras, Fanny Delaguillaumie, Marc Zussy filed Critical Commissariat Energie Atomique
Priority to US10/538,889 priority Critical patent/US20060128134A1/en
Priority to EP03809999A priority patent/EP1573805A2/fr
Publication of WO2004057667A2 publication Critical patent/WO2004057667A2/fr
Publication of WO2004057667A3 publication Critical patent/WO2004057667A3/fr

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    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de réalisation d'un boîtier à la taille d'une puce électronique et réalisé à l'échelle du substrat, le substrat comportant au moins une puce et ladite au moins une puce possédant des plots d'entrée-sortie sur une face du substrat dite face avant, le procédé comprenant les étapes suivantes : a) formation, au moyen d'un moule ou d'un pochoir complexe, d'une couche isolante de relaxation de contraintes sur ladite face avant, ladite couche de relaxation recouvrant la face avant du substrat avec un relief présentant des puits d'accès au niveau des plots d'entrée-sortie, et ailleurs, des parties en saillie destinées à relaxer les contraintes, chaque partie en saillie ayant une forme étagée comprenant au moins une zone proéminente et au moins une zone, en retrait par rapport à ladite zone proéminente, destinée à supporter un plot de connexion électrique, b) formation de pistes électriquement conductrices sur la couche de relaxation pour connecter les plots d'entrée/sortie aux plots de connexion électrique correspondants, c) formation de moyens de contact électrique vers l'extérieur sur les plots de connexion électrique. L'invention concerne également, d'une part, un moule ou pochoir complexe destiné à réaliser un boîtier à la taille d'une puce selon le procédé de l'invention, et d'autre part, ledit boîtier en lui-même.
PCT/FR2003/050188 2002-12-18 2003-12-17 Procede de reroutage de dispositifs microelectroniques sans lithographie WO2004057667A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/538,889 US20060128134A1 (en) 2002-12-18 2003-12-17 Method for re-routing lithography-free microelectronic devices
EP03809999A EP1573805A2 (fr) 2002-12-18 2003-12-17 Procede de reroutage de dispositifs microelectroniques sans lithographie

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0216117A FR2849270A1 (fr) 2002-12-18 2002-12-18 Procede de reroutage de dispositifs microelectroniques sans lithographie
FR02/16117 2002-12-18

Publications (2)

Publication Number Publication Date
WO2004057667A2 WO2004057667A2 (fr) 2004-07-08
WO2004057667A3 true WO2004057667A3 (fr) 2004-08-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2003/050188 WO2004057667A2 (fr) 2002-12-18 2003-12-17 Procede de reroutage de dispositifs microelectroniques sans lithographie

Country Status (4)

Country Link
US (1) US20060128134A1 (fr)
EP (1) EP1573805A2 (fr)
FR (1) FR2849270A1 (fr)
WO (1) WO2004057667A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007056183A1 (fr) * 2005-11-02 2007-05-18 Second Sight Medical Products, Inc. Dispositif microélectronique implantable et procédé de fabrication
US8143173B2 (en) * 2006-11-22 2012-03-27 Seiko Epson Corporation Method for manufacturing semiconductor device
US20090298277A1 (en) * 2008-05-28 2009-12-03 Mackay John Maskless Process for Solder Bumps Production
CN103065985B (zh) * 2011-10-21 2015-04-22 中国科学院上海微系统与信息技术研究所 双面布线封装的圆片级大厚度光敏bcb背面制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20020063332A1 (en) * 2000-09-19 2002-05-30 Yoshihide Yamaguchi Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure
US20020076911A1 (en) * 2000-12-15 2002-06-20 Lin Charles W.C. Semiconductor chip assembly with bumped molded substrate
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20020063332A1 (en) * 2000-09-19 2002-05-30 Yoshihide Yamaguchi Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure
US20020076911A1 (en) * 2000-12-15 2002-06-20 Lin Charles W.C. Semiconductor chip assembly with bumped molded substrate

Also Published As

Publication number Publication date
US20060128134A1 (en) 2006-06-15
FR2849270A1 (fr) 2004-06-25
WO2004057667A2 (fr) 2004-07-08
EP1573805A2 (fr) 2005-09-14

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