US20060128134A1 - Method for re-routing lithography-free microelectronic devices - Google Patents

Method for re-routing lithography-free microelectronic devices Download PDF

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US20060128134A1
US20060128134A1 US10/538,889 US53888905A US2006128134A1 US 20060128134 A1 US20060128134 A1 US 20060128134A1 US 53888905 A US53888905 A US 53888905A US 2006128134 A1 US2006128134 A1 US 2006128134A1
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substrate
front face
polymer
relaxation layer
forming
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US10/538,889
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Francois Baleras
Fanny Delaguillaumie
Marc Zussy
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention is related to a method for the manufacture of an electronic chip package produced at the substrate level (Wafer Level Chip Scale Package or WLCSP).
  • WLCSP Wafer Level Chip Scale Package
  • the aforementioned package described in the invention will be referred to as a chip-scale package.
  • the invention is also concerned with complex moulds or stencils used to produce the aforementioned chip-scale package in accordance with the method in the invention and is also concerned with the aforementioned chip-scale package itself.
  • the second defect is induced by the large differences in thermal expansion between the package and the receiving substrate (printed circuit).
  • the very large differences in thermal expansion will, especially for ball grid array packages, produce significant stresses in the balls with variations in temperature. These stresses may be sufficiently large to rupture the balls used for the connections. Miniaturisation of packages, therefore, also requires improvements to be made in the reliability of the packaging.
  • the widely used method involves rerouting of the integrated circuit inputs/outputs (see FIG. 1 and the document [1] referred to at the end of this description).
  • FIG. 1 shows a longitudinal section view of a chip-scale package 1 produced using the technique explained in document [1].
  • a substrate 2 made up of integrated circuits whose input/output pads are labelled 3 is covered with an insulating layer or passivation layer 4 .
  • spin coating is usually used for polymers, or vapour phase chemical deposition for minerals.
  • the above insulating layer is then opened, either by exposure of the polymer through a masque, or by lithography and etching (that is, by the deposit of a photosensitive resin, then exposure through a masque).
  • the rerouting process itself then commences: first a continuous layer is vaporised onto the integrated circuit, then electrolysis of copper is carried out across a photosensitive resin; this resin is then stripped away and etching of the continuous background takes place.
  • the rerouting lines 5 are obtained in this way.
  • a new insulating layer 6 is deposited, which provides demarcation for soldering and finally metallization of the integrated circuit takes place either by spraying or by UBM (“under bump metallization”) chemical deposition; UBM is a metallurgical process for attaching fusible balls 7 .
  • rerouting lines 5 (conductive) are obtained which join input/output pads to the fusible balls 7 .
  • the second problem related to this method of manufacture is that if the CSP packages (chip-scale packages) are mounted on printed circuits without resin being interposed (called “underfill” in the technique concerned), the connections produced will then be very weak. Differences in thermal expansion between the CSP and the printed circuit then result in stresses in the peripheral balls, especially if the integrated circuits are wide. For this type of package, therefore, it is essential to add a resin “underfill” beneath the package in order to distribute the stresses over the balls and the “underfill” resin.
  • the problem is that the use of this resin is not necessarily needed for all applications and this generally adds at least one additional step. In addition, the use of this resin makes the repair of components more difficult, since it requires that a defective package be replaced by a new one.
  • FIG. 2 A chip-scale package produced using the technique of document [2] is shown in FIG. 2 in a longitudinal cross-section view.
  • a WLCSP package 11 made up of a substrate 12 , integrated circuit pads 13 and a passivation layer 14 .
  • the difference in relation to the previous document is due to the presence of thick slabs of polymer 18 between the front face of the substrate 12 and the fusible balls 17 . These thick polymer slabs allow the stresses between the chip-scale package and the printed circuit to relax.
  • Rerouting of the input-output pads 13 is achieved through spraying a metallic under-layer followed by Cu/Ni electrolysis across a photosensitive resin. After removing the resin and the under-layer, the rerouting lines 15 are obtained; the “spin coating” method is then used to deposit a photosensitive insulating layer 16 . This layer is then exposed through a mask in order to delimit the fusible ball solder pads 17 . Finally, after the transfer of the fusible balls, integrated circuits are divided to obtain chip-scale packages.
  • This manufacturing method for WLCSP packages allows manufacturing costs to be reduced (the polymer slabs are deposited using screen printing, a low cost process) and reduces mechanical stresses acting on the fusible balls.
  • the method used to deposit the polymer does not allow the integrated circuit input/output pads to be insulated.
  • the method requires at least two lithographic steps: a step to delimit the metallic tracks and a step to open up the passivation that has been deposited on the metallic tracks.
  • the invention proposes a low cost manufacturing method for WLCSP packages which involves packaging of the integrated circuit at substrate scale and which does not exhibit the problems seen in the prior art.
  • the method that is the subject of the invention involves using a mould or stencil to create a layer which relaxes stresses between the chip-scale package and the printed circuit to which the said chip-scale package is connected, giving it a tiered shape which subsequently allows rerouting of inputs/outputs to be achieved with fewer lithographic steps than in prior art, or even none at all.
  • the method for producing a chip-scale electronic package at the substrate level includes the following steps:
  • each protruding part having a tiered shape made up of at least one protuberant zone and at least one zone that is recessed in relation to the aforementioned protuberant zone and is intended to support an electrical bonding pad,
  • integrated circuits located on the substrate will include input/output pads in aluminium, copper or other materials and a passivation layer in mineral or organic materials or both. These circuits may also include various finishes, for example, a Ni/Au chemical deposit.
  • the aforementioned procedure further includes, between the above steps b) and c), a step for the formation of an encapsulation layer on the relaxation layer, with exposure of the electrical bonding pads.
  • the stress relaxation layer may be created using various methods.
  • the aforementioned layer may be created using a mould.
  • the steps are as follows:
  • the aforementioned layer may this time be created using a stencil.
  • the steps are as follows:
  • the polymer may be cured and the stencil then separated from the substrate, but the separation of the stencil may in certain cases also be carried out before curing the polymer.
  • the aforementioned given relaxation polymer used in the above production methods is selected from amongst polyimide, BCB or any other polymer that is capable of stress relaxation.
  • the rerouting step or step for formation of electrically conductive tracks to connect integrated circuits input/output pads to the corresponding electrical bonding pads is simplified as a result of the complex topology of the previously created relaxation layer.
  • the complex topology of the relaxation layer means that this rerouting step for the integrated circuit inputs/outputs may not require a lithographic step. In this case, two options are available:
  • the conductive material is a metal.
  • the deposition of conductive material mentioned earlier involves metallization.
  • spraying, evaporation, electro-deposition or chemical deposition of one or more metals is carried out.
  • encapsulation of packages can be carried out in order to extend their working life.
  • encapsulation may be total or partial.
  • the encapsulation formation step involves the following steps:
  • the encapsulation formation step involves the following steps:
  • the freeing up of electrical bonding pads is achieved by lapping, mechanical/chemical polishing, etching or by any other technique.
  • step may be carried out before or after the levelling of the substrate, but it is preferably carried out after levelling. Actually, levelling allows demarcation of electrical bonding pads to be carried out.
  • the means of making electrical contact with the exterior on electrical bonding pads are fusible balls.
  • fusible balls will be installed on the electrical bonding pads by a technique selected from electrolysis of a fusible alloy, screen-printing of solder paste, transfer of balls or any other technique.
  • these means of electrical contact are chosen from anisotropic conductive films and adhesives.
  • step for separation of chip-scale packages must be carried out. This separation or marking out is performed by making cuts using a saw, laser etching or any other similar means.
  • This method for manufacturing WLCSP packages may be supplemented by additional steps.
  • the rear face of the substrate is made thinner by lapping, mechanical/electrical polishing or any other technique.
  • the substrate thickness can be reduced to 50 ⁇ m. Reduction of the thickness until it reaches the active thickness of the silicon may even be envisaged.
  • the method may also be supplemented by the following steps:
  • the invention is also concerned with complex moulds or stencils designed to create a chip-scale package as described in the method in the invention.
  • these complex moulds or stencils are made using at least one technique from amongst wet or dry etching, electroforming, adhesion of several pierced or un-pierced polymer films, moulding, laser etching or any other technique which allows a complex topography to be created.
  • the aforementioned moulds or stencils are made from silicon, metal, polymer or any similar material. It should be noted that releasing small parts from moulds is facilitated by the use of polymer moulds or stencils.
  • the invention is also concerned with chip-scale packages manufactured at the substrate level characterised by the fact that they are produced using the method as described in the invention.
  • the method as described in the invention offers a number of advantages, notably a reduction in the number of steps in the manufacture of chip-scale packages.
  • the moulding or stencil technique allows to create at the same time the topology required to create rerouting of input/outputs and the thermo-mechanical stress relaxation layer.
  • the aforementioned moulds or stencils also allow the number of photolithographic steps to be reduced. Consequently, they reduce the total number of steps required for the manufacture of the chip-scale package and in this way reduce the manufacturing cost of the aforementioned package.
  • these moulds or stencils may be re-used, which also reduces the cost of package manufacture.
  • FIGS. 1 and 2 illustrate the existing practices presented earlier in this description
  • FIGS. 3 a and 3 b illustrate the topology of the complex mould ( FIG. 3 a ) and of the complex stencil ( FIG. 3 b ) as described in the invention
  • FIGS. 4 a to 4 g illustrate one method of manufacture of WLCSP packages as described in the invention
  • FIGS. 5 a to 5 c illustrate a supplement to manufacture in order to obtain complete encapsulation of the integrated circuit
  • FIGS. 6 a to 6 g illustrate another method of manufacture of WLCSP packages in accordance with the invention
  • FIG. 7 illustrates encapsulation of all surfaces of the integrated circuit created at substrate level.
  • FIGS. 4 a to 4 g A method for manufacturing a WLCSP package in accordance with the present invention is shown in FIGS. 4 a to 4 g.
  • FIG. 4 a shows, a substrate 22 made up of integrated circuit with each circuit having input/output pads 23 and a passivation layer 24 is provided, with the aforementioned elements being obtained by methods described in the prior art.
  • step b the said stress relaxation layer labelled 28 is made on the said substrate ( FIG. 4 b ).
  • This step is carried out either by moulding of the polymer onto the substrate using a complex mould, or by screen printing of the polymer through a complex stencil onto the substrate or by transfer of the polymer (by creating the polymer structure on another support using a complex mould or stencil, and then adhering it onto the substrate).
  • This step may be accompanied by a cleaning process (for example plasma treatment) to remove polymer residues from integrated circuit input/output pads 23 .
  • a cleaning process for example plasma treatment
  • a metallic layer labelled 25 is deposited over the entire surface of the substrate (by spraying on a layer of titanium/copper, for example) ( FIG. 4 c ). If it is wished to increase the thickness of the metallic layer, this step may be supplemented by an electro-deposition of copper.
  • This metallization step may also be carried out by chemical deposition of Ni/Au over the entire surface or by selective deposition (localised metallization in access wells and in recessed zones).
  • the front face of the substrate is levelled by the deposition of an insulating layer, labelled 29 , for example by dispensation of “underfill” resin that is levelled by spin coating, by moulding of a polymer or by any other technique ( FIG. 4 e ).
  • This insulating layer is then opened up by plasma etching, polishing or by any other technique to release the ball attachment pads ( FIG. 4 f ).
  • a full encapsulation of the integrated circuits may be required.
  • the encapsulation steps must be integrated between steps f and g above.
  • thinning of the rear face of the substrate 22 may be performed by lapping or any other technique, but this step is not mandatory ( FIG. 5 a ).
  • the rear face of substrate 22 is then cut away until the passivation layer 24 of the integrated circuits is reached ( FIG. 5 b ).
  • This operation may be performed by mechanical cutting, by laser or by any other technique.
  • the last step involves full encapsulation of the rear face of the substrate 22 and filling in the slots made earlier ( FIG. 5 c ).
  • This step may be carried out by moulding, by dispensing or by any other technique for depositing insulation (labelled 31 ).
  • FIGS. 6 a to 6 g illustrate another method of manufacture of WLCSP packages. This mode of manufacture involves establishing front face/rear face contact and full encapsulation of the integrated circuits.
  • each attachment pad 40 is surrounded by a slot in order to improve the demarcation of the solder zone.
  • the same steps as those shown in FIGS. 4 d to 4 f are carried out and the device in FIG. 6 b is obtained: the recessed zones and the access wells above the input-output pads have been filled in by deposition of an insulating layer 49 .
  • the thickness of the substrate 42 ( FIG. 6 c ) starts to be reduced. This is not a mandatory step, but it facilitates establishment of contact with the front face of the substrate and later separation of the chip-scale packages.
  • slots are made in the rear face of the substrate to demarcate the integrated circuits (cuts I are made until the passivation layer 44 is reached) and to establish contact between the input/output pads (cuts II are made until the pads 43 are reached).
  • This step may be performed by cutting or by etching. If the etching option is taken, wells are made at the input/output pads 43 .
  • the rear face of the substrate must be insulated by depositing an insulating layer 51 in the cuts; this step may be performed by moulding or screen-printing.
  • the slots at the said pads are partly filled (not shown in the figure).
  • the metallization step may be preceded by an etching step (for example by laser, by plasma etc.) of the insulating layer at the contacts.
  • Metallization of the rear face of the substrate is then carried out using the same method as described previously ( FIG. 6 e ): a metallic layer 55 is obtained which covers the entire rear face of the substrate 42 .
  • the metallization 55 is isolated by mechanical-chemical polishing or by lapping (or by any other technique) of the surface of the rear face of the substrate. This step may be carried out after an encapsulation step (step not illustrated).
  • ball coating of the substrate is performed by placing fusible balls 47 on the attachment pads 40 ( FIG. 6 f ) and separation of the chip-scale packages is performed ( FIG. 6 g ) by cutting at cuts I.
  • chip-scale packages offering front face/rear face rerouting can be assembled and the interstices can be filled in using “underfill” resin.
  • the assembly could also be made after cutting of the chip-scale packages. In this way a three dimensional module is obtained.
  • Total encapsulation of the chip-scale package can also be carried out, that is, encapsulation of the front face and of the rear face of the substrate, possibly after reducing the substrate thickness ( FIG. 7 ).
  • the substrate 72 includes integrated circuits composed of input/output pads 73 and a passivation layer 74 ; the integrated circuits are then covered with a stress relaxation layer 78 which provides access wells which leave the input/output pads 73 accessible, with the said input/output pads and fusible balls 77 which overhang the relaxation layer 78 being linked by re-routing lines 75 .
  • An insulating layer 79 fills the access wells and recessed zones on the front face of the substrate, and an insulating layer 91 covers the rear face of the substrate.
  • FIGS. 6 g and 7 are non-restrictive, it being possible in particular to combine the two versions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
US10/538,889 2002-12-18 2003-12-17 Method for re-routing lithography-free microelectronic devices Abandoned US20060128134A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0216117A FR2849270A1 (fr) 2002-12-18 2002-12-18 Procede de reroutage de dispositifs microelectroniques sans lithographie
PCT/FR2003/050188 WO2004057667A2 (fr) 2002-12-18 2003-12-17 Procede de reroutage de dispositifs microelectroniques sans lithographie

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Publication Number Publication Date
US20060128134A1 true US20060128134A1 (en) 2006-06-15

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US (1) US20060128134A1 (fr)
EP (1) EP1573805A2 (fr)
FR (1) FR2849270A1 (fr)
WO (1) WO2004057667A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080119037A1 (en) * 2006-11-22 2008-05-22 Seiko Epson Corporation Method for manufacturing semiconductor device
US20090298277A1 (en) * 2008-05-28 2009-12-03 Mackay John Maskless Process for Solder Bumps Production
CN103065985A (zh) * 2011-10-21 2013-04-24 中国科学院上海微系统与信息技术研究所 双面布线封装的圆片级大厚度光敏bcb背面制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007056183A1 (fr) * 2005-11-02 2007-05-18 Second Sight Medical Products, Inc. Dispositif microélectronique implantable et procédé de fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
JP4174174B2 (ja) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに半導体装置実装構造体
US6444489B1 (en) * 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080119037A1 (en) * 2006-11-22 2008-05-22 Seiko Epson Corporation Method for manufacturing semiconductor device
US8143173B2 (en) * 2006-11-22 2012-03-27 Seiko Epson Corporation Method for manufacturing semiconductor device
US20090298277A1 (en) * 2008-05-28 2009-12-03 Mackay John Maskless Process for Solder Bumps Production
CN103065985A (zh) * 2011-10-21 2013-04-24 中国科学院上海微系统与信息技术研究所 双面布线封装的圆片级大厚度光敏bcb背面制作方法

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FR2849270A1 (fr) 2004-06-25
WO2004057667A3 (fr) 2004-08-12
WO2004057667A2 (fr) 2004-07-08
EP1573805A2 (fr) 2005-09-14

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