EP1614158A2 - Module multipuces comportant plusieurs puces de semiconducteur et carte de circuits comportant plusieurs composants - Google Patents

Module multipuces comportant plusieurs puces de semiconducteur et carte de circuits comportant plusieurs composants

Info

Publication number
EP1614158A2
EP1614158A2 EP04726437A EP04726437A EP1614158A2 EP 1614158 A2 EP1614158 A2 EP 1614158A2 EP 04726437 A EP04726437 A EP 04726437A EP 04726437 A EP04726437 A EP 04726437A EP 1614158 A2 EP1614158 A2 EP 1614158A2
Authority
EP
European Patent Office
Prior art keywords
semiconductor chips
semiconductor chip
insulation layer
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04726437A
Other languages
German (de)
English (en)
Inventor
Georg Meyer-Berg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1614158A2 publication Critical patent/EP1614158A2/fr
Withdrawn legal-status Critical Current

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Definitions

  • Multichip module with several semiconductor chips and printed circuit board with several components
  • the invention relates to a multichip module with several semiconductor chips and a printed circuit board with several components.
  • Electronic components are known in which a plurality of semiconductor chips are arranged next to one another on a carrier substrate. These semiconductor chips have contact areas, from which wirings originate both for connecting the semiconductor chips to one another and for connecting to external contacts of the carrier substrate.
  • the wiring of the semiconductor chips to each other is often very complex and very cost-intensive.
  • the invention relates to a multichip module with at least two semiconductor chips arranged in one plane on or in a carrier medium.
  • the semiconductor chips each have at least one integrated circuit.
  • at least one second semiconductor chip is designed in relation to a first semiconductor chip in such a way that the active semiconductor side arranged contact surfaces are at least partially mirror-symmetrical to the contact surfaces of the first semiconductor chip, mirror symmetry is understood to mean the reflection on a mirror plane arranged perpendicular to the active top of the semiconductor chip.
  • second semiconductor chips are referred to in the following, this means in principle those semiconductor chips whose contact areas are each mirror-symmetrical to the contact areas of a first semiconductor chip.
  • First semiconductor chips are understood to mean the non-mirrored semiconductor chips.
  • At least one first and at least one second semiconductor chip are arranged side by side and / or one behind the other in the multichip module in such a way that their respective at least partially matching arrangement of. Edges having contact surfaces lie opposite one another. Directly opposite contact areas are connected to each other by first wiring. Second wiring runs from the outer edges of the semiconductor chips, to which no further semiconductor chips are connected directly, to external contacts of the multic ip module, which are arranged in particular on an upper side of the carrier medium.
  • first semiconductor chips and second semiconductor chips which have a mirror-symmetrical arrangement of contact areas with respect to the contact areas of the first semiconductor chip are arranged alternately side by side and / or one behind the other.
  • the opposite ones Edges of the semiconductor chips always have matching arrangements of contact areas. This results in a significantly reduced wiring effort compared to multichip modules that use only one variant of semiconductor chips.
  • the invention is based on the knowledge that opposite edges of semiconductor chips can only have the same arrangement of contact areas if the contact areas of the first of the opposing semiconductor chips are mirror images of the contact areas of the second semiconductor chip.
  • the individual semiconductor chips are short and effectively wired to one another, long and intersecting line routings and the need to provide vias being completely avoided. This is particularly advantageous for long buses. Bus is understood to mean a large number of lines.
  • multichip modules according to the invention can be implemented using all conceivable chip-to-chip connection types.
  • the arrangement of semiconductor chips according to the invention can also be advantageously implemented with conventional printed circuit boards and housed components or chips arranged thereon.
  • the number of first and second semiconductor chips is the same in each case.
  • the first and the second semiconductor chips are alternately side by side and / or one behind the other Level arranged on or in the carrier medium and can form a substantially checkerboard-like pattern.
  • This essentially checkerboard-like pattern does not have to be rectangular or square, but can also have an irregular outer edge profile. It is sufficient that exactly one version of first semiconductor chips and exactly another version of second semiconductor chips are used.
  • a checkerboard-like pattern of first and second semiconductor chips can optionally be easily achieved by rotating the semiconductor chips.
  • the contact areas for external communication should preferably be arranged on these outer edges, while the other edges of the semiconductor chips are best provided with contact areas for internal communication. This difficulty does not arise with ball grid arrays or BGAs, because here the external contacts can be on the inside and the internal contacts on the outside.
  • the contact areas of the second semiconductor chips are at least partially or even completely mirror-inverted with respect to the first semiconductor chips.
  • This results in a particularly simple and inexpensive manufacture of the semiconductor chips since the intermediate masks or reticles used in the manufacture of the semiconductor chips can be used for both versions of the half conductor chips can be used or easily adapted so that they can be used to produce both second and first semiconductor chips in a matching number.
  • First and second semiconductor chips can be produced inexpensively with a single set of masks.
  • the supply lines and / or the ground lines of the semiconductor chips can also be arranged with mirror invariance.
  • wirebonds so-called downbonds, can be provided on the carrier substrate, for example in the spaces between the individual semiconductor chips of the multichip module.
  • the multichip module is implemented using bonding technology.
  • the carrier medium is designed as a circuit substrate which has contact connection surfaces on its first upper side, which are connected in particular via bushings to external contacts arranged on the second upper side of the circuit substrate.
  • the semiconductor chips are applied with their passive rear sides to the first upper side of the circuit substrate, in particular glued on by means of a conductive adhesive;
  • the first wirings are designed as first bond connections.
  • Parts of the second wirings are formed by second bond connections which connect the contact areas to the contact connection areas.
  • the entire multichip module is in a plastic mass, particularly encased in an epoxy resin.
  • the multichip module is implemented using flip-chip technology.
  • the multichip module comprises a motherboard as the carrier medium, on the first upper side of which faces the semiconductor chips, metal wirings of at least one redistribution layer or redistribution layer are arranged. These metal wirings are connected in particular via bushings to external contacts arranged on the second upper side of the main board.
  • the semiconductor chips are connected to these metal wirings via flip-chip contacts.
  • a plastic compound encapsulates the semiconductor chips as well as the first top of the main board.
  • a direct rewiring layer is provided on the semiconductor chips.
  • the carrier medium is formed by a plastic compound which encloses the semiconductor chips with their passive rear sides and with their side surfaces.
  • a structured insulation layer which in particular has polyimide (PI) or benzocyclobutene (BCB), can extend over the active top sides of the semiconductor chips.
  • PI polyimide
  • BCB benzocyclobutene
  • This insulation layer leaves the contact areas of the semiconductor chips free, so that rewiring of one or more rewiring layers can contact the contact areas.
  • the rewiring connects contact areas with neighboring contact areas and / or with external contacts.
  • the external contacts are located on the insulation layer, either above the active upper sides of the semiconductor chips or above the areas between or next to the semiconductor chips Plastic compound.
  • the rewirings run at least partially over areas of the insulation layer.
  • the semiconductor chips are applied with their passive rear side to a circuit carrier, preferably glued on by means of a conductive adhesive layer.
  • the wirings lie in at least one structured rewiring layer which extends over the active top sides of the semiconductor chips and over the regions of the top side of the circuit carrier arranged between or next to them. Because of the difference in level between the active top side of the semiconductor chips and the top side of the circuit carrier, the redistribution layer can be corrugated.
  • the structured rewiring layer has external contact areas, in particular in peripheral areas of the multichip module, on which the external contacts are located. In order to enable a simple connection of the multichip module according to the invention to other components, the top sides of the external contacts protrude above the level of the active top sides of the semiconductor chips and are at a common level.
  • a very stable circuit carrier made of plastic or metal can advantageously be used as the carrier medium, which improves the stability and service life of the multichip modules.
  • a metal circuit carrier it is advantageous to arrange a structured insulation layer below the rewiring layer and lying on top of the circuit carrier. This insulation layer extends at least over the areas not covered by the semiconductor chips. reach the top of the circuit board. For manufacturing reasons, it is not always possible for the areas of the structured insulation layer to be flush with the side faces of the semiconductor chips. Rather, there can be negligible small ones . Spaces arise.
  • transitions made of rubber-elastic material in particular of an elastomer, adjacent to the semiconductor chips.
  • These transitions made of rubber-elastic material can be designed as a second insulation layer.
  • the rewirings of the rewiring layer then rest on this rubber-elastic material and are guided from the active top side of the semiconductor chip to the top side of the circuit carrier or to the top side of the insulation layer, avoiding kinks. Providing such additional transitions ensures robust and reliable wiring.
  • the wiring of the rewiring layer is essentially planar. This results in an even more reliable and robust wiring, which can be designed in particular as a thin-film circuit and can be multi-layered.
  • the semiconductor chip arrangement 1 described above and shown below in FIGS. 1 and 2 can also be implemented analogously on a plastic circuit board with a plurality of functionally largely identical circuit components attached to it.
  • the circuit components can be of any type and can be present, for example, as semiconductor chips or ICs of one or more ball grid arrays or leadframe-based housings.
  • the circuit components can be applied to the printed circuit boards in all conceivable ways, for example by gluing with insulating or conductive glue or by soldering.
  • the circuit components are divided into first and second circuit components.
  • the second circuit components have an at least partially or even completely mirror-image arrangement of contact areas or contact connection areas with respect to the first circuit components.
  • the contacting of the first and second circuit components with one another and with the conductor tracks of the circuit board can take place by wires or by direct contacting of the contact surfaces of the semiconductor chips or the external contact surfaces of the circuit components with the rewiring layers. This results in a largely crossing-free and reliable contact, which can be produced with little wiring effort and is therefore simple and inexpensive.
  • the invention also relates to an electronic component which has one or more semiconductor chips which are applied with their passive back by means of an insulating or conductive adhesive layer to the top of a circuit carrier made of metal or an alloy. These semiconductor chips are thinly ground so that they have a relatively low height of less than 150 ⁇ m.
  • a photo-structured insulation layer in particular made of cardo, bencocyclobutene or polyimide, is arranged between the semiconductor chips and extends over the top of the circuit carrier and covers the areas of the semiconductor
  • Sawing lines are understood to mean those areas between the components in which the electronic components are later sawed apart.
  • relatively small-dimensioned trenches are arranged for production reasons, for example one Have a width of less than 100 ⁇ m and are filled with an insulating material at the top.
  • the layer thickness of the photo-structured insulation layer corresponds approximately to the sum of the height of the thin-ground semiconductor chips and the layer thickness of the adhesive layer arranged under the semiconductor chips.
  • Conduction paths of at least one redistribution layer run on the photo-structured insulation layer and / or on the insulating material of the trenches and / or on the passivation layer of the active top side of the semiconductor chips and / or on the sawing road. These line paths connect the contact areas of the semiconductor chips and / or the external contact areas and / or the carrier and thus possibly the chip backs to one another.
  • the external contact areas are preferably applied to the photo-structured insulation layer and carry external contacts which can be rigid or flexible.
  • the construction of the electronic component according to the invention ensures that the line paths of the rewiring Layer or the rewiring layers each run in one plane and are each very stable.
  • the circuit carrier can advantageously be chosen so that its coefficient of expansion corresponds approximately to the coefficient of expansion of the printed circuit board on which the electronic component is later mounted.
  • coefficients of thermal expansion are usually 11.3 to 16.6 ppm / ° K.
  • Iron-chromium-nickel alloys are particularly suitable as circuit carrier materials, whose thermal expansion coefficients between 11.3 - 16.6 ppm / ° K are adapted to the expansion coefficients of a higher-level circuit board with the help of different iron, chromium and nickel components can. This reliably prevents breakage, cracks and other damage that can occur due to temperature fluctuations or heating as a result of different thermal expansion coefficients.
  • the insulating material of the trenches has the material of the insulating adhesive layer arranged under the semiconductor chip or under the semiconductor chips.
  • Such an electronic component can be produced very inexpensively, especially since the trenches can be filled with insulating adhesive at the same time as the semiconductor chips are inserted into the free areas of the photo-structured insulation layer.
  • the insulating material of the trenches Bencocyclobuten, polyimide, or Cardo, so that the semiconductor chip and electrically conductive can be glued and the Chip Wegse 'iterated is thus grounded. If the insulating material of the trenches from the material of the photostructured insulation layer, the trenches and the areas of the photostructured insulation layer arranged next to it can be particularly clearly distinguished in the electronic component. Even if the insulating material of the trenches and the photo-structured insulation layer is the same, a boundary layer between the edge regions of the photo-structured isolation layer and the trenches can be determined.
  • the height of the insulating material in the trenches can be adapted very precisely to the layer thickness of the photo-structured insulation layer and / or to the height of the semiconductor chip and to the layer thickness of the adhesive layer arranged under the semiconductor chips. Typically, this adjustment takes place in the. Framework of the spin coating process.
  • the invention also relates to a method for producing electronic components.
  • a disk-shaped or rectangular circuit carrier in particular made of metal, e.g. made from an alloy already described above.
  • semiconductor chips are provided and thinly ground to a height of less than 150 ⁇ m. This is e.g. achieved by "dicing before grinding”. These semiconductor chips are usually provided with a photoimide passivation on their upper side.
  • An insulation layer is now applied to a surface of the circuit carrier.
  • This application can be carried out by means of a spin coating process, in which a uniform and continuous coating of the surface of the circuit carrier is achieved with a smooth and flat surface texture.
  • a suitable photoimide With a suitable photoimide, relatively large layer thicknesses of up to 150 ⁇ m can be achieved. Cardo layer thicknesses of up to 150 ⁇ m, polyimide layer thicknesses of up to 30 ⁇ m and bencocyclobutene layer thicknesses of up to 50 ⁇ m can be achieved.
  • the layer thickness of the insulation layer to be applied is to be set such that it corresponds approximately to the sum of the height of the thin-ground semiconductor chip or chips and the layer thickness of the adhesive layer to be applied to the circuit carrier for fastening the semiconductor chips.
  • adhesive layers can, for example, assume a layer thickness of 20 ⁇ m.
  • the insulation layer will . now photo-structured in such a way that depressions in the insulation layer or free areas on the circuit carrier for the semiconductor chips to be applied and for the sawing lines are created.
  • the free areas are often only slightly larger than the base area of the semiconductor chips.
  • the thin-ground semiconductor chips are then coplanarly applied or inserted with their rear side onto the upper side of the circuit carrier by means of the adhesive layer, specifically in the free areas of the insulation layer created by the photo-structuring.
  • An insulating adhesive is recommended for the adhesive layer if it is to completely fill the trenches.
  • any line paths of at least one rewiring layer are applied to this surface, which can connect the contact areas of the semiconductor chips to one another, to external contact areas and to the carrier.
  • any number of rewiring layers can be applied in this process step.
  • external contacts are applied to the external contact surfaces.
  • the component according to the invention is suitable for the application 'of all conceivable solid, rigid or flexible, resilient outer contacts, as for example., In DE 100 16 132 AI are described. Any combinations or mixed forms of such external contacts can also be used.
  • the external contacts are not applied over the semiconductor chips, but rather better on the regions of the insulation layer lying between or next to the semiconductor chips.
  • the semiconductor chips have a different expansion coefficient than the circuit board to which they are connected via the external contacts, which can lead to damage to the external contacts or the electrical component. If the external contacts are placed over the semiconductor chips, it must be ensured that the external contacts are not arranged too far from the center of gravity of the semiconductor chip to prevent damage. Finally, the circuit carrier in the sawing road is sawn into individual multichip modules at the outer edges of the multichip module positions.
  • the method according to the invention also enables the use of particularly robust circuit carriers made of metal or alloys, which increases the stability of the electronic components produced according to the invention.
  • the upper side of the semiconductor chips are at the same level as the upper sides of the insulation layer, which ensures that no difference in level needs to be managed by the line paths of the redistribution layer or the redistribution layers. Rather, the line paths run essentially horizontally, as a result of which particularly reliable and stable wiring is achieved.
  • a multilayer can thus be implemented very advantageously.
  • the trenches between the side faces of the semiconductor chips and the photo-structured insulation layer are filled by applying and by photo-structuring a further insulation layer, which enables the use of conductive adhesives.
  • Photo structuring ensures that the contact surfaces of the semiconductor chips remain freely accessible.
  • This further insulation layer also has a photoimide, in particular polyimide, bencocyclobutene or cardo, and can also be applied to the electronic component by a spin coating process.
  • a photoimide in particular polyimide, bencocyclobutene or cardo
  • the trenches between the side surfaces of the semiconductor chips and the photo-structured insulation layer are filled capillary by the, in particular, insulating adhesive.
  • the amount of adhesive used to apply each semiconductor chip to the circuit carrier is to be dimensioned such that the sum of the volume of the amount of adhesive and the volume of the semiconductor chip corresponds approximately to the volume of a free region of the photo-structured insulation layer. In practice, a slight excess is used.
  • the adhesive fills the trenches and ensures that the • top of the electronic component is substantially planar and continuous. An additional process step for closing the trenches can thus be saved inexpensively.
  • the methods described above for producing electronic components can also be used to produce a multichip module with an arrangement of first and second semiconductor chips described above.
  • the first and second semiconductor chips are first ground thin microns to a level of less than 150, then such a 'is applied to free areas of the photo-structured insulating layer that those of its edges opposite to each other, each having an at least partially matching arrangement of contact areas.
  • the line paths are formed in such a way that in each case opposite contact surfaces are connected to one another and also the external contacts are connected to the contact surfaces of the semiconductor chip or chips and that the carrier is thus grounded.
  • any rewiring layers can be applied and the wiring effort can be significantly reduced. It is often possible to connect the entire electronic component with just one wiring layer. The provision of a second wiring layer can be dispensed with in a cost-saving manner.
  • FIG. 1 shows a plan view of a semiconductor chip arrangement with semiconductor chips arranged in rows and in columns
  • FIG. 2 shows a schematic illustration of a top view of a first semiconductor chip wiring and of a second semiconductor chip wiring of an enlarged 2x2 section of the semiconductor chip arrangement shown in FIG. 1,
  • FIG. 3 shows a wire-bonded first multichip module with the semiconductor chip arrangement shown in FIG. 1 in cross section
  • FIG. 4 shows a cross section of a second multichip module produced using flip-chip technology with the semiconductor chip arrangement shown in FIG. 1,
  • FIG. 5 shows a third multichip module with the semiconductor chip arrangement shown in FIG. 1 in cross section
  • FIG. 6 shows a fourth multichip module with the semiconductor chip arrangement shown in FIG. 1 in cross section
  • FIG. 7 shows a fifth multichip module with the semiconductor chip arrangement shown in FIG. 1 in cross section
  • Figure 8 shows an electronic component in cross section.
  • FIG. 1 shows a plan view of a semiconductor chip arrangement 1 with semiconductor chips arranged in rows and in columns. The active top sides of the semiconductor chips are considered in each case.
  • the exemplary semiconductor chip arrangement 1 is constructed as a square 4x4 matrix.
  • semiconductor chip arrangements according to the invention can also be in the form of 2x1, 2x2 or 3x3 matrices or in any desired size.
  • the semiconductor chip arrangement 1 comprises 16 semiconductor chips, which are divided into eight first semiconductor chips 2 and eight second half divide the conductor chips 3.
  • the first semiconductor chips 2 and the second semiconductor chips 3 are alternately arranged side by side and one behind the other, which results in a checkerboard-like pattern.
  • First semiconductor chips 2 each form the left front and the right rear corner of the semiconductor chip arrangement 1.
  • Second semiconductor chips 3 each form the left rear and the right front corner of the semiconductor chip arrangement 1.
  • the circular, oval, rectangular and diamond-shaped symbols illustrate the geometry and the reflection of the first semiconductor chips 2 and the second semiconductor chips 3.
  • the semiconductor chip corners A, B, C and D of the semiconductor chips 2, 3 are also shown for this purpose.
  • the semiconductor chips 2, 3 arranged in lines 2 and 4 of the semiconductor chip arrangement 1 correspond completely to the semiconductor chips 2, 3 arranged in lines 1 and 3, the semiconductor chips 2, 3 arranged in lines 2 and 4 each being 180 ° in the xy Level rotated are arranged.
  • the semiconductor chip arrangement 1 ensures that the mutually opposite edges of the first semiconductor chips 2 and the second semiconductor chips 3 match each other. These respectively matching edges of the semiconductor chips 2, 3 are connected by means of buses 4 represented by arrows in FIG. 1.
  • the corresponding arrangement of contact surfaces on opposite edges ensures that the wiring of the buses 4 can be of very short dimensions and that crossings, vias and long routings of wiring are avoided.
  • the semiconductor chip arrangement 1 it is also noticeable that its outer edges are each formed by the edges A-B and B-C of the semiconductor chips 2, 3.
  • the edges AD and CD each form internal edges of the semiconductor chip arrangement 1. Accordingly, when designing the semiconductor chips 2, 3, care must be taken that contact surfaces for the external communication are best arranged on the edges AB and BC and that contact surfaces for the internal Communication of the semiconductor chips 2, 3 are mainly located on the edges AD and CD.
  • the contact areas for the external and for the internal communication can also be located on other edges, as can be seen, for example, from a consideration of the 2 ⁇ 1 matrix shown in FIG. 1, in which the edges AB, BC and CD are on the outside and only the edges AD are inside.
  • a cut line QQ runs through the first row of semiconductor chips 2, 3 of semiconductor chip arrangement 1.
  • the following Figures 3-7 include cross-sectional drawings in which the semiconductor chip arrangement 1 is shown along this section line QQ viewed from behind.
  • FIG. 2 shows a schematic illustration of a top view of a first semiconductor chip wiring 11 and of a second semiconductor chip wiring 12 of an enlarged 2x2 section of the semiconductor chip arrangement 1. This 2x2 section is shown by the middle four semiconductor chips 2, 3 in the upper two rows of the semiconductor chip arrangement 1 formed.
  • the first semiconductor chip wiring 11 can be used, for example, in the case of bonded semiconductor chips or in the case of components based on leadframe or leadframe, in particular in quad fiat packages.
  • the first semiconductor chip wiring 11 shows contact areas A1-A16 which are arranged uniformly on the edges of the active upper sides of the semiconductor chips 2, 3, five contact areas A1-A5, A5-A9, A9-A13 and A13-A1 being located on each edge.
  • the contact areas A1-A16 are arranged clockwise in the first semiconductor chips 2 and counterclockwise in the second semiconductor chips 3 on the edges of the active upper sides.
  • the contact surfaces A5-A13 arranged on opposite edges are connected to each other by first wirings 110.
  • the second semiconductor chip wiring 12 is suitable, for example, for implementation using semiconductor chips in flip-chip technology and using ball grid arrays.
  • the second semiconductor chip wiring 12 represents a conversion of the wiring according to the invention into flip-chip technology.
  • wiring according to the invention as a ball grid array differs only slightly from the second semiconductor chip wiring 12 described in FIG.
  • the second semiconductor chip wiring 12 shows contact areas A1-A5, B1-B5, C1-C5, D1-D5 and E1-E5, which in FIG. 2 are distributed in a 5 ⁇ 5 matrix over the active top sides of the semiconductor chips 2, 3.
  • the contact areas A1-A5, B1-B5, C1-C5, D1-D5 and E1-E5 of the second semiconductor chips 3 are mirror-symmetrical to the contact areas A1-A5, B1-B5, C1-C5, Dl-D5 and E1-E5 the first semiconductor chips 2 are arranged.
  • FIG. 3 shows a first multichip module 5 produced by means of bonding technology with the semiconductor chip arrangement 1 in cross section Q-Q.
  • the arrangement of the contact areas A1-A16 of the first multichip module 5 corresponds to the representation of the first semiconductor chip wiring 11 in FIG. 2.
  • FIG. 3 also shows an axis cross, with the aid of which the use of the terms “next to one another”, “behind one another”, “on top of each other” and “above one another” is standardized.
  • the term “next to each other” is used in relation to the x-axis, the term “in succession” in relation to the y-axis and the terms “on top of each other” and “one above the other” are used in relation to the z-axis.
  • the appropriate use of these terms refers to the following Figures 3-7.
  • the first multichip module 5 comprises a circuit substrate 51 which, for example, has laminate, in particular FR / BT IV.
  • the passive rear sides of the semiconductor chips 2, 3 are applied, in particular glued, to the upper side of this circuit substrate 51.
  • the representation of the adhesive layer between the passive rear sides of the semiconductor chips 2, 3, which are often placed on ground, and the representation of the upper side of the circuit substrate 51 are omitted in FIG. 3.
  • the circuit substrate 51 has first leadthroughs 53 made of metal on the edge, which extend downward through the circuit substrate 51 from contact connection areas 52 on the upper side of the circuit substrate 51.
  • the first bushings 53 are followed by bump-shaped first external contacts 54 on the underside of the circuit substrate 51, by means of which the first multichip module 5 can be connected to other electronic components.
  • the contact areas AI and A5 on the active top sides of the semiconductor chips 2, 3 can be seen particularly well in the illustration in FIG.
  • the wiring of the contact areas with one another and the contact areas with the contact connection areas 52 on the circuit substrate 51 are realized in the first multichip module 5 by means of bonding technology.
  • Very short first bond connections 55 are provided, each of which connects the contact areas of adjacent first semiconductor chips 2 and second semiconductor chips 3 to one another.
  • the contact surfaces AI and A5 are shown as an example.
  • second bond connections 56 are provided, which contact areas located on the outer edges of the semiconductor chip arrangement 1 with the contact connection areas.
  • Chen 52 connect the circuit substrate 51 and thus allow external contacting of all semiconductor chips 2, 3 of the first multichip module 5.
  • FIG. 3 shows the second bond connections 56 from the contact areas AI to the contact connection areas 52.
  • the first multichip module 5 is provided with a first plastic encapsulation 57 such that the semiconductor chips 2, 3, the bond connections 55, 56 and the contact connection areas 52 are completely enveloped by the plastic compound.
  • FIG. 4 shows a second multichip module 6 produced using flip-chip technology with the semiconductor chip arrangement 1 in cross section Q-Q.
  • the arrangement of the contact areas A1-E5 of the second multichip module 6 corresponds to the representation of the second semiconductor chip wiring 12 in FIG. 2.
  • the second multichip module 6 comprises a main circuit board 61, which in particular has plastic. On the edge side on the main board 61 extending conducting, in particular metallic second passages 64 through the main circuit board 61. On this second guides 64 close 'to the top of the motherboard 61 hump-shaped second external contacts 65 on.
  • metal wirings 62 are arranged on the main board 61 in a rewiring level.
  • the metal wirings 62 are connected to the second bushings 64 and are used for contacting the semiconductor chips 2, 3 with one another and with the outside.
  • the metal wiring 62 does not have to lie in a rewiring plane as shown in FIG. 4. It can a plurality of rewiring levels arranged one above the other can also be provided.
  • the semiconductor chips 2, 3 are arranged below the main board 61 and are aligned with their active upper sides towards the underside of the main board 61.
  • the contact surfaces 21, 31 are connected to the metal wirings 62 by means of flipchip contacts 63.
  • the semiconductor chips 2 and 3, the metal wiring 62 and the flipchip contacts 63 are optionally completely encased in a second plastic encapsulation 66.
  • the metal wirings 62 are subdivided into metal wirings 62 which connect opposing contact areas to one another and metal wirings 62 which conduct the other contact areas located on the semiconductor chip arrangement 1 to the second bushings 64.
  • FIG. 4 shows those metal wirings 62 which connect the opposing contact areas AI and A5 to one another and which connect the contact areas AI to the second bushings 64.
  • the metal wirings 62 are very short and can be easily implemented, especially since the contact surfaces of the semiconductor chips 2, 3 to be connected are opposite each other.
  • FIG. 5 shows a third multichip module 7 with the semiconductor chip arrangement 1 in cross section QQ.
  • the arrangement of the contact areas AI-AI6 of the third multichip module 7 corresponds to the representation of the first semiconductor chip wiring 11 in FIG. 2.
  • the third multichip module 7, also referred to as a universal package, is electrically contacted by means of exactly one direct rewiring layer. For other multichip modules (not shown here), rewiring by means of a plurality of rewiring layers can also be provided.
  • the semiconductor chips 2, 3 are shown in FIG. 5 with their active upper sides oriented upwards.
  • the passive rear sides and the side surfaces, but not the active top sides of the semiconductor chips 2, 3 are enclosed by a plastic compound, in particular by an epoxy resin, which forms a plastic carrier 71 for the semiconductor chips 2, 3.
  • the plastic carrier 71 is designed such that its top side lies between and next to the semiconductor chips 2, 3 at the same level as the active top sides of the semiconductor chips 2, 3 or slightly higher than the active top sides of the semiconductor chips 2, 3.
  • a structured polyimide layer 72 is applied to the upper side of the semiconductor chips 2, 3, which leaves only the contact areas 21, 31 free on the active upper sides of the semiconductor chips 2, 3.
  • Functional multichip modules can also be implemented without such a structured polyimide layer 72.
  • the polyimide layer 72 shown in Figure 5 can also be photo structured such that it extends only over the active top sides of the semiconductor chips 2, 3 and the 'leaves free between or adjacent to the semiconductor chips 2, 3 lying areas of the plastic carrier 71st
  • First redistributions 73 and second redistributions 74 of the redistribution layer are applied to the structured polyimide layer 72.
  • the first rewirings 73 connect the individual semiconductor chips 2, 3 to one another.
  • the second rewirings 74 connect the contact areas located at the edge of the semiconductor chip arrangement 1 to third external contacts 75, which protrude upwards and rest on the second rewirings 74.
  • the first and second rewirings 73, 74 are essentially planar and can be constructed in multiple layers.
  • the semiconductor chip arrangement 1 according to the invention and the resulting very short and easily realizable first and second rewirings 73, 74 make it possible to implement all rewirings 73, 74 of the third multichip module 7 in a single rewiring layer. This results in a faster and more cost-effective way of producing such multichip modules.
  • FIG. 6 shows a fourth multichip module 7b with the semiconductor chip arrangement 1 in cross section Q-Q.
  • the arrangement of the contact areas AI-AI6 of the fourth multichip module 7b corresponds to the representation of the first semiconductor chip wiring 11 in FIG. 2.
  • the fourth multichip module 7b corresponds in many points to the third multichip module 7 from FIG. 5, the semiconductor chips 2, 3 not being enclosed by a plastic carrier 71, but with their passive rear sides on a temperature and mechanically stable and flat carrier, in the exemplary embodiment on a carrier plate 76 made of metal or Silicon are applied or glued.
  • the semiconductor chips 2, 3 usually have a height of less than 150 ⁇ m.
  • a photoimide layer 77 is applied to the carrier plate 76, which encloses the sides of the semiconductor chips 2, 3 and on which the structured polyimide layer 72 rests.
  • This photoimide layer 77 has a photo-structurable insulator, for example CARDU.
  • CARDU photo-structurable insulator
  • two insulating layers are arranged one above the other, namely the structured polyimide layer 72 and the photoimide layer 77.
  • the height of these two layers 72, 77 should overall be at least as large as the height of the semiconductor chips 2, 3 and those arranged below, not shown in FIG. 6 Adhesive layer.
  • FIG. 7 shows a fifth multichip module 8 with the semiconductor chip arrangement 1 in cross section Q-Q.
  • the arrangement of the contact areas AI-AI6 of the fifth multichip module 8 corresponds to the representation of the first semiconductor chip wiring 11 in FIG. 2.
  • the fifth multichip module 8 is constructed on a bottom-mounted first circuit carrier 81, which in particular has metal.
  • the semiconductor chips 2, 3 are attached with their passive rear side to the top of the first circuit carrier 81. This attachment is implemented in FIG. 5 by means of a structured first adhesive layer 82.
  • a first photostructured insulation layer 83 is shown in FIG. 5 in such a way that it is flush with completes the side faces of the semiconductor chips 2, 3.
  • the first photo-structured insulation layer 83 which is idealized in FIG. 7, is usually designed in such a way that it does not extend completely to the side surfaces of the semiconductor chips 2, 3.
  • rubber-elastic transitions 84 made of an elastomer are provided on the edge sides of the semiconductor chips 2, 3.
  • Third and fourth metal conduction paths 85, 86 run on the areas of the first photo-structured insulation layer 83 not covered by the transitions 84 and on the transitions 84 themselves.
  • the third line paths 85 connect mutually opposite contact areas of the first and second semiconductor chips 2, 3.
  • the fourth line paths 86 connect the contact areas located on the edges of the semiconductor chip arrangement 1 to fourth external contacts 87, which are placed on external contact areas 88 arranged in edge regions of the fourth multichip module 8. These fourth external contacts 87 protrude significantly above the active top sides of the semiconductor chips 2, 3.
  • FIG. 8 shows an electronic component 9 in cross section.
  • the electronic component 9 comprises a second circuit carrier 91 made of an iron-chromium-nickel alloy, on the surface of which a first thin-ground semiconductor chip 92 and a second thin-ground semiconductor chip 93 with their passive rear sides by means of second adhesive layers 95 are brought.
  • the thinly ground semiconductor chips 92, 93 have a height of 120 ⁇ m and the second adhesive layers 95 have a layer thickness of 20 ⁇ m.
  • contact areas 94 and areas of a photo-passivation not shown in FIG. 8 are provided, unless passivation is carried out over the entire surface of the electronic component 9.
  • a second photostructured insulation layer 96 is arranged between and next to the thinly ground semiconductor chips 92, 93, each of which is flush with the second circuit carrier 91 on the left and on the right side.
  • Cardo has the second photo-structured insulation layer 96 and has a layer thickness of 140 ⁇ m in the present exemplary embodiment.
  • Trenches 97 are formed between the edge sides of the thinly ground semiconductor chips 92, 93 and the edge regions of the second photostructured insulation layer 96 which are arranged next to each other and each have a width of 50 ⁇ m in the present exemplary embodiment and extend down to the surface of the second circuit carrier 91.
  • the trenches 97 are completely filled by means of a filling material 98.
  • the surfaces of the second photo-structured insulation layer 96 and the filling material 98 of the trenches 97 lie on one level with the active upper sides of the thin-ground semiconductor chips 92, 93.
  • the filling material 98 filling the trenches 97 can also have slight bulges upwards.
  • the filling material 98 is formed from a photoimide.
  • the filling material 98 of the trenches 97 can also be the insulating adhesive of the second adhesive layers 95, which fills the trenches 97 when the thin-ground semiconductor chips 92, 93 are inserted.
  • Fifth conductive paths 99 run on the surfaces of the filler material 98 of the trenches 97 and on the surfaces of the second photo-structured insulation layer 96, which connect the contact surfaces 94 of the thin-ground semiconductor chips 92.93 both to one another and to external contacts 101, which also open in edge regions of the top of the second photostructured insulation layer 96 external contact surfaces 100 are applied.
  • the fifth line paths 99 can also run over the active top sides of the thin-ground semiconductor chips 92, 93, especially since these are provided with the photoimide passivation.
  • the second circuit carrier 91 is first provided. Then the insulation layer 96 is applied to the second circuit carrier 91 and photo-structured in such a way that free areas for receiving the thin-ground semiconductor chips 92, 93 as well as sawing lines (not shown in FIG. 8) between the electronic component 9 and adjacent electronic components (also not shown in FIG. 8) arise.
  • the semiconductor chips 92, 93 are first thinly ground. This method is known to the person skilled in the art and is required here not to be explained further.
  • the thinly ground semiconductor chips 92, 93 are then inserted into the free areas of the second photo-structured insulation layer 96 and at the same time connected to the second circuit carrier 91 by means of the second adhesive layers 95.
  • These adhesive layers 95 can also be made conductive.
  • a further insulation layer which is not explicitly shown in FIG. 8, is then applied to the electronic component 9 and photostructured in such a way that only the contacts 94 and the sawing road remain free and that the trenches 97 are filled.
  • the adhesive does not only have second adhesive layers 95 with a layer thickness of 20 ⁇ m forms, which attach the thinly ground semiconductor chips 92, 93 with their passive back on the second circuit carrier 91, but that this adhesive also fills the trenches 97 completely capillary.
  • the fifth line paths 99 are applied, which can also ground the circuit carrier 91 via the saw road.
  • external contacts 101 are placed on the external contact surfaces 100 in order to be able to connect the electronic component 9 to a higher-level printed circuit board, for example.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un module multipuces comportant au moins une première puce de semiconducteur (2) et au moins une deuxième puce de semiconducteur (3). Ces puces de semiconducteur (2, 3) sont placées de manière coplanaire sur ou dans un substrat (51) et présentent des composants adaptés les uns aux autres ainsi que des surfaces de contact (A1, A5) situées sur leurs faces supérieures actives. Au moins une deuxième puce de semiconducteur (3) présente un agencement de surfaces de contact (A1, A5) à symétrie spéculaire par rapport à une première puce de semiconducteur (2). Au mois une première puce de semiconducteur (2) et au moins une deuxième puce de semiconducteur (3) sont juxtaposées et/ou placées l'une derrière l'autre de sorte que leurs bords qui présentent un agencement correspondant de surfaces de contact (A1, A5) sont situés les uns en face des autres. Des câblages (55, 56) s'étendent respectivement entre des surfaces de contact (A1, A5) qui se font face et entre des surfaces de contact (A1), situées sur les bords extérieurs des puces de semiconducteur (2, 3), et des contacts extérieurs (54).
EP04726437A 2003-04-11 2004-04-08 Module multipuces comportant plusieurs puces de semiconducteur et carte de circuits comportant plusieurs composants Withdrawn EP1614158A2 (fr)

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DE2003117018 DE10317018A1 (de) 2003-04-11 2003-04-11 Multichipmodul mit mehreren Halbleiterchips sowie Leiterplatte mit mehreren Komponenten
PCT/DE2004/000750 WO2004093190A2 (fr) 2003-04-11 2004-04-08 Module multipuces comportant plusieurs puces de semiconducteur et carte de circuits comportant plusieurs composants

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US7317251B2 (en) 2008-01-08
US20060060954A1 (en) 2006-03-23
DE10317018A1 (de) 2004-11-18
WO2004093190A2 (fr) 2004-10-28

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