EP1585174A1 - Circuit device and manufacturing method of the same - Google Patents

Circuit device and manufacturing method of the same Download PDF

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Publication number
EP1585174A1
EP1585174A1 EP05004672A EP05004672A EP1585174A1 EP 1585174 A1 EP1585174 A1 EP 1585174A1 EP 05004672 A EP05004672 A EP 05004672A EP 05004672 A EP05004672 A EP 05004672A EP 1585174 A1 EP1585174 A1 EP 1585174A1
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EP
European Patent Office
Prior art keywords
film
wiring pattern
circuit device
under bump
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05004672A
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German (de)
English (en)
French (fr)
Inventor
Takaaki Domon
Toshiyuki Nagatsuka
Tsutomu Yasui
Ryoichi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
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Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Publication of EP1585174A1 publication Critical patent/EP1585174A1/en
Withdrawn legal-status Critical Current

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    • H01L2924/3011—Impedance

Definitions

  • the invention relates to a circuit device and a manufacturing method of the same, used for transmitting and receiving wireless telecommunications equipments such as a wireless LAN, ETC, and cellular phones, etc., and especially to a semiconductor integrated circuit device and a manufacturing method of the same which contains a high frequency thin film coil or the like.
  • voids may be formed because of diffusion phenomenon if the metallic bump of Au (gold) etc. directly formed on the Al film used as the wiring patterns might invite decrease in joint strength.
  • characteristic of the circuit device might be influenced by the decrease in joint strength and the problem is caused in reliability.
  • an under bump metal is formed with designated thickness on the surface of the electrode pad pattern of the Al film by an under bump metal processing (UBM processing).
  • UBM processing under bump metal processing
  • a Ni (nickel) film and an Au film are formed in order as lamination layers on the electrode pad pattern of the Al film or further formed a Ti (titanium) film between the Al film and the Ni film.
  • FIG. 4 shows a prior art of a structure of a circuit device containing a high frequency thin film coil.
  • a wiring pattern 2 of an Al (aluminum) film and an electrode pad pattern 4 are formed on a bottom side surface of a Si-IC substrate 1 (the bottom is upward shown in the figure) in a wafer process.
  • an insulation protection of a passivation film 3 is formed on the wiring pattern 2, some part of the electrode pad pattern 4 of the Al film corresponding to a putting part of a metallic bump 12 should be exposed for instance by photo lithography.
  • the bump 12 is provided through which an electrical connection is achieved with another substrate by the flip chip bonding, or other bonding methods.
  • the UBM consisting of lamination layers are formed one by one on the electrode pad pattern 4 of the Al film.
  • the lamination layers include for instance a Ni film 6 and an Au film 7 as the uppermost layer.
  • the wiring pattern 2 to compose a coil 5 was put under an insulation protection by the passivation film 3, and was irrelevant to the UBM processing.
  • the above-mentioned circuit device which contains a high frequency thin film coil is used for instance as a device for the wireless telecommunications equipment, in order to minimize a loss in a transmission side and to improve filtering effect in a reception side, the improvement of Q characteristic of the coil becomes a main subject.
  • a thickness of an Al deposited film formed in a wafer process is usually suppressed to a minimum thickness of necessary, that is about 0.5 ⁇ m from a viewpoint of balancing electric performance with manufacturing cost. Therefore, there was a limit so as to form the coil of high Q and low direct current resistance in an adjacent formation on an IC substrate in case of considering the coil formed with the Al film of the said thickness. For instance, if the value of inductance is 3 nH, the value of Q lowers to become about 5-6, such value of Q will not satisfy requirements for a composition element of a filter or the like.
  • the coil shapes When a high density device formation is requested to the IC substrate, the coil shapes inevitably becoming small and the accumulation space of the magnetic energy of the coil is small, and it becomes difficult more and more to obtain a high Q characteristic, as the wiring pattern of the Al film forming the coil conductor becomes thin.
  • the value of Q is inverse proportion to an energy loss, as a result, though the Q characteristic is improved when the loss is a little, it is difficult to keep the high Q characteristic by the above-mentioned reason in order to realize the miniaturizing electronic parts.
  • Japanese Patent Application Laid-Open No.2002-57292, No.9-330817, and No.8-172161 are examples of showing a device containing a coil (inductive element) in a semiconductor substrate.
  • a plurality of chip formation areas are arranged on a semiconductor wafer substrate, and a circuit element formation area is arranged in each chip formation area, and a coil (inductive element) is formed with a conductor layer on the circuit element formation area from which the conductor layer is insulated by a insulation layer so as to miniaturize the coil.
  • a coil inductive element
  • an electrolytic plating conductor layer is formed after a spiral coil conductor of an electroless plating conductor layer is formed on a silicon substrate, so as to increase the total thickness of the coil conductor and to improve Q value.
  • a formation of a contacting part and the formation of the coil are practiced separately.
  • a structure which has a resin insulation film formed on a half insulation semiconductor substrate, and a wiring metal layer for an inductance element on the resin insulation film.
  • a low ratio permittivity material is used for the resin insulation film and a thickness of which is increased, consequently a capacity between the lines of the wiring metal is decreased so as to improve Q value.
  • a first object of the invention is to provide a circuit device that has connection bumps on a surface of a substrate and laminated layer formation of the same metallic film as UBM in the UBM processing, so that the laminated layer formation provided on at least a part of a wiring pattern on the surface (the pattern is piled up) can decrease a electric resistance of the wiring pattern without inviting an increase in production steps and can provide a low price device.
  • a second object of the invention is to provide a circuit device that has the laminated layer formation of the same metallic film as the UBM provided on at least a part of a wiring pattern, so as to enable to improve a Q value in case of a coil formed in the wiring pattern part.
  • a third object of the invention is to provide a manufacturing method of a circuit device that has a step to form at least one laminated metallic film on an electrode pad pattern and a part of or all of a wiring pattern at the same time in the UBM formation process so as to decrease a electric resistance of the wiring pattern without inviting an increase in production steps, in its turn enabling to form a high Q coil.
  • the invention provides a circuit device comprising: at least one under bump metal formed on a surface of a substrate; a connection bump provided on the uppermost layer of the under bump metal; at least one laminated metallic film formed on part of or all of wiring pattern formed on the surface of the substrate, the laminated metallic film consisting of the same material and also the same thickness as the under bump metal.
  • the invention further provides a circuit device wherein a coil includes at least a part of the wiring pattern.
  • the invention further provides a circuit device wherein a plurality of under bump metals are provided and an upper layer of the under bump metals is an Au film, and a lower layer of the under bump metal is a Ni, Pt, Pd or W film.
  • the invention further provides a circuit device wherein the wiring pattern is an Al film, and the lowest layer of a Ti, Cu, Cr, CrNi or Ge film is formed between the wiring pattern and the lower layer of the under bump metals of the Ni, Pt, Pd or W film.
  • the invention provides a manufacturing method of a circuit device which comprises an under bump metal formation process where at least one under bump metal is formed on a surface of a substrate, and a bump formation process where a connection bump is formed on the under bump metal, the method comprising the steps of: forming a passivation film on the surface of the substrate except at least a part of a wiring pattern and an electrode pad pattern on the surface so as to expose said part of the wiring pattern and the electrode pad pattern; in the under bump metal formation process, forming at least one laminated metallic film on the exposure part of the wiring pattern and the electrode pad pattern.
  • the invention further provides a manufacturing method of a circuit device wherein the passivation film is formed after exposing said part of the wiring pattern and the electrode pad pattern by an exposure development processing method.
  • the invention further provides a manufacturing method of a circuit device wherein a Ni, Pt, Pd or W film is formed as a lower layer, and then an Au film is formed as an upper layer laminated on the lower layer in the under bump metal formation process.
  • the invention further provides a manufacturing method of a circuit device, wherein the electrode pad pattern and the wiring pattern are Al films, and in the under bump metal formation process, a Ti, Cu, Cr, CrNi, or Ge film as the lowest layer, the Ni, Pt, Pd, or W film as the lower layer and the Au film as the upper layer are formed in order as lamination layers.
  • FIG. 1 is a cross-sectional view showing a first embodiment of a circuit device and manufacturing method of the same in accordance with the invention.
  • FIG. 2 is a cross-sectional view showing a second embodiment of a circuit device and manufacturing method of the same in accordance with the invention.
  • FIG. 3 is a graph that shows relations between an inductance value and a Q value of high frequency coils of the sample A according to a prior art, the sample B according to the first embodiment and the sample C according to the second embodiment.
  • FIG. 4 is a cross-sectional view showing a prior art of a circuit device including a high frequency thin film coil.
  • FIG. 1 is a cross-sectional view of a first embodiment to explain a structure and a production process of a circuit device that contains a high frequency thin film coil.
  • the same numerals are fixed to common members in the prior art (refer to FIG. 4) and FIG. 1, and the explanations thereof are omitted.
  • the different point of the device of the first embodiment from the prior art (refer to FIG. 4) is that a passivation film 3 is formed on a surface of a substrate 1 on the condition that a part of (or all of) the wiring pattern 2 forming a high frequency coil 5 and an electrode pad pattern 4 of an Al film as a putting part of a metallic connection bump 12 are exposed by an exposure development processing method for instance by photo lithography or the like.
  • the bump 12 is provided through which an electrical connection is achieved with other substrate by the flip chip bonding, or other bonding methods.
  • both of one film forming process with a UBM 6 (a lower layer: barrier layer) of a Ni film and a UBM 7 (an upper layer) of a Au film on the electrode pad pattern 4 of the Al film, and another process with a metallic film 8 (a lower layer: barrier layer) of Ni and a metallic film 9 (an upper layer) of Au on the part of wiring pattern 2 of the Al film composing the coil 5 are executed in the lump at the same time in the same production process (a dry film forming method of sputter, etc. or a wet film forming method of plating, etc.).
  • the metallic connection bump 12 is formed and bonded on the UBM 7 of the Au film through Au or solder (for instance, a sphere or a rod shape Au as the bump is connected by ball bonder machine etc.).
  • the electrode pad pattern 4 of the Al film has been formed in an active area (parts areas such as diodes and transistors other than wiring) of the Si-IC substrate 1.
  • the film thickness of the UBM 6 of the Ni film and the Ni film 8 is about 0.1 ⁇ m-7 ⁇ m, and forming with plating (electrolytic or electroless) is more desirable.
  • the film thickness of the UBM 7 of the Au film and the Au film 9 is about 0.03 ⁇ m-1 ⁇ m, and it is possible to use each method of plating (electrolytic or electroless) and sputtering.
  • FIG. 2 is a cross-sectional view of a second embodiment to explain a structure and a production process of a circuit device.
  • the same numerals are fixed to common members in the above-mentioned first embodiment, and the explanations thereof are omitted.
  • the different point of the device of the second embodiment from the first embodiment is forming a metallic film 11 (the lowest layer: sticking layer) of Ti on the part of the wiring pattern 2 of the Al film composing coil 5 in the UBM formation process, at the same time as forming an UBM 10 (the sticking layer) of the Ti film which becomes the lowest layer on the electrode pad pattern 4 of the Al film.
  • the UBM 6 of Ni film and the metallic film 8 (the lower layer: barrier layer) of Ni, and the UBM 7 of the Au film and the metallic film 9 (the upper layer) of Au are formed at the same time in the same production process (the dry film forming method of sputter, etc. or the wet film forming method of plating, etc.).
  • the film thickness of the UBM 10 of the Ti film and the metallic film 11 of Ti is about 0.03 ⁇ m-0.3 ⁇ m, and it is desirable to form them with sputtering.
  • the film thickness of the UBM 6 of the Ni film and the metallic film 8 of Ni is about 0.1 ⁇ m-1 ⁇ m, and although the film thickness of the UBM 7 of Au film and the metallic film 9 of Au is allowed similar to the first embodiment, it may decrease the film thickness of the UBM 6 of Ni and the metallic film 8 only by the film thickness of the UBM 10 of the Ti film and the Ti film 11.
  • the IC substrate bottom including the coil pattern formed in the above-mentioned production process is sealed for insulation in the resin-sealed process.
  • the insulation sealing is done by under fill of the resin system so as to satisfy electric insulation and moisture resisting sealing of the coil after the Si-IC substrate is connected to a surface of other substrate through the bumps by flip chip bonding.
  • FIG. 3 shows relations between an inductance value (nH) and a Q value in the coil part, in case of the sample A according to a prior art of FIG. 4 where no laminated layer formation of the metallic films is provided in the wiring pattern part composing the high frequency coil, the sample B (film thickness Ni : 3 ⁇ m/Au : 0.03 ⁇ m) according to the first embodiment and the sample C (film thickness Ti : 0.03 ⁇ m/Ni : 0.3 ⁇ m/Au : 0.3 ⁇ m) according to the second embodiment.
  • the Q value is calculated by measuring S parameter with a network analyzer.
  • the Q value increases most the case of the sample C that includes metallic film 11 of Ti between the part of wiring pattern 2 of the Al film and the metallic film 8 of Ni so as to compose the coil 5.
  • the Q value of the sample B without the metallic film 11 of Ti is inferior to that of the sample C, though the sample B is the higher Q value sample than the sample A. It will be considered that the Q value has decreased due to a magnetic loss of Ni, and if possible it is desirable to form the metallic film 11 of Ti and to put the metallic film 8 of Ni thinly (the Q value can be changed by change of the Ni film thickness in the UBM formation process.).
  • the passivation film 3 is formed on the bottom surface of the Si-IC substrate 1 except both the electrode pad pattern 4 and the part of the wiring pattern 2 consisting of coil 5 on condition that the electrode pad pattern 4 and said part of the wiring pattern are exposed, and in the UBM formation process provided on the electrode pad pattern 4 so as to stabilize electrically and mechanically the connection of the bump 12 to the electrode pad pattern 4, so that, it can be formed both of the UBM on the electrode pad pattern 4 and the metallic film on the said wiring pattern part in the same production process at the same time. Therefore, it is possible to realize the circuit device including the coil improved Q value by the shortest process.
  • both film forming methods are acceptable to the Au layer without limiting.
  • the Ni film of the lower layer is formed of the wet film forming method, and though the Au film of the upper layer is formed by the dry film formation, the dry and the wet film forming process can be acceptable together.
  • the use such as Pt (platinum), Pd (palladium) or W (tungsten) film, etc. is permitted instead of the Ni film of the lower layer in the first and second embodiments, and also the use such as Cu (copper), Cr (chrome), CrNi, and Ge (germanium) film, etc. is permitted instead of the Ti film of the lowest layer in the second embodiment. Therefore, a Ti, Cu, Cr, CrNi, or Ge film as the lowest layer, the Ni, Pt, Pd, or W film as the lower layer and the Au film as the upper layer can be formed in order as lamination layers.
  • the laminated metallic film consisting of the same material and also the same thickness as the UBM is formed on part of or all of wiring pattern formed on the surface of the substrate, so that it is possible to decrease the electric resistance by enlarging the sectional area of the wiring pattern by the lamination. Therefore, when the coil is composed partially of the wiring pattern for instance, a high Q value can be achieved.
  • a passivation film is formed on the surface of the substrate except at least a part of the wiring pattern and the electrode pad pattern on the surface so as to expose said part of the wiring pattern and the electrode pad pattern, and in the under bump metal formation process, forming at least one laminated metallic film on the exposure part of the wiring pattern and the electrode pad pattern, so that it is possible to execute at the same time in the UBM formation process so as to increase the film thickness of the wiring pattern (to increase the sectional area) without increase of the production steps, moreover it is possible to form a high Q value coil, etc. on the substrate because of using the wiring pattern part of the low resistance.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP05004672A 2004-03-25 2005-03-03 Circuit device and manufacturing method of the same Withdrawn EP1585174A1 (en)

Applications Claiming Priority (2)

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JP2004088145 2004-03-25
JP2004088145A JP3851320B2 (ja) 2004-03-25 2004-03-25 回路装置及びその製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2100328A1 (en) * 2006-12-11 2009-09-16 FlipChip International L.L.C. Solder bump/under bump metallurgy structure for high temperature applications

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI255568B (en) * 2005-09-15 2006-05-21 Chipmos Technologies Inc Light emitting diode and fabricating method thereof
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
WO2008075537A1 (ja) * 2006-12-18 2008-06-26 Panasonic Corporation 電極構造体およびバンプ形成方法
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
US20090057909A1 (en) * 2007-06-20 2009-03-05 Flipchip International, Llc Under bump metallization structure having a seed layer for electroless nickel deposition
DE102007057689A1 (de) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Chipgebiet, das für eine aluminiumfreie Lothöckerverbindung gestaltet ist, und eine Teststruktur, die für eine aluminiumfreie Drahtverbindung gestaltet ist
IT1400060B1 (it) * 2010-05-07 2013-05-17 Galileo Vacuum Systems S P A "metodo e impianto per produzione di antenne per circuiti rfid"
JP2012009510A (ja) * 2010-06-22 2012-01-12 Sumitomo Bakelite Co Ltd 金属微細パターン付き基材、プリント配線板、及び半導体装置、並びに、金属微細パターン付き基材及びプリント配線板の製造方法
TWI467719B (zh) * 2012-05-07 2015-01-01 Novatek Microelectronics Corp 薄膜覆晶裝置
US20130292819A1 (en) * 2012-05-07 2013-11-07 Novatek Microelectronics Corp. Chip-on-film device
US8952489B2 (en) * 2012-10-09 2015-02-10 Infineon Technologies Ag Semiconductor package and method for fabricating the same
KR102347394B1 (ko) * 2015-02-12 2022-01-06 삼성전자주식회사 회로 기판을 포함하는 전자 장치
US10211663B2 (en) * 2015-08-21 2019-02-19 Apple Inc. 3D shaped inductive charging coil and method of making the same
JP2019004186A (ja) * 2018-10-02 2019-01-10 株式会社ニコン 半導体装置及びその製造方法、撮像装置、並びに電子カメラ
TWI800153B (zh) * 2020-12-24 2023-04-21 南韓商東友精細化工有限公司 電路板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08172161A (ja) * 1994-12-16 1996-07-02 Hitachi Ltd インダクタ素子とその製法およびそれを用いたモノリシックマイクロ波集積回路素子
JPH09330817A (ja) * 1996-06-12 1997-12-22 Fuji Electric Co Ltd 面状コイル装置およびその製造方法
JP2002057292A (ja) * 2000-08-11 2002-02-22 Iep Technologies:Kk 半導体装置および半導体装置の製造方法
US20020185749A1 (en) 1996-03-07 2002-12-12 Farnworth Warren M. Mask repattern process
EP1359618A2 (en) 2001-04-17 2003-11-05 Casio Computer Co., Ltd. Semiconductor device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1079428A (ja) 1996-09-03 1998-03-24 Hitachi Ltd 電極配線の製造方法及び処理装置
US6440836B1 (en) * 1999-03-16 2002-08-27 Industrial Technology Research Institute Method for forming solder bumps on flip chips and devices formed
EP1107307B1 (en) 1999-06-15 2005-09-07 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
JP4196314B2 (ja) 1999-10-05 2008-12-17 富士通株式会社 Ｎｉ電極層の形成方法
JP4469927B2 (ja) 2000-05-23 2010-06-02 Ｄｉｃ株式会社 感光性組成物およびこれを用いた平版印刷版原版、画像形成方法
JP3596864B2 (ja) 2000-05-25 2004-12-02 シャープ株式会社 半導体装置
US6521996B1 (en) * 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
SG99939A1 (en) 2000-08-11 2003-11-27 Casio Computer Co Ltd Semiconductor device
JP4361223B2 (ja) 2001-03-19 2009-11-11 株式会社フジクラ 半導体パッケージ
US6781229B1 (en) * 2001-12-19 2004-08-24 Skyworks Solutions, Inc. Method for integrating passives on-die utilizing under bump metal and related structure
JP2003318212A (ja) 2002-04-26 2003-11-07 Murata Mfg Co Ltd 蒸着リフトオフによるバンプ形成に用いるレジストパターンおよびその形成方法、バンプおよびその形成方法、ならびに弾性表面波素子およびその製造方法
US6861749B2 (en) * 2002-09-20 2005-03-01 Himax Technologies, Inc. Semiconductor device with bump electrodes
JP2003142525A (ja) 2002-11-11 2003-05-16 Toshiba Corp 半導体装置
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08172161A (ja) * 1994-12-16 1996-07-02 Hitachi Ltd インダクタ素子とその製法およびそれを用いたモノリシックマイクロ波集積回路素子
US20020185749A1 (en) 1996-03-07 2002-12-12 Farnworth Warren M. Mask repattern process
JPH09330817A (ja) * 1996-06-12 1997-12-22 Fuji Electric Co Ltd 面状コイル装置およびその製造方法
JP2002057292A (ja) * 2000-08-11 2002-02-22 Iep Technologies:Kk 半導体装置および半導体装置の製造方法
EP1359618A2 (en) 2001-04-17 2003-11-05 Casio Computer Co., Ltd. Semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 11 29 November 1996 (1996-11-29) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 04 31 March 1998 (1998-03-31) *
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 06 4 June 2002 (2002-06-04) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2100328A1 (en) * 2006-12-11 2009-09-16 FlipChip International L.L.C. Solder bump/under bump metallurgy structure for high temperature applications
EP2100328A4 (en) * 2006-12-11 2011-12-07 Flipchip Internat L L C LÖTHÖCKER - / - UNDERHELLING METALURGY STRUCTURE FOR HIGH-TEMPERATURE APPLICATIONS

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US7125788B2 (en) 2006-10-24
CN1674763A (zh) 2005-09-28

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