EP1584113A2 - Transistor a effet de champ organique et circuit integre - Google Patents

Transistor a effet de champ organique et circuit integre

Info

Publication number
EP1584113A2
EP1584113A2 EP03799430A EP03799430A EP1584113A2 EP 1584113 A2 EP1584113 A2 EP 1584113A2 EP 03799430 A EP03799430 A EP 03799430A EP 03799430 A EP03799430 A EP 03799430A EP 1584113 A2 EP1584113 A2 EP 1584113A2
Authority
EP
European Patent Office
Prior art keywords
ofet
electrode
integrated circuit
electrodes
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03799430A
Other languages
German (de)
English (en)
Inventor
Walter Fix
Andreas Ullmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PolyIC GmbH and Co KG
Original Assignee
PolyIC GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PolyIC GmbH and Co KG filed Critical PolyIC GmbH and Co KG
Publication of EP1584113A2 publication Critical patent/EP1584113A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/80—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]

Definitions

  • the invention relates to an organic field effect transistor (OFET) and / or an integrated circuit on an organic basis with a high switching frequency.
  • OFET organic field effect transistor
  • a disadvantage of the known layout for organic electronics is that no organic conductor tracks are provided.
  • the task is to redesign the basic components of all digital circuits such as transistors, inverters and NAND or NOR gates and to create a suitable layout for them.
  • the invention therefore relates to an organic field effect transistor, at least a first electrode layer with source and drain electrodes, a semiconducting layer, a Insulator layer and a second electrode layer comprising, in which in the first electrode layer one of the electrodes, source or drain the other except for one side or location, the connection side or location of this electrode, 2-dimensionally, so that a current channel can be formed, that begins and ends on one side or location of an electrode of the first electrode layer.
  • the source electrode delimits the drain electrode of each organic field effect transistor (OFET) used on three sides, the respectively enclosed electrode, the drain electrode (drain and source can of course also be interchanged) only open on one side and has only one connection on one side, ie the current channel that forms after the gate voltage is applied begins and ends on the same side of the electrode, the connection side, and is eg U-shaped or meandering.
  • OFET organic field effect transistor
  • the OFETs are arranged in the NAND or NOR gate such that the connection sides are opposite each other.
  • the NAND and / or in the NOR gate there are 2 or more OFETs in parallel (two or more U-shaped channels next to one another in the NOR gate) or one inside the other (two or more U-shaped channels one inside the other in the NAND gate) nested.
  • the connecting lines and / or the inputs and outputs are each preferably located in the area between the connection sides.
  • the gate electrode also covers a small part of the source or drain electrode in addition to the entire channel.
  • the current channel is completely covered and additionally at least part of one or both of the first electrodes, this additional covered part lying in the width in the range from 0 to 20 ⁇ m and in length in the range of the length of the current channel.
  • the width of the coverage depends on the adjustment accuracy of the production technology and is in the range from a few (0 to 8) ⁇ m to about 20 ⁇ m, preferably 1 to 5 ⁇ m.
  • holes or interruptions in the semiconductor layer that reduce leakage currents between the OFETs are provided. These holes are preferably located between the connection sides. These subsequently created holes or interruptions serve to reduce leakage currents that are generated by the unintentional background doping or contamination of the typically unstructured semiconductor layer that covers the entire chip.
  • Yet another embodiment provides that instead of an electrical connection, which is sometimes necessary between the gate electrode and the drain electrode of a load OFET, a through contact is used, which is additionally connected to the output of the inverter. This saves at least one through-contact. Typically, one through-contact is required for the gate-drain connection from the load FET and another at the inverter output for the
  • the via is preferably shaped so that it extends to one or both sides of the OFET.
  • the leakage currents are minimized on the one hand by the arrangement of the electrodes and on the other hand by the holes in the semiconductor layer.
  • the arrangement of the electrodes completely suppresses leakage currents between different inverters or NAND or NOR gates, since neighboring electrodes are each at the same electrical potential (supply voltage or ground), which in turn is a consequence of the fact that an OFET electrode has the respective encloses and shields others up to one side or place.
  • the electrode 5 is grounded and the electrode 1 is connected to the supply voltage, two immediately adjacent inverters (one above the other in the figure) then only touch electrodes with the same potential (see also FIG. 5).
  • Circuits are much simpler to design in accordance with the invention: the inverters or the logic gates can be assembled in a modular manner without having to maintain distances.
  • the channel geometries channel length and width
  • the space required for the circuit is smaller, which is why the entire available area can be used to advantage.
  • the number of vias is reduced by reducing the number (see FIG. 5).
  • Figure 1 shows two layouts for an OFET.
  • Figure 2 shows two layouts for an inverter.
  • Figure 3 shows a layout for a 2-fold NOR gate.
  • FIG. 4 shows a layout for a double NAND gate
  • Figure 5 shows a layout for a 5-stage ring oscillator
  • FIG. 1 shows an OFET with a first electrode 1 (source or drain) and a second electrode 2 (drain or source), the first electrode 1 enclosing the second electrode 2 except for one side or on three of four sides. All that remains is the connection side 4 of the OFET, on which the first electrode 1 does not surround the second electrode 2.
  • Figure la shows the simplest version in which a U-shaped current channel (OFET channel 3) is formed and ⁇
  • Figure 1b shows a somewhat more elaborate embodiment in which a meandering OFET channel 3 is formed.
  • Figure 2 shows two layouts for an inverter
  • Figure 2a shows an inverter with load OFET on output:
  • the inverter u holds two OFETs, the load OFET (load OFET) and the control OFET (drive OFET).
  • the source electrode 1 of the load OFET surrounds the drain electrode 2 of the load OFET on three sides, an OFET channel 3 is formed, which is covered by the gate electrode 13 of the load OFET, with part of the source also -Electrode 1 and the drain electrode 2 of the load OFET are also covered.
  • the gate electrode 13 is connected via the via 10 to both the source electrode 2, the output 11 and the source electrode 7 of the drive OFET.
  • the gate electrode 8 of the drive OFET covers channel 6 of the drive OFET and is connected to the input 12.
  • Drain electrode 5 of the drive OFET encloses source electrode 7 and thus defines channel 6.
  • the holes or interruptions 9 in the semiconductor layer are located between load and drive OFET and prevent leakage currents.
  • the supply voltage is applied to electrode 1, electrode 5 is grounded.
  • the electrical connection which, depending on the circuit, between the gate electrode 13 and the drain electrode 2 of the load OFETs is necessary, is implemented via a via 10, which is additionally connected to the output 11.
  • FIG. 2b The example of an inverter shown in FIG. 2b) has the load OFET gate at the supply voltage.
  • the structure is analogous to that of Figure 2a).
  • the gate electrode 13 is here connected to the source electrode 1 through the via 10a and not as in 2a) with the via 10a to the output 11.
  • the through contact 10b is elongated to the edge of electrode 1, which has the advantage that inverters lying next to one another can use the through contact together.
  • the through contact is preferably shaped such that it extends to the sides of the OFET.
  • inverters, NAND or NOR gates connected in series have a common through-hole.
  • FIG. 3 A layout for a double NOR gate is shown in FIG. 3: The layout essentially corresponds to that of the inverter from FIG. 2b) with the difference that two drive OFETs are connected in parallel.
  • the second drive OFET comprises the source electrode 14 and has a common drain electrode 5 with the first drive OFET.
  • the gate electrode 15 of the drive OFET is connected to the second input 12b of the NOR gate.
  • the entire NOR gate is shielded by the two electrodes 1 and 5, which are connected to the supply voltage or ground.
  • a double NAND gate is shown in FIG.
  • the NAND layout also essentially corresponds to the inverter from FIG. 2b), with the difference that two drive OFETs are connected in series.
  • the second drive OFET is enclosed on three sides by the first.
  • Source electrode 7 of the first drive OFET is also the drain electrode of the second drive OFETs.
  • the source electrode 14 determines the channel 16 of the second drive OFET and is covered by the gate electrode 15, which is connected to the second input 12a. This layout also results in shielding by electrodes 1 and 5.
  • FIG. 5 finally shows a 5-stage ring oscillator which comprises five inverters which are constructed in accordance with FIG. 2b.
  • the inverters are arranged so that a common via 10 (10b) in the middle can be used for all inverters.
  • the inverters are arranged directly abutting one another, which is only possible due to the layout according to the invention.
  • the inverters are connected by the connecting lines 17, and the holes or interruptions in the semiconductor 9 between the connecting lines are also continued in order to prevent leakage currents.
  • the output 11 of the ring oscillator branches off on a connecting line 17.
  • FIG. 5 shows impressively how efficiently circuit layouts are created with the aid of the invention.
  • lines are replaced by direct contact, which e.g. leads to higher switching speed.
  • the invention relates to an organic field effect transistor (OFET) and / or an integrated circuit on an organic basis with a high switching frequency. Merging the two ends of the power channel results in compact and fast circuit layouts.
  • OFET organic field effect transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un transistor à effet de champ organique (OFET) et/ou un circuit intégré à base organique présentant une fréquence de commutation élevée. L'assemblage des deux extrémités du canal de courant permet d'obtenir des configurations de circuit compactes et rapides.
EP03799430A 2003-01-14 2003-12-08 Transistor a effet de champ organique et circuit integre Withdrawn EP1584113A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10301086 2003-01-14
DE10301086 2003-01-14
PCT/DE2003/004036 WO2004068608A2 (fr) 2003-01-14 2003-12-08 Transistor a effet de champ organique et circuit integre

Publications (1)

Publication Number Publication Date
EP1584113A2 true EP1584113A2 (fr) 2005-10-12

Family

ID=32797260

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03799430A Withdrawn EP1584113A2 (fr) 2003-01-14 2003-12-08 Transistor a effet de champ organique et circuit integre

Country Status (8)

Country Link
US (1) US20060145140A1 (fr)
EP (1) EP1584113A2 (fr)
JP (1) JP2006513578A (fr)
KR (1) KR100745570B1 (fr)
CN (1) CN1757123A (fr)
AU (1) AU2003299265A1 (fr)
DE (1) DE10394197D2 (fr)
WO (1) WO2004068608A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669720B1 (ko) * 2004-08-06 2007-01-16 삼성에스디아이 주식회사 평판 디스플레이 장치
DE102005009819A1 (de) 2005-03-01 2006-09-07 Polyic Gmbh & Co. Kg Elektronikbaugruppe
JP2007123773A (ja) * 2005-10-31 2007-05-17 Fuji Electric Holdings Co Ltd 薄膜トランジスタ、及びその製造方法
US20080128685A1 (en) * 2006-09-26 2008-06-05 Hiroyuki Honda Organic semiconductor device, manufacturing method of same, organic transistor array, and display
DE102006047388A1 (de) * 2006-10-06 2008-04-17 Polyic Gmbh & Co. Kg Feldeffekttransistor sowie elektrische Schaltung
JP2010040897A (ja) * 2008-08-07 2010-02-18 Sony Corp 有機薄膜トランジスタ、有機薄膜トランジスタの製造方法、および電子機器
DE102009009442A1 (de) 2009-02-18 2010-09-09 Polylc Gmbh & Co. Kg Organische Elektronikschaltung

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JPH069214B2 (ja) * 1984-09-27 1994-02-02 株式会社東芝 薄膜集積回路の製造方法
JPS6230375A (ja) * 1985-07-31 1987-02-09 Fujitsu Ltd 薄膜トランジスタとその製造方法
TW454101B (en) * 1995-10-04 2001-09-11 Hitachi Ltd In-plane field type liquid crystal display device comprising liquid crystal molecules with more than two different kinds of reorientation directions and its manufacturing method
KR100393324B1 (ko) * 1998-06-19 2003-07-31 띤 필름 일렉트로닉스 에이에스에이 집적 무기/유기 보상 박막 트랜지스터 회로 및 그 제조방법
ATE344535T1 (de) * 1999-07-06 2006-11-15 Elmos Semiconductor Ag Cmos kompatibler soi-prozess
WO2001017029A1 (fr) * 1999-08-31 2001-03-08 E Ink Corporation Transistor pour ecran a commande electronique
WO2001027998A1 (fr) * 1999-10-11 2001-04-19 Koninklijke Philips Electronics N.V. Circuit integre
KR100654158B1 (ko) * 1999-10-25 2006-12-05 엘지.필립스 엘시디 주식회사 액정 표시장치 제조방법 및 그 제조방법에 따른 액정표시장치
US6284562B1 (en) * 1999-11-17 2001-09-04 Agere Systems Guardian Corp. Thin film transistors
EP1243035B1 (fr) * 1999-12-21 2016-03-02 Flexenable Limited Formation d'interconnexions
CN1181546C (zh) * 2000-03-28 2004-12-22 皇家菲利浦电子有限公司 带可编程存储器单元的集成电路

Non-Patent Citations (1)

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Title
See references of WO2004068608A2 *

Also Published As

Publication number Publication date
KR100745570B1 (ko) 2007-08-03
WO2004068608A2 (fr) 2004-08-12
DE10394197D2 (de) 2005-12-01
AU2003299265A8 (en) 2004-08-23
WO2004068608A8 (fr) 2005-08-04
AU2003299265A1 (en) 2004-08-23
CN1757123A (zh) 2006-04-05
US20060145140A1 (en) 2006-07-06
KR20050103195A (ko) 2005-10-27
JP2006513578A (ja) 2006-04-20
WO2004068608A3 (fr) 2004-10-14

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