EP1570951A2 - Procédé de production de plaquettes semiconductrices comprenant des surfaces pauvres en défauts, l'utilisation de telles plaquettes et les ensembles électroniques ainsi obtenus - Google Patents

Procédé de production de plaquettes semiconductrices comprenant des surfaces pauvres en défauts, l'utilisation de telles plaquettes et les ensembles électroniques ainsi obtenus Download PDF

Info

Publication number
EP1570951A2
EP1570951A2 EP05004484A EP05004484A EP1570951A2 EP 1570951 A2 EP1570951 A2 EP 1570951A2 EP 05004484 A EP05004484 A EP 05004484A EP 05004484 A EP05004484 A EP 05004484A EP 1570951 A2 EP1570951 A2 EP 1570951A2
Authority
EP
European Patent Office
Prior art keywords
polishing
wafer
wafers
substrate
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05004484A
Other languages
German (de)
English (en)
Other versions
EP1570951A3 (fr
Inventor
Peter Blaum
Burkhardt Speit
Ingo Köhler
Bernd Ruedinger
Wolfram Beier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Schott AG
Original Assignee
Schott AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schott AG filed Critical Schott AG
Publication of EP1570951A2 publication Critical patent/EP1570951A2/fr
Publication of EP1570951A3 publication Critical patent/EP1570951A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor

Definitions

  • the invention relates to low-voltage substrate wafer with a defect-poor, active surface, a method too their preparation and their use and thus obtained electronic components, such as LEDs, transistors and chips.
  • Electronic and electro-optical semiconductor elements such as lasers, high-speed transistors, LDs, LEDs and other complex components usually include a thin carrier or wafer substrate on which in particular terraced superimposed functional layers lie.
  • Such functional layers are usually semiconductor or insulation or Leveling layers.
  • the procedure is usually such that the wafer wafer from a block, cylinder or rod of the sawn out of respective substrate and then ground, lapped and polished to a possible to get even and smooth surface, the one Maximum elasticity or flatness and minimal roughness having.
  • the grinding and polishing of the wafers is normally performed in such a way that the Wafer substrate is mounted in a holder, preferably rotated about its longitudinal axis and thereby optionally its direction of rotation changes, d. H.
  • the wafer substrate is also used on one changing direction of rotation rotating grinding or polishing plate pressed, which equipped with a polishing pad is. In this way, the substrate surface to be coated becomes as evenly as possible and removed Smoothed, resulting in good to very good surfaces receive. Only then will those beforehand said functional layers on the solid, as a rule applied very thin substrate wafer.
  • MOCVD organometallic Gas phase epitaxy
  • MOCVPE metal organic chemical vapor phase epitaxy
  • defects in the surface be it disturbances of the crystal structure, Impurities or even unevenness in the surface as well as other defects to faulty Jobs in the layer structure can lead, which the desired electrical, insulating and / or electro-optical Affect the function of the layers.
  • a particularly suitable method for detecting this typical Defects is the interference microscopy (eg. using a Leica interference microscope, 160 times (16x10) magnification, resolution max. 0.8 ⁇ m).
  • the invention therefore has the object of wafer substrates for the Production of electronic and / or electro-optical To provide semiconductor elements which oppose Temperature fluctuations in the coating with Epitaxy are insensitive and make up of semiconductor elements let that win in their semiconductor layers at least low in defects and in particular the surface are "pit" -free.
  • this is achieved ensures that the substrates to be coated freely movable are arranged between polishing elements. On In this way, wafer substrates are obtained, which at a Coating, in particular in the epitaxy process, sometimes insensitive to temperature changes are, but also low-defect and in particular result in defect-free components.
  • the Wafer substrates preferably on a support (support table with a support surface) and with a Pressed counter element on the support. It can either the support, the counter element or both as Polierwerkmaschine be formed. Preferably both are prepared as polishing tools. Between these Both elements (support element and counter element) can The substrates during polishing relatively move freely to the polishing tool in any direction. This free movement includes both two-dimensional linear as well as curved movements and rotations about one perpendicular to the wafer surface standing axis with a.
  • the edition points preferably a boundary or an edge, the the pad limits on which the wafer substrate rests and on which the wafers are free during polishing can move without falling off the support.
  • the pad preferably has one possible flat surface and is in particular completely planar.
  • a preferred embodiment comprises one, at least a flat, holey recess having Guide disc, wherein the recess has a larger Diameter than the wafer to be processed.
  • that forms Recess a the thickness of the plate penetrating hole Conveniently, such a guide plate several such recesses or holes, which means Punching or sawing are available. In these Recess or hole of the wafer to be treated is introduced.
  • the hole in the guide disc acts as a cage or "carrier" within which the wafer or wafers are freely movable.
  • the guide disc on the Edition loose, freely movable arranged, so too this in the polishing and grinding process in all Move and rotate spatial directions.
  • the guide disc usually consists of metal and / or a Plastic.
  • the wafer is in Polished form of a laminate. This is done by the wafer glued on a carrier. Preferably then lies at Polishing the carrier freely moving, sliding on the Edition and the pressure forces of the polishing tools act in a more or less vertical direction the wafer surface to be treated. In principle however, it is also readily possible that when polishing the wafer with its to be polished and later to Coating active surface sliding down freely is arranged on the carrier. In a special preferred embodiment is inventively as Carrier used another wafer, so that both the on the support adjacent (outer) surface of the one Wafers (carrier wafer) as well as the opposite outer surface of the other (second) wafer at the same time to be polished.
  • the wafer laminates are guided freely movable in so-called cages or "carriers", the movements, which are constantly rotating as well as the requirements complete.
  • both the edition works as well as the overlying counter element as a polishing tool in the polishing device.
  • the polishing is preferably carried out with the aid of a polishing agent or polishing medium performed.
  • a polish In principle, all common polishing media can be used as long as there are no scratches or other mechanical Cause damage in the wafer surface and a sufficient surface smoothness or minimum Create surface roughness while maintaining a flatness (flatness) of the wafer surface, which Grinding and lapping the wafer was not achieved destroy again, but improve.
  • polishing are those induced by the grinding or lapping steps Deep damage, also SSD (Sub Surface Damage) called, worked out without disturbing new others Create damage. Beyond that the depth damage generated from the prepolishing process steps removed and an optimal germ density for ensured epitaxial coating.
  • Polishing agents to be used in the process according to the invention preferably contain polishing bodies. These polishing bodies preferably have an average particle size with a diameter of 10-1000 nm, with particles having a diameter of 50-500 nm, in particular 150-300 nm, being particularly preferred. Such average diameters or particle sizes are usually determined optically in a known manner in the scattered light method. For example, a device of the company " Lambda Physics” (Göttingen, DE) offers the device “ Lambda 900 UV / Vis / IR " with integrating sphere as a measuring device.
  • Preferred polishing agents are those used for treating silicon wafers, semiconductors, microchips, optical elements, and clock crystals and glass components.
  • the polishing according to the invention is performed abrasive by means of the respective grinding bodies, whereby a desired layer thickness is removed at the surface.
  • Preferred abrasive articles are colloidal silica, which is available as a slurry in standard industry standards.
  • Such a product is, for example, from the company "Eminess Technologies, Inc.” under the designation “Ultra-Sol” ( www.eminess.com/products/us_slurry.html ) or also offered by the company “Rodel” with the trade name “NALCO” of the “Ondeo NALCO Company” (Naperville, IL, USA) ( www.rodel.com/rodel/products/Substrates ).
  • these abrasives are used as a sol.
  • the particle sizes vary between 20 and 300 nm.
  • the abrasive usually has a pH of 5-11, preferably 6.5-11, and especially 8.5-10.5.
  • a preferred buffer for adjusting the pH is bicarbonate.
  • the polishing is usually carried out under pressure.
  • the polishing tool is pressed onto the surface to be polished.
  • Such pressures are usually 0.05-1 kg / cm 2 , in particular 0.1-0.6 kg / cm 2 , with 0.15-0.35 kg / cm 2 being particularly preferred.
  • the polishing is usually done with a possibly oscillating Rotation speed of 5 - 200 rpm, in particular 10 to 80 rpm, whereby 20 to 50 RPM are particularly preferred. Usual polishing times can last up to 10 hours, with polishing times up to 4, especially up to 2.5 hours, particularly preferred are.
  • Abtragsdicken of 0.5 - 5 microns / h, in particular 0.8-3 ⁇ m / h, and in particular removal rates of 1 - 2 ⁇ m / h.
  • the polishing according to the invention is preferably at Temperatures of below 100 ° C, preferably below 50 ° C, with temperatures below 25 ° C are particularly preferred. Especially preferred is to perform the polishing at room temperature of 20 ° C, with deviations of +/- 8 ° C, in particular +/- 5 ° C and preferably +/- 2 ° C are quite possible.
  • the temperature at which the wafers are polished is critical once the consistency of the abrasive, for example, by agglomeration of the abrasive particles and / or increasing the viscosity, substantially changes.
  • Substrates become a wafer on a freely movable Carrier, in particular a polishing plate or else releasably connected to another wafer.
  • an adhesive It is the Adhesive layer thickness preferably 0.5-5 ⁇ m, wherein 0.8 - 3 microns, and especially 1 - 2 microns particularly preferred is.
  • the adhesive is preferably softenable by heating, so that the wafers bonded for polishing or wafer and carrier by increasing the temperature let solve again.
  • the adhesive preferably a softening temperature below 150 ° C, especially below 120 ° C, in particular of ⁇ 100 ° C.
  • the glue should be selected in the method according to the invention such that this has a softening temperature, at least 10 ° C, preferably at least 20 ° C above the temperature at which the surface is polished.
  • a preferred adhesive shows pressure, shear and / or elastic properties.
  • wax and / or rosin are particularly preferred.
  • Mixtures thereof are particularly preferred.
  • usable waxes can be both herbal as well as animal and / or mineral waxes, if necessary also mixtures thereof.
  • Useful vegetable waxes Candelila, Cornauba, Japan, Esparto, Cork, guaruma, rice germ oil waxes etc are preferred animal waxes are especially beeswax, spermaceti, Lanolin as well as raffia fat.
  • Useful mineral waxes are ceresin, petrolatum, paraffin and microwaxes as well as fossil waxes. Such waxes can both of course, as well as chemically altered or completely be synthetic.
  • Beeswax which has a melting point of 60-70 ° C or 63 - 65 ° C, as well as similar waxes with a similar composition or similar properties.
  • wax esters the contain as alcohol component in particular 1-triacontanol, which in particular with palmitic and cerotic acid is esterified.
  • Wax esters of hydroxy fatty acids such as ceryl hydroxypalmitate and derivatives thereof verwenbar.
  • the adhesive to be used according to the invention is preferably removable from the wafer substrate.
  • the removal For example, by liquefying the Heating can be achieved and / or through use more suitable the wafer or the properties of the Wafer's non-damaging solvent.
  • preferred wafer substrates are crystalline wafer substrates, with crystalline Al 2 O 3 (sapphire) and SiC crystals being particularly preferred.
  • Al 2 O 3 crystals are usually obtained by the known cultivation methods such as, for example, the Czochralskitechnik.
  • the method according to the invention is independent of its preparation and the preceding treatment steps for any wafer substrates and leads to the desired good results.
  • the method according to the invention it is possible to produce wafer substrates which are suitable for the production of electrical and / or electro-optical components with semiconductor layer systems, which are extremely low in defects and in particular a pit density of ⁇ 1000 / cm 2 , especially ⁇ 500 / cm 2 , where ⁇ 100 / cm 2 is particularly preferred.
  • a particularly preferred polishing method according to the invention is carried out by means of CMP (chemical-mechanical polishing).
  • CMP chemical-mechanical polishing
  • silicon colloids which were hydrolyzed by a sol-gel method of methyl silicates and 100-200 ppm ammonium salts in an alcohol / water solution to finely dispersive colloid, are preferably used.
  • a common solution contains 25% of such colloids, the particle size being between 550 nm, in particular between 250 nm.
  • Bacterial formation can be prevented for example by the addition of hydrogen peroxide.
  • colloids are commercially available. It is important to ensure that agglomeration, for example by dehydration or condensation of the silicon colloids is avoided, which can lead to the formation of scratches on the substrate surfaces.
  • the SiO 2 reacts with Al 2 O 3 to form an Al 2 Si 2 O 7 aluminosilicate, which is softer than the sapphire (Al 2 O 3 ).
  • Al 2 O 3 aluminosilicate
  • it is easy to remove by polishing with mechanical pressure.
  • the invention also relates to the substrate wafer obtained by means of the method according to the invention and its use for the production of electronic components in high-temperature and high-power electronics, in lasers and in high-intensity light-emitting diodes.
  • the invention also relates to the use of such wafers for the production of solar cells.
  • the invention also relates to electronic Semiconductor components, one or more of each other arranged on a substrate low-defect layers includes semiconducting materials and by means of the process according to the invention is available. This includes in particular the production of a single crystal and optionally annealing the single crystal such a single crystal to wafer substrate discs, Grinding and / or lapping and polishing the discs including the final polishing and cleaning according to the invention at least one of the disc surfaces.
  • FIG. 1 An inventive method is in the accompanying Figure 1 shown.
  • the resulting laminate 10, 20, 30 has outer surfaces 12, 22 and inner surfaces glued together 14, 24, and lies on one about an axis 48 rotating polishing plate 40 on.
  • the polishing plate is at its outer edge with walls 44 which provide a Falling out of the wafer laminate and / or the guide disc prevent. This is done through a targeted Fixation and guidance of the wafers on the plate and will preferably by plastic discs, so-called cages or "Carrier" reached (not shown).
  • On its inner surface 42 contains the polishing plate a polishing agent 50 containing fine particles.
  • the polishing plate may possibly also have an eccentric rotation perform, but with alternating rotations Turning directions, d. H. oscillatory rotations preferred are.
  • a pressure plate acts on the wafer laminate 60, which at its lower side 62 likewise an abrasive 50.
  • the pressure plate 60 rotates or also oscillates about a longitudinal axis 66.
  • the polishing agents are preferably applied to a cloth (not shown) applied. Such polishing cloths For example, consist of commercially available polyurethane towels.
  • the CMP process is preferably as a multi-level Procedure carried out, the grain size is reduced.
  • a common reduction in grain size ranges from 100 - 10 nm, with a reduction of 600 - 40, in particular 500 - 50 nm is particularly preferred.
  • the polishing process according to the invention the grain size in at least two stages, preferably reduced to three levels.
  • Figure 2a shows the surface of a LED (Light Emitting Diode) structure processed according to the invention Wafer surface (see Table 2)
  • Figure 2b the in Table 2 described surface of a LED coated commercially available comparative wafer (Comparative wafer No. 3).
  • FIG. 3 shows interference microscopy Recordings of those described in Table 3 HEMT (High Electron Mobility Transistor) structures, the epitaxially processed on sapphire substrates according to the invention (Fig. 3a) and commercial comparison material (Fig. 3b-c) at temperatures of 50 K. above the optimum process temperature specified by the manufacturer have grown up.
  • HEMT High Electron Mobility Transistor
  • FIG. 4 a shows the respective surface quality of a commercially available sapphire substrate after carrying out a standard polishing process, as is commercially available, and FIG. 4 b of the same wafer after polishing according to the invention has been carried out.
  • the sapphire substrate polished according to the invention shows the homogeneous-symmetrical surface structure which is particularly preferred for an epitaxial coating.
  • the surface of the inventively polished substrate not only has a much lower roughness of 0.2 nm, but also a much greater flatness of 5 microns over the entire diameter of 2 or 4 "on.
  • a sapphire crystal with a diameter of 55 mm and a length of 200 mm was grown by means of the Czochralskimethode and then annealed, as described in the unpublished DE-A 103 06 801.5 of the same applicant. Subsequently, the monocrystal thus obtained was sawed in a manner known per se, into thin disks of thickness 0.5 mm and ground and lapped according to the usual methods used for the production of sapphire wafers, as described, for example, in F. Schmid et al. US Pat 6,418,921 B1 . Thereafter, the wafers were subjected to a polishing method of the present invention as follows.
  • Two wafer substrates each were attached to one Glued side together.
  • As an adhesive was a Rosin beeswax blend with a softening point used by 80 ° C, in an adhesive thickness of about 2 microns.
  • This laminate was then prepolished in a silicon suspension with particle sizes of 250-300 nm for 1.5 hours chemical-mechanical and then polished in a further polishing machine with the colloidal silicon suspension with particle sizes of 80 nm chemical-mechanical with variable polishing time. Both processes took place at process pressures of 0.1-0.3 kg / cm 2 and rotational speeds of the polishing plates of 50-150 rpm. In this case, the wafer substrates were bonded together by means of different mixing ratios, which have different softening temperatures. The adhesives were adjusted so that their softening temperature for the separation required a force of not more than 1 Kp (per 5 cm wafer [equivalent to 20 cm 2 ]).
  • the wafer substrates obtained according to the invention were coated with HEMT functional layers by means of a conventional process under the same conditions in a multiwafer MOCVD plant, wherein, however, the process temperature was varied during the coating time.
  • Table 3 It was found that in wafers which were treated by the method according to the invention, the process temperature in a wide range, ie can fluctuate up to 50 ° C, without causing growth errors. In the wafers of the prior art, even slight changes in the coating lead to a large number of growth defects, as documented in FIGS. 3a-3c and Table 3. This surprising difference is achieved exclusively by means of the polishing method according to the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Semiconductor Lasers (AREA)
EP05004484A 2004-03-03 2005-03-01 Procédé de production de plaquettes semiconductrices comprenant des surfaces pauvres en défauts, l'utilisation de telles plaquettes et les ensembles électroniques ainsi obtenus Withdrawn EP1570951A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004010379A DE102004010379A1 (de) 2004-03-03 2004-03-03 Verfahren zur Herstellung von Wafern mit defektarmen Oberflächen, die Verwendung solcher Wafer und damit erhaltene elektronische Bauteile
DE102004010379 2004-03-03

Publications (2)

Publication Number Publication Date
EP1570951A2 true EP1570951A2 (fr) 2005-09-07
EP1570951A3 EP1570951A3 (fr) 2006-04-05

Family

ID=34745363

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05004484A Withdrawn EP1570951A3 (fr) 2004-03-03 2005-03-01 Procédé de production de plaquettes semiconductrices comprenant des surfaces pauvres en défauts, l'utilisation de telles plaquettes et les ensembles électroniques ainsi obtenus

Country Status (5)

Country Link
US (1) US7367865B2 (fr)
EP (1) EP1570951A3 (fr)
JP (1) JP5105711B2 (fr)
CN (1) CN1684234B (fr)
DE (1) DE102004010379A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8207539B2 (en) * 2009-06-09 2012-06-26 Epistar Corporation Light-emitting device having a thinned structure and the manufacturing method thereof
DE102009052744B4 (de) * 2009-11-11 2013-08-29 Siltronic Ag Verfahren zur Politur einer Halbleiterscheibe
JP7148427B2 (ja) 2019-02-06 2022-10-05 昭和電工株式会社 ＳｉＣエピタキシャルウェハ及びその製造方法
CN112720247B (zh) * 2020-12-30 2022-04-19 合肥晶合集成电路股份有限公司 一种化学机械平坦化设备及其应用

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531582A (en) * 1978-08-15 1980-03-05 Ibm Free polishing device
JPH06762A (ja) * 1992-06-17 1994-01-11 Sumitomo Electric Ind Ltd ウエハの片面研磨方法
JPH07161667A (ja) * 1993-12-13 1995-06-23 Sony Corp 半導体ウェハの研磨方法及びそれに用いるウェハホルダ
JP3534207B2 (ja) * 1995-05-16 2004-06-07 コマツ電子金属株式会社 半導体ウェーハの製造方法
US6395613B1 (en) * 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US5895583A (en) * 1996-11-20 1999-04-20 Northrop Grumman Corporation Method of preparing silicon carbide wafers for epitaxial growth
JPH11277413A (ja) * 1998-03-27 1999-10-12 Kyocera Corp ウェハ研磨盤
US6464571B2 (en) * 1998-12-01 2002-10-15 Nutool, Inc. Polishing apparatus and method with belt drive system adapted to extend the lifetime of a refreshing polishing belt provided therein
JP2001093867A (ja) * 1999-09-21 2001-04-06 Rodel Nitta Kk ウエハ外周部の保護部材及びウエハの研磨方法
JP4028163B2 (ja) * 1999-11-16 2007-12-26 株式会社デンソー メカノケミカル研磨方法及びメカノケミカル研磨装置
EP1439246B1 (fr) * 2000-04-07 2008-06-25 Hoya Corporation Procédé de fabrication de carbure de silicium monocristallin
KR20030024834A (ko) * 2000-08-07 2003-03-26 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 양측 폴리싱을 이용한 반도체 웨이퍼 처리 방법
US6709981B2 (en) * 2000-08-16 2004-03-23 Memc Electronic Materials, Inc. Method and apparatus for processing a semiconductor wafer using novel final polishing method
US6753954B2 (en) * 2000-12-06 2004-06-22 Asml Masktools B.V. Method and apparatus for detecting aberrations in a projection lens utilized for projection optics
US6418921B1 (en) * 2001-01-24 2002-07-16 Crystal Systems, Inc. Method and apparatus for cutting workpieces
AU2002340793A1 (en) * 2001-05-07 2002-11-18 Coatue Corporation Molecular memory device
US6488767B1 (en) * 2001-06-08 2002-12-03 Advanced Technology Materials, Inc. High surface quality GaN wafer and method of fabricating same
US6768157B2 (en) * 2001-08-13 2004-07-27 Advanced Micro Devices, Inc. Memory device
JP2003273049A (ja) * 2002-03-18 2003-09-26 Toshiba Ceramics Co Ltd ウエハの真空貼付装置
JP4206233B2 (ja) * 2002-07-22 2009-01-07 旭硝子株式会社 研磨剤および研磨方法
TWI257126B (en) * 2002-07-25 2006-06-21 Hitachi Chemical Co Ltd Slurry and polishing method
FR2843061B1 (fr) * 2002-08-02 2004-09-24 Soitec Silicon On Insulator Procede de polissage de tranche de materiau
US6770905B1 (en) * 2002-12-05 2004-08-03 Advanced Micro Devices, Inc. Implantation for the formation of CuX layer in an organic memory device
US6686263B1 (en) * 2002-12-09 2004-02-03 Advanced Micro Devices, Inc. Selective formation of top memory electrode by electroless formation of conductive materials
DE10306801A1 (de) * 2003-02-18 2004-09-02 Schott Glas Verfahren zur Herstellung von hexagonalen Einkristallen und deren Verwendung als Substrat für Halbleiterbauelemente
US6656763B1 (en) * 2003-03-10 2003-12-02 Advanced Micro Devices, Inc. Spin on polymers for organic memory devices
US6825060B1 (en) * 2003-04-02 2004-11-30 Advanced Micro Devices, Inc. Photosensitive polymeric memory elements
US6787458B1 (en) * 2003-07-07 2004-09-07 Advanced Micro Devices, Inc. Polymer memory device formed in via opening
US6803267B1 (en) * 2003-07-07 2004-10-12 Advanced Micro Devices, Inc. Silicon containing material for patterning polymeric memory element
US6852586B1 (en) * 2003-10-01 2005-02-08 Advanced Micro Devices, Inc. Self assembly of conducting polymer for formation of polymer memory cell

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None

Also Published As

Publication number Publication date
EP1570951A3 (fr) 2006-04-05
JP2005260225A (ja) 2005-09-22
CN1684234B (zh) 2012-08-01
US7367865B2 (en) 2008-05-06
JP5105711B2 (ja) 2012-12-26
US20050233679A1 (en) 2005-10-20
DE102004010379A1 (de) 2005-09-22
CN1684234A (zh) 2005-10-19

Similar Documents

Publication Publication Date Title
DE69723338T2 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE10132504C1 (de) Verfahren zur beidseitigen Material abtragenden Bearbeitung von Halbleiterscheiben und seine Verwendung
DE102009025243B4 (de) Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
DE10159833C1 (de) Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
DE69001411T2 (de) Verfahren zur Herstellung eines Substrats für Halbleiteranordnungen.
DE69127582T2 (de) Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates
DE10142400B4 (de) Halbleiterscheibe mit verbesserter lokaler Ebenheit und Verfahren zu deren Herstellung
DE112014003787B4 (de) Verfahren zum Herstellen eines spiegelpolierten Wafers
DE102009030292B4 (de) Verfahren zum beidseitigen Polieren einer Halbleiterscheibe
DE102009030295B4 (de) Verfahren zur Herstellung einer Halbleiterscheibe
DE3335116A1 (de) Halbleiterplaettchen sowie verfahren und vorrichtung zu ihrer herstellung
DE112011101813T5 (de) Glättungsverfahren für Halbleitermaterial und von daraus hergestellten Wafern
DE112015001512T5 (de) Siliziumkarbid-Einkristallsubstrat, Siliziumkarbid-Epitaxiesubstrat und Verfahren zur Herstellung derselben
DE102008059044A1 (de) Verfahren zum Polieren einer Halbleiterscheibe mit einer verspannt-relaxierten Si1-xGex-Schicht
DE10344602A1 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE112017006401T5 (de) Verfahren zum polieren eines siliziumwafers und verfahren zum produzieren eines siliziumwafers
DE112010003306B4 (de) Verfahren zur Herstellung eines epitaktischen Siliziumwafers
EP0857542B1 (fr) Méthode pour fabrication d'une plaquette semi-conductrice à une seule face et avec finition miroir
DE3148957C2 (de) Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben
DE102020211915A1 (de) Verfahren zum schleifen eines substrats
DE112012002597T5 (de) Verfahren zur Herstellung eines Siliciumcarbidsubstrats
DE112010002274B4 (de) Verfahren zur Herstellung eines Siliziumepitaxialwafers
DE102009025242B4 (de) Verfahren zum beidseitigen chemischen Schleifen einer Halbleiterscheibe
DE102004010379A1 (de) Verfahren zur Herstellung von Wafern mit defektarmen Oberflächen, die Verwendung solcher Wafer und damit erhaltene elektronische Bauteile
DE102006022089A1 (de) Verfahren zur Herstellung einer Halbleiterscheibe mit einr profilierten Kante

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050301

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR LV MK YU

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR LV MK YU

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20100517

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: B24B 37/30 20120101AFI20150817BHEP

Ipc: B24B 37/04 20120101ALI20150817BHEP

INTG Intention to grant announced

Effective date: 20150911

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20160122