EP1535274A1 - Unite de commande et procede pour reduire des modeles d'interferences lors de l'affichage d'une image sur un ecran - Google Patents

Unite de commande et procede pour reduire des modeles d'interferences lors de l'affichage d'une image sur un ecran

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Publication number
EP1535274A1
EP1535274A1 EP03793774A EP03793774A EP1535274A1 EP 1535274 A1 EP1535274 A1 EP 1535274A1 EP 03793774 A EP03793774 A EP 03793774A EP 03793774 A EP03793774 A EP 03793774A EP 1535274 A1 EP1535274 A1 EP 1535274A1
Authority
EP
European Patent Office
Prior art keywords
frequency
clk
pixel
control unit
ppll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03793774A
Other languages
German (de)
English (en)
Other versions
EP1535274B1 (fr
Inventor
Oliver Engelhardt
Andreas Eckhardt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Intellectual Property and Standards GmbH
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property and Standards GmbH, Koninklijke Philips Electronics NV filed Critical Philips Intellectual Property and Standards GmbH
Publication of EP1535274A1 publication Critical patent/EP1535274A1/fr
Application granted granted Critical
Publication of EP1535274B1 publication Critical patent/EP1535274B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the present invention relates to a control unit and a method for controlling a screen, and more particularly to a control unit and a method for reducing interference patterns when displaying an image on the screen.
  • the present invention relates to a method and a control unit for use with a TFT / LCD screen.
  • PC personal computer
  • VGA video graphics adapter
  • the input signals provided to the control chip 800 by the input sources 802 to 806 are applied to an input selection unit 808, which selects the input signals to be processed and provides them to an input 810 of the control chip 800.
  • FIFO First In First Out
  • the processing unit 812 outputs the pixel data to be displayed on the screen at a pixel frequency ppll_clk to the screen via an output 814 and the output interface 816.
  • the control chip 800 further comprises a configuration block 818, which is operated with the system clock sys_clk.
  • the signals are present in front of the processing unit 812 with the clock fclk, which corresponds to the clock of the input signals detected by the input sources 802 to 806 (DVI_clk, AVI_clk, PVI_clk).
  • clock domains of the input sources (AVI_clk, DVI_clk, PVI_clk) on the control chip 800, depending on the type of control unit, further clocks (domains) for the memory interface 814 (mpll_clk) and the screen interface 818 (ppll_clk).
  • the system clock sys_clk is also provided.
  • the control chip 800 shown in Fig. 8 is arranged, for example, on a printed circuit board, and receives e.g. the video or graphic signals provided by a computer for processing and display on the screen.
  • control units The problem with such control units is that the clock signals couple via the substrate of the control chip 800 into one or more inputs of the control chip and overlap with the signals present. This creates disruptive interference patterns when the data is displayed on the screen. This problem is explained below using the signals received at the analog input.
  • the DVI input 804 can also be disturbed by the other clock signals (clock domains) via the substrate of the chip, but the following explanations are limited to the analog input 802 for the sake of simplicity (AVI) as interference sink, wherein the memory and screen clock signals mpll_clk and ppll_clk are regarded as a source of interference, which couple into the analog input AVI via the substrate of the control chip 800, which is usually of low impedance.
  • AVI analog input 802 for the sake of simplicity
  • mpll_clk and ppll_clk are regarded as a source of interference, which couple into the analog input AVI via the substrate of the control chip 800, which is usually of low impedance.
  • interference with LCD control units is the coupling of the interference signal into the analog video input 802 (AVI) with the frequency of the screen clock ppll_clk (pixel frequency) or the harmonic harmonics of this clock.
  • AVI analog video input 802
  • ppll_clk pixel frequency
  • the interference signal is generated and gets into the low-resistance substrate of the chip 800.
  • the main source for the substrate voltages are the input / output drivers of the output interface 818.
  • FIG. 9 An equivalent circuit diagram of the screen interface or output interface 818 from FIG. 8 is shown with reference to FIG. 9.
  • the elements of the control chip are shown in the left section of FIG. 9 (left of the dashed line) and the elements of the circuit board are shown on the right of the dashed line.
  • the interface receives at a driver stage 822 the pixel signals to be displayed on the screen with the pixel frequency of the screen ppll_clk.
  • the driver stage 822 comprises a first field effect transistor 822a and a second field effect transistor 822b.
  • the output of the driver stage 822 is connected to a connection area of the control chip 800, the connection area having an impedance with an ohmic component and a capacitive component against the substrate mass, which is indicated in FIG. 9 by the resistance Ri and the capacitance Ci is.
  • the control chip 800 is connected to a housing via a bonding wire in order to connect a connection area of the control chip to a connection area of the chip housing.
  • the inductive component of Li and the ohmic component R 2 is the impedance of the wire shown Bond ⁇ .
  • the capacitive, inductive and ohmic components of the impedances of the connection area and the housing to which the control chip 800 is connected via the bonding wire are shown as a resistor R 3 , as an inductor L 2 and as capacitors C 2 and C 3 .
  • a transmission line TL Transmission Line
  • driver stage 824 comprises a first field effect transistor 824a and a second field effect transistor 824b.
  • the capacity C illustrates a capacity of the housing of the driver stage 824.
  • FIG. 9 also shows the voltage u L (t) dropping across it with respect to the inductance Li.
  • one of the main sources of substrate voltages is the output signals of the input / output driver stage 822 of the screen interface.
  • This interface generates very steep signals (high di / dt) via the inductors Li, L 2 and the resistors R x , R 2 , R 3 of the bonding wires and the connection pads. This leads to the fact that voltages of up to a few 100 mV (u L (t)) can drop over the bond wires, which, due to the driver layout, couple directly or indirectly to the substrate of the control chip 800.
  • Another source of interference at the analog input of the control chip 800 can be ground or supply voltage disturbances (bounces), which are caused by a slight or no decoupling on the control chip in the digital gore or by inadequate routing of the lines carrying the supply voltage (power routing ) can arise.
  • FIG. 10A shows an example of such an interference pattern, which was simulated for an LCD control unit with a screen interface based on a C model.
  • the course of the interference pattern shown in FIG. 10A largely corresponds to the course to be observed in a real LCD control unit.
  • the very steep signals (high di / dt) generate inductive voltages across the bond wires, which couple into the substrate and can influence the analog circuits from there.
  • both frequencies are considered independently of one another, a superposition of two interference patterns as shown in FIG. 10B is possible. Only the fundamental frequencies are taken into account here and not the harmonic frequency components, which in turn would lead to a different interference pattern.
  • the interference frequency fmterf is first calculated from this:
  • a maximum / minimum of the interference thus occurs periodically with a distance of
  • decimal value of (interf / line) * n ma ⁇ in the last line determines the starting value of the interference in the following frame (f + 1), which means that in most If the diagonal lines move up or down. The result is, depending on the vertical frequency of the screen, moving diagonal lines that move in one direction over the original image. In the case of rigid frequency ratios, the apparent speed and direction of this movement are constant and only depend on the interference frequency and the time course of the input signal at the analog video input.
  • the mechanism of interference generation is more complex, because not only all harmonic frequency components, but also the dynamic behavior of all components on the control chip and the external elements, e.g. the phase-locked loops on the control chip, the input signal sources, etc., play an important role play, but in principle the resulting interference can also be calculated here.
  • the correlated interference patterns generated on the screen due to the mechanisms described above are visible to a user / viewer and therefore annoying.
  • the present invention is therefore based on the object of providing a method and a control unit which avoids the visible interference on a screen.
  • the present invention provides a method for reducing interference patterns when displaying an image on a screen with a pixel frequency, the image being writable by pixel data which are provided to the screen by a control unit, one or more of the clock signals used in the generation of the pixel data being varied during the generation of the pixel data.
  • the present invention provides a method for reducing interference patterns when displaying an image on a screen at a pixel frequency, the image being writable by pixel data provided to the screen by a controller, the pixel frequency being generated during the generation of the pixel data will be changed.
  • the present invention further provides a control unit for controlling a screen operating at a pixel frequency, for displaying an image on the screen with a reduced interference pattern.
  • the control unit comprises egg NEN input for receiving image data, a processing device which processes the received image data to generate the pixel data, wherein the processing means during the generation of the pixel data re one or more ⁇ of the clock signals used in generating the pixel data varies, and an output to provide the pixel data for display.
  • the present invention further provides a control unit for controlling a screen that operates at a pixel frequency, for displaying an image on the screen, with a reduced interference pattern.
  • the control unit comprises an input for receiving image data, a processing device which processes the received image data to generate the pixel data, the processing device changing the pixel frequency during the generation of the pixel data, and an output to provide the pixel data for display.
  • the method according to the invention and the control unit according to the invention manipulate the clock ratios on the control chip, as a result of which typical interference patterns are destroyed and thus made almost invisible.
  • the present invention is based on the knowledge that a rigid frequency ratio and a fixed input signal time curve are the cause for the formation of the interference pattern or the interference images. If it is no longer possible to avoid visible interference by designing the analog components alone, the frequency ratios on the chip are the starting point for solving the problems associated with interference images.
  • the approach according to the invention is to be seen in destroying the correlation or the rigid ratio of the frequencies used, so that no regular interference patterns can arise within a frame or within successive frames.
  • this correlation or the rigid ratio of the frequencies is destroyed by time-dependent frequency modulation.
  • the time-dependent frequency modulation is implemented by a continuous-time frequency modulation.
  • the time-dependent frequency modulation is implemented by a time-discrete frequency modulation.
  • the frequency modulation for a control chip is carried out by an external frequency source or, according to a further exemplary embodiment, by an internal frequency source implemented on the chip.
  • the frequency modulation is carried out by using spread spectrum phase locked loops).
  • FIG. 3 is a block diagram illustrating clock generation in a control chip for a screen
  • FIG. 4 shows a block diagram of a control unit according to a first exemplary embodiment of the present invention with an external frequency modulation
  • FIG. 5 shows a control unit according to a second exemplary embodiment of the present invention with an internal frequency modulation
  • 6 shows the frequency response in the case of a spread spectrum phase locked loop
  • 7 shows an example of an interference pattern in an LCD control unit with a memory and screen interface
  • FIG. 9 shows an equivalent circuit diagram of the screen interface of the LCD control unit from FIG. 8;
  • 10A shows an interference pattern of an LCD control unit with a screen interface
  • 10B shows an interference pattern of an LCD control unit with a screen interface and a memory interface
  • 11 is an illustration for explaining the formation of an interference pattern.
  • the change in the pixel frequency to avoid the interference pattern is achieved by realizing a time-dependent frequency modulation FM which destroys the correlation or the rigid ratio of the frequencies, so that when the interference frequencies are coupled in Interference patterns can be reduced or suppressed.
  • the time-dependent frequency modulation is implemented by means of a continuous-time frequency modulation, for example by the function of a frequency sweep which encompasses a frequency range ⁇ f around the base frequency (f 0 ) required by the screen or the memory at a suitable rate, which is obtained by Modulation function g (t) is set, passes.
  • phase locked loop PLL Phase Locked Loop
  • ⁇ f frequency range around the base frequency
  • g (t) modulation function
  • the modulation function g (t) can be any continuous function, for example the functions shown in FIGS. LA to IC, but there is in principle no restriction with regard to the design and implementation of the function used.
  • the resultant pattern of interference will change continuously within each line and thus also within each individual frame, and if the function g (t) and the parameter ⁇ f are appropriately defined, it is possible to to generate an apparently uncorrelated "white" (quasi) noise from the originally correlated interference pattern.
  • the frequency f x iii n oo to be modulated does not change continuously, but, depending on the design, frame by frame or line by line. Any time specification can also be selected. As with continuous-time frequency modulation, the frequency can change continuously or randomly and suddenly by means of a suitable random generator, which enables more effective generation of “white” (quasi) noise.
  • the running index k is increased by 1 whenever a previously defined condition for a frequency change is fulfilled, eg. B. a line or frame change or the like occurs, that is, a new line or a new frame is reached.
  • 2A to C show examples of the discrete-time modulation frequency g (k), although it should also be pointed out here that there is basically no restriction with regard to the discrete function to be used.
  • the result is, with a suitable choice of the function g (k), the modulation condition and the parameter ⁇ f, a “white” (quasi) noise, which in the best case is not or only very slightly visible is.
  • both described methods for generating the time-dependent frequency modulation can be used in an extremely flexible manner by suitable determination of the modulation condition, which is also necessary due to the large number of possible input modes and input frequencies in order to adapt the method according to the invention to different ones To allow environmental conditions.
  • the circuit comprises a multiplexer 100, which receives a horizontal synchronization signal HS (H-Sync) at a first input.
  • the multiplexer 100 receives an external oscillator clock sys_clk at a second input. Based on a control signal, the multiplexer selects one of the two inputs as an input signal for generating the pixel clock ppll_clk.
  • the output signal selected by the multiplexer 100 is provided via a line 102 to a pre-divider 104 (pre-divider, n pred i V ), an output signal generated by this being provided via a further line 106 to the input of a phase-locked loop 108 which under control of an internal divider 110 (n d i V ) provides the pixel clock ppll_clk at the output.
  • the external oscillator clock sys_clk is further provided to a further pre-divider 112 (n pre - div ), which outputs an output signal to the phase-locked loop 116 via a line 114 at its output.
  • the phase locked loop 116 is controlled by an internal controller 118 (n div ) and outputs the memory clock mpll_clk at the output.
  • rclk is equal to the system clock or external oscillator clock sys_clk.
  • the basic circuit diagram shown in FIG. 3 is a control unit for clock generation for an LCD control chip with external memory, which generally has at least four different clock cycles (clock domains) that are in a specific, time-variant relationship to one another. 3, a configuration for clock generation is also considered, which can also be found in later implementations and applications.
  • phase-locked loop 108 (IIpll), which can use the horizontal synchronization signal HS of the analog video input AVI as the input signal, all other phase-locked loops are generated by the external oscillator clock sys_clk driven.
  • the situation is different with the memory clock mpll_clk and screen clock (pixel clock) ppll_clk, which are generated by the associated phase locked loops 108 and 116 (ppll, mpll).
  • These clock signals not only clock very large digital blocks of the LCD control chip, but also the corresponding input / output interfaces, namely the memory interface and the screen interface.
  • the external oscillator clock can be used as the input signal in both phase-locked loops and the desired frequency of the clock signal at the output can be set by programming the pre-dividers 104, 112 and the internal loop dividers 110, 118.
  • the screen phase-locked loop can also use the H-sync signal of the selected input, in the illustrated embodiment the signal HS of the analog video input, as the input signal.
  • a first exemplary embodiment is described with reference to FIG. 3, in which the frequency-modulated system clock is fed in by an external source.
  • 4 shows a section of the circuit elements shown in FIG. 3 for generating the pixel clock ppll_clk and the memory clock mpll_clk, the system clock sys_clk being fed in externally being selected as the input signal to the phase locked loop 108 for generating the pixel clock for the implementation of the method, so that, for the sake of simplicity, the multiplexer 100 shown in FIG. 3 has been omitted in FIG. 4.
  • FIG. 4 shows that instead of the external quartz or crystal oscillator 126 used in conventional LCD control chips, a wobble generator 128 is now used to provide the system clock sys_clk. This is shown by the broken connection between the quasi-oscillator 126 and the pre-dividers 104 and 112 (n prediv ) at 130.
  • the exemplary embodiment shown in FIG. 4 is a simple implementation of the present invention, with an external frequency generator 128, for example an external frequency generator 128, instead of the conventionally used quartz oscillator 126.
  • B. of the type Stanford DG 245 is used instead of the quartz oscillator on the printed circuit board is arranged on which the control chip for controlling the screen is arranged.
  • this frequency-modulated output signal of the generator 128 can be used as the input signal or system clock sys_clk for the phase-locked loops 108 and 116.
  • a quasi-decorrelation of the clock signals ppl_clk and mpll_clk generated by the phase locked loops 108 and 116 (ppll, mpll) is achieved with respect to the sampling clock of the analog input signal (avi_clk).
  • the systematic limits of the parameters to be selected depend on the one hand on the dynamic control properties of the phase locked loops 108 and 116 and on the other hand on the frequency tolerance of the connected units, that is to say the connected monitor and the memory. This means that even with a maximum frequency deviation due to the frequency modulation, secure data transfer to the connected units must still be guaranteed.
  • compliance with the restrictions applied for the synthesis of the digital blocks must also be observed in order to avoid timing problems within the blocks and above all at the interfaces between the clocks (clock domains).
  • the determination of the parameters to be selected for frequency modulation is very complex theoretically, because in reality not only the fundamental frequencies, but also all harmonic components and the dynamic properties of all components overlap and lead to complex time and frequency behavior.
  • the parameters for frequency modulation are preferably determined empirically for each combination of input mode / application. Based on the determined Values are then set according to a desired mode.
  • the frequency-modulated system clock is generated internally; H. in the control unit, namely on the chip. 5 shows a circuit for the internal generation of frequency modulation.
  • the commonly used external quartz oscillator 126 located on the circuit board is maintained to provide the system chip sys_clk to the control chip.
  • a divider controller 132 (divider controller) is also provided, which via a first control bus 134 with the first pre-divider 104, via a second control bus 136 with the second pre-divider 112 third control bus 138 is connected to the first feedback divider 110 and via a fourth control bus 140 to the second feedback divider 118.
  • the implementation shown in FIG. 5 is a more elegant and technically incomparably easier implementation of the decorrelation by means of an “on-chip” frequency modulation compared to the implementation described with reference to FIG. 4.
  • the starting points for frequency modulation on which the example is based are the pre-dividers 104 and 112 used in the phase-locked loops 108 and 116 as well as the feedback dividers 110 and 118.
  • the division value of each of the pre-dividers 104 and 112 and the feedback divider is controlled by the divider control 132 modified by means of a suitable algorithm or a programmable pseudo-random generator in order to obtain the time and frequency behavior described above.
  • the divider controller 132 includes a scan controller, a programmable counter / divider, and a random number generator.
  • the accuracy of the pre-dividers 104, 112 is important for the result of the frequency modulation, it being important to note that the smallest frequency step ⁇ f step to be set thereby is carried out by the feedback divider 110, 118 (n div ) of the phase locked loop 108, 116 is transformed up again.
  • the size of the frequency step to be effectively achieved with the pixel clock ppll_clk or with the memory clock mpll_clk the same applies to the circuits:
  • ⁇ f step ⁇ f n * n d iv / n pred i V ,
  • a problem with the variation of the frequency dividers is the fact that in principle these are counters that are programmed to a specific end value and deliver an output pulse when this end value (threshold) is reached. Reprogramming and thus modulation of the input frequency of the phase locked loops can thus only take place when the counter overflows. Due to the dynamic behavior of the phase locked loops, however, there is a more or less continuous change in the output clock signals or the output frequencies mpll_clk, ppll_clk. For this reason, it is also not necessary to realize a high resolution in increments ⁇ fs c HRIT t, since the intermediate areas are already run continuously from the phase-locked loops.
  • the implementation of the second exemplary embodiment for implementing the method according to the invention is much easier than when the frequency-modulated signal is generated externally, but the timing of the phase-locked loop is also decisive here. Since the pre-dividers are already present in existing circuits and designs, the method according to the invention can be implemented and verified with little effort (divider logic and control).
  • a third, preferred exemplary embodiment for implementing the frequency modulation required for the decorrelation is the use of an alternative phase locked loop concept.
  • EMI minimization interference radiation minimization
  • FIG. 6 shows the difference between a normal phase locked loop (normal PLL) and a spread spectrum phase locked loop (Spread Spectrum PLL).
  • normal PLL normal phase locked loop
  • Spread Spectrum PLL spread spectrum phase locked loop
  • the spread spectrum PLL generates set to the normal PLL output signals over a predetermined frequency range, whereas the normal PLL only provides a single output frequency depending on the input frequency.
  • the clock signals can also be realized here by the decorrelation methods according to the invention described above.
  • control units are particularly suitable, e.g. B. SAA6714, with the possibility to save the data in a memory and thus evaluate it statically.
  • a corresponding test setup is therefore described below and the results of the decorrelation obtained therefrom, with external feeding of the frequency-modulated system clock, are then presented.
  • test setup included the following devices and components:
  • LG Philips panel 18 inch, model LM181E1, SXGA resolution, Deutronic Power Supply 12V / 5A, model DTP60
  • the behavior of an LCD controller as described with reference to FIG. 8 was examined.
  • the output of the external frequency generator serves as a reference signal for the memory clock and the screen clock (pixel clock), as described above.
  • Frequency modulation on the external generator leads to frequency modulation of the memory clock or of the screen clock, which is determined by the dynamic behavior of the respective phase locked loop.
  • the interference pattern that occurred at 25,000.004 Hz system clock.
  • a sweep rate of 25 Hz, a swept frequency range of 7777 Hz and a sine function as the modulation frequency g (t) were chosen, and with these settings on the function generator a very good result was achieved in which the interference lines for the human eye were not were more visible.
  • the method according to the invention is preferably carried out using a random modulation, since there is the possibility that the frequency modulation itself generates a new interference pattern which is complex in its formation. Since this behavior is to be expected above all with continuous modulation functions, the simulation results with the discrete model show that random modulation is the cheaper variant of frequency modulation.
  • the method according to the invention has shown both in the model and in reality that this can effectively mitigate or make invisible interference phenomena in LCD control units by means of the described quasi-decorrelation of the clock signals.
  • all interference signals on the chip or on the circuit board can be manipulated in the same way as the signals ppll and mpll, so that the present invention is not restricted to these clock signals, but rather is generally applicable to all clock signals.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne une unité de commande et un procédé pour réduire un modèle d'interférence lors de l'affichage d'une image sur un écran au moyen d'une fréquence de pixels (ppll_clk). L'image est représentée par des données pixels et fournie à l'écran par une unité de commande. Pendant la création des données pixels, les signaux d'horloge utilisés pour cette création de données pixels sont modifiés ou bien la fréquence des pixels est changée.
EP03793774A 2002-09-06 2003-08-29 Unite de commande et procede pour reduire des modeles d'interferences lors de l'affichage d'une image sur un ecran Expired - Lifetime EP1535274B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10241343 2002-09-06
DE2002141343 DE10241343A1 (de) 2002-09-06 2002-09-06 Steuernheit und Verfahren zum Reduzieren von Interferenzmustern bei der Anzeige eines Bildes auf einem Bildschirm
PCT/EP2003/009633 WO2004023452A1 (fr) 2002-09-06 2003-08-29 Unite de commande et procede pour reduire des modeles d'interferences lors de l'affichage d'une image sur un ecran

Publications (2)

Publication Number Publication Date
EP1535274A1 true EP1535274A1 (fr) 2005-06-01
EP1535274B1 EP1535274B1 (fr) 2007-01-24

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EP (1) EP1535274B1 (fr)
JP (1) JP4410677B2 (fr)
CN (1) CN100405457C (fr)
AU (1) AU2003264136A1 (fr)
DE (2) DE10241343A1 (fr)
TW (1) TWI250505B (fr)
WO (1) WO2004023452A1 (fr)

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JP2005538397A (ja) 2005-12-15
TW200415566A (en) 2004-08-16
DE10241343A1 (de) 2004-03-25
EP1535274B1 (fr) 2007-01-24
CN100405457C (zh) 2008-07-23
JP4410677B2 (ja) 2010-02-03
AU2003264136A1 (en) 2004-03-29
CN1679080A (zh) 2005-10-05
WO2004023452A1 (fr) 2004-03-18
TWI250505B (en) 2006-03-01
DE50306395D1 (de) 2007-03-15

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