200415566 坎、發明說明： t务明所屬之技術領域】 本發明係關於_ #田.、，t 於種用以控制螢幕之控制單亓另t i各 此特定言之侍關於絲m 早凡及方法，在 案之控制單元及方法心圖像的干擾圖 寺疋δ之，本發明係關一 TFT/LCD螢慕夕古土 u仏 種用於 瓦辱之方法及控制單元。 【先前技術】 咸？：個信號的複雜系統，顯示隨著圖案尺寸的不斷 減小而在數位與類比組件之間漸增的互動。該實際情況在 將數個時脈信號(時脈域)集成於一晶片上以及針對數位資 料處：錢比資料獲取使用類似頻率的系統中是嚴重的。 特定言之，在圖形應用中，該類互動以該輪出圖像中的 干擾圖案的形式顯示，以下將關於—TF丁/LSD勞幕（丁打=200415566 Description of the invention: The technical field to which Wuming belongs] The present invention relates to a control list for controlling the screen, and other specific instructions on the subject. In the control unit and method of the document, the interference image of the image is δ, and the present invention relates to a method and a control unit for humiliation of a TFT / LCD screen. [Prior art] Salty? : A complex system of signals, showing increasing interaction between digital and analog components as the pattern size continues to decrease. This reality is severe in systems where multiple clock signals (clock domain) are integrated on a chip and digital data: money-to-data acquisition uses similar frequencies. In particular, in graphic applications, this type of interaction is displayed in the form of interference patterns in the revolving image. The following will be about —TF 丁 / LSD 劳 幕 (丁 打 =
Thin Film Transist〇r(薄膜電晶體）；LCD = Liquid Crystal Display(液晶顯示器））對此作更詳細的討論。 為將TFT/LCD螢幕連接至共同圖像來源（例如至圖形 卡· VGA、DVI以及並聯埠（pc>個人電腦；VGA=^訊圖形 配接卡；DVI =數位視訊輸入），需要]1(：1)控制單元，其獲取 不同的輸入資料並將之轉換為數位RGB資料（RGb =紅、綠 、藍）並以個別螢幕類型所需的波形（像素頻率）將之輸出。 圖8顯示一傳統LCD控制晶片800之一簡化方塊圖。該控 制晶片800接收來自不同輸入來源802、804及806的輸入信 號。該示意性說明的信號來源802提供類比視訊輸入信號 (Analog Video lnput ; avi)。該信號來源804提供數位視訊 87792 200415566 輸入信號（Digital Video Input ; DVI)。該信號來源806提供 平行視訊輸入信號（Parallel Video Input ; PVI)。由該等輸 入來源802至806提供給該控制晶片800的輸入信號應用於 一輸入選擇單元808，該單元選取欲處理的輸入信號並將其 提供給該控制晶片800之一輸入810。將提供於輸入810處的 信號提供給包含一「先進先出」記憶體（First In First Out ;FIFO)與一記憶體元件之一處理單元812。與該處理構件 8 12相關聯的記憶體連接至一記憶體介面814 (Memory Interface ; MI)。該處理單元812經由一輸出814及該輸出介 面816向螢幕輸出欲顯示於具有一像素頻率ppii—cik之螢幕 上的像素資料。該控制晶片800進一步包含由一系統時脈 sys—elk驅動的一配置區塊818。 在該處理單元8 12，該等信號應用於該時脈fclk，該時脈 與自該等輸入來源 802至 806 (DVI_clk、AVI一elk、PVI—elk) 獲取的輸入信號之時脈相對應。 如圖8中之說明，除了該等輸入來源（AVI—cik，DVI_clk ，PVI 一 elk)的不同時脈（時脈域）以外，依據控制單元的類型 ，在該控制晶片800上提供用於該記憶體介面814 (mpll_clk) 與该螢幕介面818 (ppll_clk)之其他時脈（域）。進一步，提 供έ亥糸統時脈s y s c 1 k。 例如，圖8中顯示的控制晶片800，係置放於一印刷電路 板上，並接收例如由一電腦所提供之用於在螢幕上呈現及 顯示的視訊或圖形信號。 5亥類控制單元的問題是，該時脈信號經由該控制晶片8 0 0 87792 200415566 的基板耦合為該控制晶片之一或數個輸入並覆蓋所應用的 信號。因此，干擾性的干擾圖案便產生於螢幕上的顯示資 料中。下面將關於接收於該類比輸入的信號對此問題進行 說明。 就A &制晶片8 〇 〇之不同輸入而言，應注意，理論上說， 該DVI輸入804可受到經由該晶片之基板的其他時脈信號 (時脈域）的干擾，但是，基於簡單明瞭考量，以下說明僅 限於作為干擾吸收器的類比輸入802 (AVI)，其中將該記憶 體及螢幕時脈信號mpll-Clk&ppll-Clk視為干擾來源，其經 由通常具有一低阻抗的控制晶片800的基板耦合為該類比 輸入AVI 〇 LSCD控制單元中之干擾的最簡單情形在實務中經常發 生，即一干擾信號内部耦合為分別具有該螢幕時脈ppl匕 elk(像素頻率）之頻率以及該時脈之較高諧波的類比視訊輸 8 02 (AVI)。5亥干擾彳§號如何產生及其如何進入該晶片8〇〇 的低阻抗基板，有數種可能。除在該核心中的數位邏輯之 外，可將該輸出介面8 1 8的輸入/輸出驅動器視為該等基板 電壓的主要來源。 圖9顯不圖8的螢幕介面或輸出介面818之一等效電路圖。 在圖9的左邊部份（虛線左側），說明該記憶體晶片之元件， 而在該虛線右側說明該電路板之元件。 忒介面在該驅動器級822處從輸出8 1 6接收欲顯示於螢幕 上的像素信號，其具有該螢幕像素頻率ppU—clk。在所說明 的4範例中，泫驅動器級822包含一第一場效電晶體822a 87792 200415566 以及一第二場效電晶體82213。該驅動器級822的輸出連接至 。玄捡制曰曰片800之一墊，其中，該墊具有一對抗基板接地之 阻抗，忒阻抗具有一歐姆部份與一電容部份，圖9中以電阻 器Ri與電谷C!對此作了說明。該控制晶片8〇〇經由一焊接導 ，連接至-外设’以將該控制晶片之—塾連接至該晶片外 殼之一墊。在圖9中，顯示該焊接導線的阻抗之電感部份^ 與歐姆部份R2。 此外，δ亥墊以及該控制晶片經由該焊接導線所連接的外 设之阻抗的電容、電感及歐姆部份，顯示為電阻器R3、電 感L2以及電容(^與c3。 在4私路板上提供一傳送線TL，其將自該控制晶片輸出 的信號輸出至另一驅動器級，該驅動器級再將該信號繼續 傳遞給該螢幕。與該驅動器級822類似，該驅動器級824包 含一第一場效電晶體824a與一第二場效電晶體824b。進一 步’以該電容C4說明該驅動器級824的外殼之一電容。 進一步，圖9中，說明與該電感]^相關的該電壓UL(t)，該 電壓橫跨該電容而下降。如以上所討論，該等基板電壓的 主要來源之一係該螢幕介面的輸入/輸出驅動器級822之輸 出信號。該介面橫跨該等焊接導線與該等墊的電感L i、L2 及電阻器Ri、R2、R3而產生非常陡的信號（高di/dt)。由此 引起的情況是，高達數百mV (uL (t))的電壓可下降於該等焊 接導線上，由該驅動器配置而使得該等焊接導線直接或間 接地耦合於該控制晶片800之基板内。 在έ亥控制晶片8 0 0的類比輸入處的干擾 < 另一來源可以 -9- 87792 200415566 是集中或供應電壓干擾(反彈)，其係由該數位核心内的一 控制晶片i之1或遺_解♦禺纟或由供應該供應電壓 (功率輸送）之線的一不充分引導而引起。 “ 二情形中的可見效果很類似，由於該類比電路的不充分 免疫性(功率供應漣波去除、接地及基板雜訊解耦合)，此 等效果可見於下列形式：高頻率準雜訊信號（具有高干擾頻 率 finterf « avi—clk、窄對角條帶與線形式（1/2 avi_cik > 2 或者低頻率、較低或較高亮度的水平對齊條帶 的形式（fhoriz_i 2 finterf 2 fvertieal)。 螢幕上可見干擾的出現取決於與該輸入時脈相關而設定 於遠控制曰曰曰片800上的頻率，其中個別輸人格式（活動區域 、空白等）具有重要作用。 圖10A中，說明了該類干擾圖案之一範例，其模擬用於具 有以一 〇模型為依據的一螢幕介面之一 LCD控制單元。圖 1〇a中說明的該干擾圖案之波形大都與將在一實際LCD控 制單元中觀察到的波形相對應。 至此’僅考慮到具有一螢幕介面的LCD控制單元。此外 ’存在亦具有該記憶體介面8丨4的LCD控制單元，例如參考 圖8所說明者。原則上，應用與以上同樣的考慮，但在具有 外部記憶體的LCD控制單元中，除該螢幕介面以外，在該 控制晶片800上存在用於該記憶體介面的明顯較強的驅動 為輸入/輸出。提供用於該記憶體介面的該些較強驅動器係 明顯用於該考慮，並不僅因為其對該基板的影響。一般地 ’藉由一不同而且通常比在該螢幕介面中更高的一時脈來 87792 -10- 200415566 對板跨該記情、p ’藉由該,；；面的資料計時。像在該勞幕介面中-樣 感電麼1其信號（高峨）橫跨該等悍接導線產生電 因此，實Ρ上在°於5亥基板並能由此影響該等類比電路。 其大約在：所二基板上有至少二個頻率之-頻率混合， avi ,, , π 慮的輸入來源8〇2的信號之輸入頻率 aVI-cik相同的範圍内。 貞羊 如果對二個頻率# 圖案之-重如圖1G时心，二干擾 非該諸波頻率部份，/考U該4基礎頻率而 ， ，、自身曰導致一不同的干擾圖案。 成作l將對根據圖1GA與刚所討論的干擾圖案之形 5手細的考慮。在該干擾圖案的形成中，將以下所說 明的簡化機制作為一依據。從—降 :^ ^ 具I不入GA (XGA =擴充圖形 見卡）輸入模式開始，藉由考慮該設定的像素頻率（僅該 基礎頻率)’由計算得出所產生的干擾圖案並進行圖形說明 。假定以下條件供以下之考慮： 輸入模式： 78.75 MHz XGA1024 X 768，在頻率為 75 & 水平後沿：176像素 水平前沿：112像素 垂直後沿：28線 垂直前沿：4線 螢幕設定： XGA1024 X 768 87792 -11 - 200415566 像素頻率：66 MHz 據此’該干擾頻率finterf首先計算為： fThin Film Transistor (LCD; Liquid Crystal Display) discusses this in more detail. To connect a TFT / LCD screen to a common image source (for example, to a graphics card · VGA, DVI, and a parallel port (pc >PC; VGA = ^ graphics graphics adapter card; DVI = digital video input), you need) 1 ( : 1) The control unit takes different input data and converts it into digital RGB data (RGb = red, green, blue) and outputs it with the waveform (pixel frequency) required by the individual screen type. Figure 8 shows a A simplified block diagram of one of the conventional LCD control chips 800. The control chip 800 receives input signals from different input sources 802, 804, and 806. The illustrated signal source 802 provides an analog video input signal (Analog Video Input; avi). The signal source 804 provides digital video 87792 200415566 input signal (Digital Video Input; DVI). The signal source 806 provides parallel video input signal (Parallel Video Input; PVI). The input sources 802 to 806 provide the control chip 800 The input signal is applied to an input selection unit 808, which selects an input signal to be processed and supplies it to one of the control chips 800, input 810. Will be provided The signal at the input 810 is provided to a processing unit 812 including a "first in first out" memory (FIFO) and a memory element. The memory associated with the processing component 8 12 is connected to a A memory interface 814 (Memory Interface; MI). The processing unit 812 outputs pixel data to be displayed on a screen having a pixel frequency ppii-cik to the screen via an output 814 and the output interface 816. The control chip 800 further includes A configuration block 818 driven by a system clock sys_elk. In the processing unit 812, the signals are applied to the clock fclk, and the clock is from the input sources 802 to 806 (DVI_clk, AVI- elk, PVI-elk) corresponds to the clock of the input signal. As illustrated in Figure 8, except for the different clocks (clock domain) of these input sources (AVI-cik, DVI_clk, PVI-elk), According to the type of the control unit, other clocks (domains) for the memory interface 814 (mpll_clk) and the screen interface 818 (ppll_clk) are provided on the control chip 800. Further, a clock sysc 1 is provided. k. For example, the control chip 800 shown in FIG. 8 is placed on a printed circuit board and receives, for example, a video or graphic signal provided by a computer for presentation and display on a screen. The problem with the 5H type control unit is that the clock signal is coupled to one or more inputs of the control chip via the substrate of the control chip 8 0 87792 200415566 and covers the applied signal. Therefore, noisy interference patterns are generated in the display data on the screen. This problem is explained below with respect to the signals received at the analog input. With regard to the different inputs of A & chip 8000, it should be noted that, in theory, the DVI input 804 may be interfered by other clock signals (clock domain) via the substrate of the chip, but based on simplicity For the sake of clarity, the following description is limited to the analog input 802 (AVI) as an interference absorber, in which the memory and the screen clock signal mpll-Clk & ppll-Clk are regarded as the source of interference, which is usually controlled by a low impedance The simplest case of the interference of the substrate coupling of the chip 800 in this analog input AVI LSCD control unit often occurs in practice, that is, an interference signal is internally coupled to a frequency having the screen clock ppl kelk (pixel frequency) and The analog of the higher harmonics of this clock is 8 02 (AVI). There are several possibilities for how the Hai Hai interference 彳 § number is generated and how it enters the low-impedance substrate of the chip 800. In addition to the digital logic in the core, the input / output driver of this output interface 8 1 8 can be regarded as the main source of voltage for these substrates. FIG. 9 shows an equivalent circuit diagram of one of the screen interface or the output interface 818 of FIG. 8. In the left part (left side of the dotted line) of FIG. 9, components of the memory chip are described, and on the right side of the dotted line components of the circuit board are described. The interface receives the pixel signal to be displayed on the screen from the output 8 1 6 at the driver stage 822, which has the screen pixel frequency ppU-clk. In the four examples illustrated, the ytterbium driver stage 822 includes a first field-effect transistor 822a 87792 200415566 and a second field-effect transistor 82213. The output of this driver stage 822 is connected to. One of the pads of the 800 chip, which has an impedance against the ground of the substrate, and the impedance has an ohmic part and a capacitive part. In Figure 9, the resistor Ri and the electric valley C are used for this. Clarified. The control chip 800 is connected to a peripheral device via a solder guide to connect the control chip to a pad of the chip case. In FIG. 9, the inductance part ^ and the ohmic part R2 of the impedance of the bonding wire are shown. In addition, the capacitance, inductance, and ohmic portions of the delta pad and the impedance of the peripherals connected to the control chip via the solder wire are shown as resistor R3, inductance L2, and capacitance (^ and c3. On 4 private circuit boards A transmission line TL is provided, which outputs a signal output from the control chip to another driver stage, which in turn passes the signal to the screen. Similar to the driver stage 822, the driver stage 824 includes a first A field-effect transistor 824a and a second field-effect transistor 824b. Further, a capacitor of the casing of the driver stage 824 is described with the capacitor C4. Further, in FIG. 9, the voltage UL () related to the inductor is illustrated. t), the voltage drops across the capacitor. As discussed above, one of the main sources of the substrate voltage is the output signal of the input / output driver stage 822 of the screen interface. The interface spans the solder wires and These pads' inductors Li, L2 and resistors Ri, R2, R3 produce very steep signals (high di / dt). The resulting situation is that voltages up to several hundred mV (uL (t)) can be Down on these soldered wires, The driver is configured such that the solder wires are directly or indirectly coupled into the substrate of the control chip 800. The interference at the analog input of the control chip 800 is another source-9- 87792 200415566 is concentrated Or the supply voltage interference (rebound), which is caused by a control chip i in the digital core or a solution, or caused by an insufficient guidance of a line supplying the supply voltage (power transmission). The visible effects in the two cases are similar. Due to the inadequate immunity of the analog circuit (power supply ripple removal, grounding, and substrate noise decoupling), these effects can be seen in the following form: high-frequency quasi-noise signals (with High interference frequency finterf «avi-clk, narrow diagonal strip and line form (1/2 avi_cik > 2 or low frequency, lower or higher brightness horizontally aligned strip form (fhoriz_i 2 finterf 2 fvertieal). The appearance of visible interference on the screen depends on the frequency set on the remote control chip 800 in relation to the input clock. Individual input formats (active areas, blanks, etc.) have important effects. An example of this type of interference pattern is illustrated in FIG. 10A, which is simulated for an LCD control unit having a screen interface based on a 10 model. Most of the waveforms of the interference pattern illustrated in FIG. 10a Corresponds to the waveform that will be observed in an actual LCD control unit. So far, 'only considers the LCD control unit with a screen interface. In addition, there are LCD control units that also have the memory interface 8, 4 for example, refer to the figure 8. Explained in principle. In principle, the same considerations as above are applied, but in the LCD control unit with external memory, in addition to the screen interface, there is significantly stronger on the control chip 800 for the memory interface. The drive is input / output. The stronger drivers provided for the memory interface are clearly used for this consideration, not only because of their effect on the substrate. In general, ‘with a different and usually higher clock than in the screen interface, 87792 -10- 200415566 against the board across the memory, p’ with the time of the data. As in the interface of this screen-the sense of electric power 1 whose signal (high) generates electricity across these hard-connected wires. Therefore, the actual P is on the substrate and can affect such analog circuits. It is approximately: there are at least two frequency-frequency mixtures on the two substrates, and the input frequency aVI-cik of the signal of the input source 802, avi ,,, π is within the same range. If the frequency of the two frequency # patterns is as shown in Figure 1G, the two interferences are not the frequencies of the waves, and the 4 fundamental frequencies of the four frequencies will cause a different interference pattern. Production l will carefully consider the shape of the interference pattern according to Figure 1GA and just discussed. The formation of this interference pattern is based on the simplified mechanism described below. Starting from-Descending: ^ ^ With I not in GA (XGA = extended graphics see card) input mode, by taking into account the set pixel frequency (only the base frequency) 'interference pattern generated by calculation and graphical description . The following conditions are assumed for the following considerations: Input mode: 78.75 MHz XGA1024 X 768, at a frequency of 75 & horizontal trailing edge: 176 pixels horizontal leading edge: 112 pixels vertical trailing edge: 28-line vertical leading edge: 4-line screen setting: XGA1024 X 768 87792 -11-200415566 Pixel frequency: 66 MHz Based on this, the interference frequency finterf is first calculated as: f
Mnterf: 78·75 MHz-66 MHz = 12.75 MHz 〇 據此’可就每一輸入線計算於該類比視訊輸入（活動區域 +空白）的干擾數量，其結果為： mterf/線=(78.75/1 2.75)·1 * 1312 = 212.4190 因此’該干擾之最大/最小值週期性地發生並具有以下間 距： linterf= 1312/212.4190 …=6.1764 …像素 以及 分別為 tinterf= (78.75 MHz)-1 * 6，1764··· = 78.43 13··· ns。 如果假定在該第一圖框中（frarne ;f=1)，選取第一線（n=1) ，起點t=〇s，則在該第六與第七像素之間而且各在78·43ι3 ns後可以分別先看見該干擾之一最小/最大值，並且自此以 後，週期性地可見直至該線末尾。由於該干擾週期一般不 作為一整數而恰好適於一輸入線，因此在每一線之末尾留 下一餘數。（interf/線）*n與下一整數之差則係用於下一條線 n+1的個別起始值。隨著每一條線的個別起始值之偏移，形 成一對角線圖案，其中應用以下： 餘數{interf/line} < 0.5 —對角條 \\\\\\\ 餘數{interf/line} > 0.5 —對角條 /////// 87792 200415566 累積於最後一條線之在（interf/line)* ^以的小數點後的 值決定該後續圖框（f+ 1)中該干擾的起始值，其中在大多數 情況下’發生該等對角線之一向上或向下偏移。結果是， 視該螢幕的垂直頻率而定，在一方向上橫跨該原始圖像行 進之一移動對角線。在固定頻率比率中，在該移動方向上 的表觀速度是不變的並僅取決於該干擾頻率以及於該類比 視訊輸入處的輸入信號之波形。 參考圖11再次以圖示總結產生該干擾圖案的以上說明。 特定言之，該起始值的固定係說明用於後續線以及後 框。 、 上實際上’該干擾形成的機制更為複雜，因為不僅所有的 諧波頻率部份，而且在該控制晶片上的所有組件以及該等 外部元件(例如在該控制晶片上的鎖相迴路、該等輸入” ，源等)之動態行為，都起了重要作用，但是原則上，卻： 能在此計算出所產生的干擾。 由於上述機制所產生的螢幕上相關干擾圖案，對於 用者/觀察者來說是可見的並因而具有干擾性。 【發明内容】 此，本發明之目的是提供一種避免 擾之方法及控制單元 第由如申請專利範圍第1項之方法，以及如申請專利| 第9項之設備可達到此目的。 本發明提供一種減少具有一 的工4益门一 1豕京頻率之螢桊上顯示国 的干擾圖案之方法，立中可以山 八中了以由一控制單元提供給該| 87792 -13 - 200415566 的像素資料來說明該圖像，#中在該像素f料產生過程中 ，可變動用於產生該等像素資料的時脈信號之一或數個。 【實施方式】 依據一項具體實施例，本發明提供—種減少具有一像素 頻率之螢幕上顯示圖像的干擾圖案之方法，其中可以由二 控制單元提供給該螢幕的像素資料來說明該圖像，其中在 該像素資料的產生過程中，該像素頻率改變。 進一步，本發明提供用於控制以一像素頻率運作之螢幕 之一控制單元，以便在螢幕上顯示具有已減少干擾圖案之 圖像。該控制單元包含用於接收圖像資料的一輸入，一處 理單元（其處理所接收到的圖像資料以產生該等像素資料 ’其中在該等像素資料產生過程中’該處理構件變動用於 料像素資料之產生的-或數㈣脈信號）以及提供像素 資料以供顯示之一輸出。 依據-具體實施例’本發明進一步提供用於控制以一像 素頻率運作之登幕之-控制單元，以便在營幕上顯示具有 已減少干擾圖案之圖像。該控制單元包含用於接收圖像資 料之一輸入’一處理構件(其處理所接收到的圖像資料以產 生該等像素資料’以在該等像素f料產生過程中，該處 理構件改.變該像素頻率）以及提供像素資料以供顯示之一 輸出。 之控制單元引起在該控制晶片上 由此破壞典型的干擾圖案並因此 本發明之方法及本發明 该專時脈比率之一操作， 使之幾乎不可見。 87792 -14- 200415566 本^明所依據的知識係’一剛性頻率比率以及一固定的 輸入信號波形分別是該等干擾圖案與該等干擾圖像形成的 原因。如果不再可能單獨藉由該等類比組件之一適當設計 來避免a玄等可見干擾’則在該晶片上的頻率比率係用以解 決與干擾圖像相關的問題之起點。 一般地’在破壞所使用頻率之相關性以及剛性比率中分 別能見到該發明步驟，如此使得在一圖框内或在後續圖框 内不能發生規則的干擾圖案。依據一較佳的具體實施例， 對該等頻率的相關性及剛性比率之破壞，分別藉由依時間 而定的頻率調變而發生。 因此，一般在一與五最低有效位元（Least Significant Bit ;LSB)之間的干擾仍然存在，但肉眼僅可見該圖像中略不 規則的雜訊，因此而具有小得多的干擾性。 依據一第一具體實施例，由一時間連續頻率調變實現依 時間而定的頻率調變（frequency m〇dulati〇n，fm)。依據另 一具體實施例，由一時間離散頻率調變實現一依時間而定 的頻率調變。 依據一第二較佳具體實施例，一控制晶片的頻率調變係 由一外部頻率來源實行，或者，依據另-具體實施例，由 實現於該晶片上的一内部頻率來源來實行。 依據一第三較佳具體實施例，藉使用該（等）展頻鎖相迴 路實行該頻率調變。 在申請專利範圍之附屬項中定義本發明之較佳進展。 在該等較佳具體實施例的以下說明中，圖式中相 | 口J、看 -15- 87792 200415566 似相同或相似的元件具有相同的參考符號。 依據上述干擾形成之簡單模型，以下說明發明步驟、方 法及設備，藉此可避免或抑制可見並因而具有干擾性的干 擾之形成。 在此，應注意，將以下所述的方法 '步驟及設備視為附 加於在相關的類比電路零件及整個系統（印刷電路板、晶片 、應用）中必須採取的措施，以減小對雜訊的敏感度以及不 需要的基板及集中電壓。因此，最好將本發明應用於已充 分發展並具有相關干擾非敏感性之一類比操作行為之系統。 如以上所述，依據本發明之一較佳具體實施例，藉由實 現一依時間而定的頻率調變（frequency m〇dulati〇ii FM)以 獲得像素頻率的變化來避免干擾圖案，該頻率調變分別破 壞該等頻率的相關性及剛性比率，如此使得當内部耦合該 等干擾頻率時，該等干擾圖案得到減少或抑制。 依據一第一具體實施例，藉由以一適當速率穿過一頻率 區域Μ的一時間連續頻率調變，例如藉由一頻率擺動輪的 作用，來實現該依時間而定的頻率調變，其由在該螢幕與 該記憶體所需的基礎頻率（f())左右的一調變函數分別固 定。 假定所需的時脈信號係藉由鎖相迴路（phase locked lQQps ;PLL)而產生於該控制晶片上，對於該等鎖相迴路的輸入 頻率fXPmn⑴，下式成立： fxpllin(t) = f〇 + Af * g (t) 87792 -16 - 200415566 及： f〇 該螢幕之基礎頻率（像素頻率）或 率 該記憶體之基礎 頻 △f —在该基礎頻率左右的頻率範圍 g(t)=調變函數 該調變函數g⑴可以是一任意的連 1 P丄 、山要文，例如圖I A 5 1 C中所說明的函數，直中一 ^ ^ ，、 又亚不產生對所使用的函數之 形成與實現的限制。 口數之 在此所說明的頻率調變的時間連續情彤中所 、 擾圖案將在每一線並因而在每一個別圖框内連續改J的： 當對該函數g⑴及該參數轉出適當衫時，可能由原先相 關的干擾圖案產生一看似不相關的白色(準)雜訊。 在本發明之另一較佳具體實施例中，使用一更 間離散頻率調變以取代—般非常昂責的用於時間連續頻率 调變的上述步驟，其產生類似的結果，但就實現方面而言 ，其具有明顯的優點。 ° 在該具體實施例中，欲調變的頻率fxpiiin(k)並不連續變化 ’而視藉由圖框或藉由線之實施方案而定。進一步，可選 取-任意的適時的決^。如同在該時間連續頻率調變中^ 經由-適當的隨機產生器’該頻率可連續或任意而不稃定 地變化’其能實現「白色」（準)雜訊之-更有效產生： 在該具體實施例中，對於該鎖相迴路配置的輸入頻率， 下式成立： -17- 87792 200415566 fxpllin⑴=f〇 + Af * g(k) 及： f〇 =該螢幕之基礎頻率（像素頻率）或該記憶體之基礎頻 率 △ f =在該基礎頻率左右的頻率範圍 g(k)=時間離散調變函數 k =運行指數 每當滿足一頻率變化之一預定條件時，該運行指數k便增 加1 ’例如發生一線或一圖框變化或類似者，其表示分別到 達-新的線及一新的圖框。在圖2八至。中，說明該時間離 散調變頻率g(k)之範例，但是其中，纟此應注意，在欲使 用的離散函數方面一般並無限制。 如上述第一具體實施例，藉由適當選擇該函數g(k)、該 ㈣條件及該參數M，結果可為—「白色」（準）雜訊，: 在最佳情況下不可見或僅微弱可見。 就上述具體實施例而言，一般應注意，藉由適當決定含 調變條件，能夠極為靈活地使用上述二種用以產生該依; :而：的頻率調變之方法，以使本發明之方法可適用於巧 =的％ i兄條件，此舉的必要性係起因於複數個可能的輸^ 模式與輸入頻率。 、I面對時脈信號在一控制晶片上的產生及分佈作更詳細 =兄明’如根據圖8對之所作的說明，隨後，依據此討論内 -來說明在LCD螢幕的控制晶片中實施本發明方法的具體 87792 -18- 200415566 實施例。 圖3中說明在控制晶片上產生時脈所需的單元之一方塊 圖。如圖3之示意圖中所見’其所顯示的切換元件係用於產 生該記憶體時脈mpll一elk及該像素時脈ppU—clk。該電路包 含一多工器100，其於一第一輸入接收一水平同步信號（HS ;H_Sync)。於一第二輸入’該多工器100接收一外部振盡 器時脈sys—clk。依據一驅動信號，該多工器選取該等一輸 入之一作為輸入信號以產生該像素時脈ppU一dk。經由線 102將由該多工器100所選取的輸出信號提供給一預除法器 104(nprediV)’其中經由另一線106將由其產生的一輸出作赛 |^供給一鎖相迴路108之輸入’其在一内部除法器〖〖ο ) 的控制下於該輸出處提供該像素時脈ρρΠ 一 Clk。進一步，將 該外部振盈器時脈sys一elk提供給另一預除法器112 (n ) ，遠預除法裔於其輸出處經由線114將一輸出信號輸出至該 鎖相迴路116。該鎖相迴路116由一内部控制U8 (ndiv)驅動 並於該輸出處將該記憶體時脈1111311一()1]^輸出。 進一步，圖3中顯不用於運作該暫存器（圖8中所顯示的配 置暫存器)的時脈’ rclk等同於該系統時脈或外部振盪器時 脈 sys一elk 〇 進一步，說明該輸入時脈avi 一 Clk經由另一鎖相迴路12〇 與一下游相位延遲迴路〖Μ而自^亥水平同步信號HS (synchronization signai)產生’亦將其提供給一取樣器i24 用於該AVI信號的獲取及數位轉換。 圖3所示的示意性電路圖是用於具有外部記憶體之一 87792 -19- 200415566 LCD控制晶片用以產味 座生時脈之一控制單元，其一般具有至 少四個在一定時問相$ 互關聯變化的不同時脈（時脈域）。進 一步，依據圖3，鞀+田# 、…、用於該時脈產生之一配置，在後來的 實施及應用中亦可發現該配置。 圖3中’概述該等四個 、 時脈及其產生，並且除了能將該類 比視訊輸入AVI的水孚R止，t ^十同步“號HS作為輸入信號的鎖相迴 路108 (llpll)以外，所右f 所有其他鎖相迴路均由該外部振盪器時 脈sys—elk驅動。 用於該控制晶片800的暫存器的時脈rcik並非關鍵。該時 脈般與該外部日守脈相同（rclk=sys—clk)，而且由於該等暫 存器在-般操作中係靜態的，因此其對該晶片的類比電路 不造成可見或可測之影響。 對於自該等相關聯的鎖相迴路108及116 (ppu、mpll)產生 的記憶體時脈mpll—clk及該螢幕時脈（像素時脈）ppU_dk， 情況就不同了。經由該些時脈信號，不僅該LCC^S制晶片 的很大數位區塊，而且個別輸入/輸出介面，即該記憶體介 面及該螢幕介面都得到計時。在二鎖相迴路中，均可將該 外部振盈器時脈用作輸入信號，並藉由程式化該等預除法 器104、112以及該等内部迴路除法器11〇、118，可在該产 出處設定該時脈信號的所需頻率。在該螢幕鎖相迴路中， 所選取的輸入之H-Sync信號，以及，在所說明的具體實施 例中，該類比視訊輸入的信號HS，可用作輸入信號作為々亥 外部時脈sys_clk之替代。 自圖3中所說明的該系統架構開始，下面將說明用於實施 87792 -20- 200415566 士述方法以作該等時脈之準分解的二項較佳具體實施例。 熟習本技術者從下述實施方案將明白，其他實施方 可能。 一’ 根據圖3，說明 弟一具 體實施例，其中由-外部來源饋 入已調變頻率的系統時脈。圖4顯示圖3所示用於產生該像 素蚪脈ppll—elk和記憶體時脈mpU一clk的電路元件之一部份 ，其中外部饋入系統時脈Sys—Clk選取為該鎖相迴路1〇8的輸 入信號以產生該像素時脈，因此基於簡單明瞭考量，在圖4 中省略圖3中所示的多工器1〇〇。 圖4中可見到，取代用於傳統LCD控制晶片的外部石英或 晶體振盪器126，現在使用一掃描產生器126以提供該系統 時脈sys一elk。此由130中的準振盪器126與預除法器1〇4及 112 (npre-div)之間斷開的連接所顯示。圖*中所說·明的具體 實施例是本發明之一簡單實施方案，其中在此使用一外部 頻率產生器128,例如Stanford DG 245之類，以取代一般所 使用的石英振盪器126,其取代該石英振盪器而置放於該印 刷電路板上，用於驅動該螢幕的控制晶片亦置放於此。如 設定該頻率產生器128，以與上述本發明之具體實施例相對 應而產生一已調變頻率的信號，則該產生器128之已調變頻 率的輸出信號可分別用作輸入信號及系統時脈sys — c Ik以用 於該等鎖相迴路108及116。藉由仔細選擇該等參數，可獲 得與該類比輸入信號（avi一elk)之樣本時脈相關的，由該等 鎖相迴路108及116 (ppll一mpll)所產生的時脈信號ppi_cik與 mpll—clk之一準分解。 -21- 87792 200415566 欲選取的參數之系統邊取 于死遺界方面，取決於該等鎖相迴 路1 0 8及11 6的動態相位特性 符性另一方面’取決於該等已連 接單元（指已連接的螢幕與記憶體）之頻率容限。這表示， 即使由於該頻率調變而處於—最大頻率偏離中’仍然必須 保證一安全資料傳遞至已連接罝 了心王G逆筏早兀。除此以外，在一強頻 率調變中，必須考yf庫用於^童令/ “應用於數位方塊合成的限度控制，以 避免在該等區塊及特定古之亦力兮堃 竹疋〇之亦在5亥荨區塊（區塊域）之間的 介面處的時序問題。 從理論上說，將選取用於該頻率調變的參數之決定是很 昂貴的’ ®為，實際上，不僅該等基礎頻率而且所有的諧 波部份以及所有組件的動態特性都重疊並導致一複雜的時 間及頻率行為1管能在理論上決定之’但對於輸入模式/ 應用的每一組合，最好採用經驗法決定用於頻率調變的泉 數。依據以此方法決定的值，按照一所需模式進行一嘹定^ 儘管剛剛說明的具體實施例對該外部頻率產生器提又供了 良好結果’但該具體實施例之-缺點是用於連接該外部頻 率產生器的成本及人力耗費太高。對於一後來的庫用，並 不需要使用-外部頻率產生器1此在一實際情況中，可 使用在該印刷電路板上的-簡化可程式/可初始化產生器 ，其代表一可能但亦不經濟的解決方法。 因此，依據·本發明之用於貫施本發明之方、、表 •乃 /女-第—.目 體實施例，該頻率調變系統時脈產生於肉都 曰上 ~ ^ 於内。p，即在該控制 早7L内也就是在該晶片上。在圖5中，說明用於該頻率，料 之内部產生之-電路。可以看見’傳統所使用的外部二 -22- 87792 振盪器126，其置放於該電路 板上，保留之以將該系統時脈 sys—cik提供給該控制晶片。 糾 A Γ以上已經說明的元件，提 七、一除法器控制器1 3 2，其經由… 八、，、二由一弟一控制匯流排134連接 主邊弟_預除法器丄〇4，經 _ 第一控制匯流排1 3 6連接至 “弟二預除法器丨丨2，經由一— 田弟二控制匯流排138連接至該 第反饋除法器11 〇並經由一篦to以心^ > 略一 田弟四控制匯流排140連接至該 第一反饋除法器丨丨8。 八"巾所一况明的只現’是由-「晶片上」頻率調變所為的 解之只^，其與根據圖4所說明的實際情況相比更高明 而技術上更容易實現。用於該項具體實施例所基於的頻率 ㈣之起點是分別用在該等鎖相迴路i n 器：12,以及該等反饋除法器u。與118。經由」= 的法或可耘式隨機產生器，在該除法器控制器i32 的控制下’變動該等預除法器1〇4及112之每一個與該反饋 除法器的除法器值，以獲取上述時間與頻率行為。在圖5 所說明的具體實施例中，該除法器控制器132包含一樣本控 制、一可程式計數器/除法器以及一隨機產生器。 對於該頻率調變之結果，該等預除法器104、112 (npi<e，div) 的知確11疋重要的，其中應注意，由此欲設定的最小頻率 段差Msup藉由該鎖相迴路1〇8、116的反饋除法器u〇、ιΐ8 (ndiv)而向上轉換。對於將分別在該像素時脈卯u —與該記 憶體時脈mpll〜cik中有效獲取的頻率段差之數量，在具有該 等電路之相同結構條件下，下式成立：Mnterf: 78 · 75 MHz-66 MHz = 12.75 MHz 〇 Based on this, the amount of interference in this analog video input (active area + blank) can be calculated for each input line. The result is: mterf / line = (78.75 / 1 2.75) · 1 * 1312 = 212.4190 Therefore 'the maximum / minimum value of this interference occurs periodically with the following spacing: linterf = 1312 / 212.4190… = 6.1764… pixels and tinterf = (78.75 MHz) -1 * 6, respectively, 1764 ......... = 78.43 13 ... ns. If it is assumed that in the first frame (frarne; f = 1), the first line (n = 1) is selected and the starting point t = 0s, then between the sixth and seventh pixels and each at 78 · 43ι3 After ns, one of the minimum / maximum of the interference can be seen first, and thereafter, periodically, until the end of the line. Since the interference period is generally not suitable for an input line as an integer, it leaves the next remainder at the end of each line. (Interf / line) The difference between * n and the next integer is the individual starting value for the next line n + 1. With the shift of the individual starting values of each line, a diagonal pattern is formed, in which the following applies: remainder {interf / line} < 0.5 —diagonal bars \\\\\\\ remainder {interf / line } > 0.5 —diagonal bar //////// 87792 200415566 The value accumulated after the last line (interf / line) * ^ to determine the interference in the subsequent frame (f + 1) The starting value, where in most cases one of these diagonals shifts up or down. As a result, depending on the vertical frequency of the screen, a diagonal line is moved across one of the original image travels in one direction. In a fixed frequency ratio, the apparent speed in the moving direction is constant and depends only on the interference frequency and the waveform of the input signal at the analog video input. With reference to FIG. 11, the above description of generating the interference pattern is summarized again by illustration. In particular, the fixed value of the starting value is used for subsequent lines and back frames. In fact, the mechanism for the formation of this interference is more complicated, because not only all the harmonic frequency parts, but also all components on the control chip and these external components (such as the phase-locked loop on the control chip, The dynamic behavior of such inputs ”, sources, etc., all play an important role, but in principle, they can: calculate the interference generated here. The relevant interference pattern on the screen due to the above mechanism, for the user / observation [Abstract] The purpose of the present invention is to provide a method and control unit for avoiding disturbances, such as the method in the first scope of the patent application, and the patent application | The equipment of item 9 can achieve this goal. The present invention provides a method for reducing the interference pattern displayed on a fluorescent screen with a frequency of one to four, one to one, and one frequency to Beijing, which can be controlled by a control unit. The pixel data provided to the | 87792 -13-200415566 to explain the image. In the process of generating the pixel data in #, the clock signal used to generate the pixel data can be changed. [Embodiment] According to a specific embodiment, the present invention provides a method for reducing the interference pattern of an image displayed on a screen having a pixel frequency, wherein the control unit can provide the screen to the screen. The pixel data is used to describe the image, wherein the pixel frequency is changed during the generation of the pixel data. Further, the present invention provides a control unit for controlling a screen that operates at a pixel frequency, so as to display on the screen having The image of the interference pattern has been reduced. The control unit includes an input for receiving image data, and a processing unit (which processes the received image data to generate the pixel data ', in which the pixel data generation process "The processing component changes are used to generate pixel data-or digital pulse signals) and provide pixel data for display. An output according to the specific embodiment-the present invention further provides for controlling operation at a pixel frequency -The control unit for displaying images with reduced interference patterns on the camp screen. The control unit Contains one input for receiving image data 'a processing component (which processes the received image data to generate the pixel data') in the process of generating the pixels, the processing component changes. The pixel is changed Frequency) and providing pixel data for display one output. The control unit causes the control chip to thereby destroy a typical interference pattern and therefore operates according to one of the method of the present invention and the dedicated clock ratio of the present invention, making it almost Not visible. 87792 -14- 200415566 The basis of the knowledge is that a rigid frequency ratio and a fixed input signal waveform are the causes of the interference patterns and the interference images. If it is no longer possible to borrow separately A proper design of one of these analog components to avoid visible interference such as “a” is the starting point of the frequency ratio on the chip to solve problems related to interference images. Generally, the steps of the invention can be seen in destroying the correlation of the frequency used and the rigidity ratio, so that regular interference patterns cannot occur in one frame or in subsequent frames. According to a preferred embodiment, the destruction of the correlation and rigidity ratio of these frequencies occurs by frequency modulation depending on time, respectively. Therefore, the interference between one and five Least Significant Bits (LSBs) still generally exists, but only slightly irregular noise in the image can be seen by the naked eye, so it has much less interference. According to a first embodiment, a time-dependent frequency modulation (frequency m0dulation, fm) is achieved by a time-continuous frequency modulation. According to another specific embodiment, a time-dependent frequency modulation is achieved by a time-dispersed frequency modulation. According to a second preferred embodiment, the frequency modulation of a control chip is performed by an external frequency source, or according to another embodiment, is performed by an internal frequency source implemented on the chip. According to a third preferred embodiment, the frequency modulation is performed by using the (or other) spread spectrum phase-locked circuit. The preferred developments of the invention are defined in the subordinates of the scope of the patent application. In the following descriptions of these preferred embodiments, the elements in the drawings | port J, see -15- 87792 200415566 elements that look like or similar have the same reference symbols. Based on the simple model of interference formation described above, the steps, methods and equipment of the invention will be described below, whereby the formation of visible and therefore disturbing interference can be avoided or suppressed. Here, it should be noted that the methods and steps described below are considered as additional to the measures that must be taken in related analog circuit parts and the entire system (printed circuit board, chip, application) to reduce noise Sensitivity and unwanted substrate and concentrated voltage. Therefore, it is best to apply the present invention to a system that has been fully developed and has an analog operation behavior related to interference insensitivity. As described above, according to a preferred embodiment of the present invention, the interference pattern is avoided by implementing a time-dependent frequency modulation (frequency m0dulati〇ii FM) to obtain a change in pixel frequency. The frequency Modulation destroys the correlation and stiffness ratio of these frequencies respectively, so that when the interference frequencies are internally coupled, the interference patterns are reduced or suppressed. According to a first specific embodiment, the time-dependent frequency modulation is achieved by a time-continuous frequency modulation that passes through a frequency region M at an appropriate rate, for example, by the action of a frequency wobble wheel, It is respectively fixed by a modulation function around the fundamental frequency (f ()) required by the screen and the memory. It is assumed that the required clock signal is generated on the control chip by a phase locked loop (PLL). For the input frequency fXPmn⑴ of these phase locked loops, the following formula holds: fxpllin (t) = f〇 + Af * g (t) 87792 -16-200415566 and: f〇 the fundamental frequency (pixel frequency) of the screen or the fundamental frequency of the memory △ f — the frequency range around the fundamental frequency g (t) = tuning Variation function The modulation function g⑴ can be an arbitrary 1 P 丄, the main text, for example, the function illustrated in Figure IA 5 1 C, directly in a ^ ^, but also does not produce a function of the function used Formation and implementation restrictions. The number of times in the time-continuous situation of the frequency modulation described here, the interference pattern will be continuously changed in each line and thus in each individual frame: when the function g⑴ and the parameter are turned out appropriately In shirts, a seemingly uncorrelated white (quasi) noise may be generated from the originally correlated interference pattern. In another preferred embodiment of the present invention, a discrete frequency modulation is used instead of the above-mentioned steps for time-continuous frequency modulation, which generally yields similar results. In terms of it, it has obvious advantages. ° In this specific embodiment, the frequency fxpiiin (k) to be modulated does not change continuously, depending on the implementation of the frame or the line. Further, optional-any timely decision. As in this time-continuous frequency modulation ^ Via-an appropriate random generator 'the frequency can be continuously or arbitrarily and indefinitely changed' it can achieve "white" (quasi) noise-more efficient generation: In a specific embodiment, for the input frequency of the phase-locked loop configuration, the following formula holds: -17- 87792 200415566 fxpllin⑴ = f〇 + Af * g (k) and: f〇 = the fundamental frequency (pixel frequency) of the screen or Fundamental frequency of the memory △ f = frequency range around the fundamental frequency g (k) = time discrete modulation function k = operating index The operating index k increases by 1 whenever a predetermined condition of a frequency change is satisfied 'For example, a line or a frame change or the like occurs, which means that a new line and a new frame are reached, respectively. In Figure 2 eight to. In the following, an example of the time-dispersion modulation frequency g (k) is described. However, it should be noted here that there is generally no limitation on the discrete function to be used. As in the first embodiment described above, by properly selecting the function g (k), the unitary condition, and the parameter M, the result can be-"white" (quasi) noise: invisible or only in the best case Faintly visible. As far as the above specific embodiments are concerned, it should be generally noted that, by appropriately determining the modulation conditions, the above two methods for generating the dependency can be used with great flexibility, and The method can be applied to the condition of %%. The necessity of this is due to a plurality of possible input modes and input frequencies. The generation and distribution of I and clock signals on a control chip are described in more detail = Brother Ming 'as explained in accordance with FIG. 8, and then, based on this discussion-to explain the implementation in the control chip of the LCD screen Specific 87792-18-200415566 embodiments of the method of the present invention. FIG. 3 illustrates a block diagram of a unit required to generate a clock on a control chip. As shown in the schematic diagram of FIG. 3, the displayed switching elements are used to generate the memory clock mpll-elk and the pixel clock ppU-clk. The circuit includes a multiplexer 100 that receives a horizontal synchronization signal (HS; H_Sync) at a first input. At a second input, the multiplexer 100 receives an external oscillator clock sys_clk. According to a driving signal, the multiplexer selects one of the inputs as an input signal to generate the pixel clock ppU-dk. The output signal selected by the multiplexer 100 is provided to a pre-divider 104 (nprediV) via a line 102 'where an output generated by the multiplexer 100 is matched via another line 106 to an input of a phase-locked loop 108' which The pixel clock ρρΠ-Clk is provided at the output under the control of an internal divider [〖ο). Further, the external oscillator clock sys_elk is provided to another pre-divider 112 (n), and the far pre-divider outputs an output signal to the phase-locked loop 116 via line 114 at its output. The phase-locked loop 116 is driven by an internal control U8 (ndiv) and outputs the memory clock 1111311 _ () 1] ^ at the output. Further, the clock 'rclk shown in FIG. 3 which is not used to operate the register (the configuration register shown in FIG. 8) is equivalent to the system clock or the external oscillator clock sys_elk. Further, the explanation The input clock avi A Clk is generated from the horizontal synchronization signal HS (synchronization signai) via another phase-locked loop 12 and a downstream phase delay loop ′, and is also provided to a sampler i24 for the AVI signal. Acquisition and digital conversion. The schematic circuit diagram shown in FIG. 3 is for a control unit with one of the external memories 87792 -19- 200415566 LCD control chip used to produce a taste clock, which generally has at least four phases at a certain time. Interrelated different clocks (clock domain). Further, according to Fig. 3, 鼗 + 田 #, ..., a configuration for the clock generation, this configuration can also be found in subsequent implementations and applications. In Figure 3, the four clocks and their generations are summarized, and in addition to the phase-locked loop 108 (llpll) which can input the analog video into AVI's Rf, t ^ synchronous "number HS as the input signal. Therefore, all other phase-locked loops are driven by the external oscillator clock sys_elk. The clock rcik used for the register of the control chip 800 is not critical. The clock is generally the same as the external clock (Rclk = sys_clk), and since these registers are static in normal operation, they have no visible or measurable effect on the analog circuit of the chip. For these associated phase locks The memory clock mpll-clk and the screen clock (pixel clock) ppU_dk generated by the circuits 108 and 116 (ppu, mpl) are different. Through these clock signals, not only the LCC ^ S chip Large digital blocks, and individual input / output interfaces, that is, the memory interface and the screen interface are timed. In the two phase-locked loop, the external oscillator clock can be used as an input signal, and borrowed By stylizing the pre-dividers 104, 112 and the internal The loop dividers 11 and 118 can set the required frequency of the clock signal at the output. In the screen phase-locked loop, the selected input H-Sync signal and the specific implementation described In the example, the analog video input signal HS can be used as an input signal as a substitute for the external clock sys_clk. Starting from the system architecture illustrated in Figure 3, the following will be used to implement 87792-20-200415566. The method is described as two preferred specific embodiments of the quasi-decomposition of such clocks. Those skilled in the art will understand from the following embodiments that other implementations are possible. 1 'According to FIG. 3, a specific embodiment will be described. The system clock with a modulated frequency is fed from an external source. Fig. 4 shows a part of the circuit elements shown in Fig. 3 for generating the pixel clock pulse pll-elk and the memory clock mpU-clk. The external feed system clock Sys-Clk is selected as the input signal of the phase-locked loop 108 to generate the pixel clock. Therefore, based on simple and clear considerations, the multiplexer 1 shown in FIG. 3 is omitted in FIG. 4. 〇. Can be seen in Figure 4, take An external quartz or crystal oscillator 126 for a conventional LCD control chip, now uses a scan generator 126 to provide the system clock sys-elk. This consists of a quasi-oscillator 126 in 130 and pre-dividers 104 and 112. (npre-div) is shown. The specific embodiment described in the figure * is a simple embodiment of the present invention, in which an external frequency generator 128 is used, such as Stanford DG 245 or the like. To replace the commonly used quartz oscillator 126, it is placed on the printed circuit board instead of the quartz oscillator, and the control chip for driving the screen is also placed here. If the frequency generator 128 is set to generate a modulated frequency signal corresponding to the specific embodiment of the present invention, the modulated frequency output signal of the generator 128 can be used as an input signal and a system, respectively. The clock sys — c Ik is used for the phase locked loops 108 and 116. By carefully selecting these parameters, the clock signals ppi_cik and mpl generated by the phase-locked loops 108 and 116 (ppll-mpll) related to the sample clock of the analog input signal (avi-elk) can be obtained. —Clk one quasi-decomposition. -21- 87792 200415566 The system edge of the parameter to be selected is taken from the dead boundary, which depends on the dynamic phase characteristics of the phase-locked loops 108 and 116. On the other hand, it depends on the connected units ( Refers to the frequency tolerance of the connected screen and memory). This means that even if it is in the -maximum frequency deviation due to the frequency modulation ', it is still necessary to ensure that a safety data is transmitted to the connected heart king G reverse raft. In addition, in a strong frequency modulation, the yf library must be tested for ^ Tongling / "Limit control applied to the synthesis of digital blocks, in order to avoid these problems and specific ancient times. It is also a timing problem at the interface between the 5Hixun blocks (block domain). Theoretically, the decision to select parameters for this frequency modulation is very expensive. In fact, Not only these fundamental frequencies, but also the harmonic characteristics of all harmonics and the dynamic characteristics of all components overlap and lead to a complex time and frequency behavior. One tube can be theoretically determined. But for each combination of input modes / applications, It is good to use the empirical method to determine the number of springs used for frequency modulation. Based on the value determined in this way, a determination is made according to a desired pattern ^ Although the specific embodiment just described provides good results for the external frequency generator Result 'But the disadvantage of this specific embodiment is that the cost and labor cost for connecting the external frequency generator is too high. For a later library use, it is not necessary to use-the external frequency generator 1 is in a practical situation , The simplified-programmable / initializable generator used on the printed circuit board represents a possible but also uneconomical solution. Therefore, according to the present invention, the method, table, and table for implementing the present invention are: / 女-第 —. In the embodiment, the clock of the frequency modulation system is generated in the meat. It is within 7L of the control, that is, on the chip. In FIG. 5, Explain that for this frequency, the internal circuit is generated. You can see 'External 2-22-87792 Oscillator 126 traditionally used, which is placed on the circuit board, and it is reserved to set the system clock sys— cik is provided to the control chip. Correction A Γ For the components already described above, mention seven, a divider controller 1 3 2, which is connected to the master and the younger brother via the eighth, the second and the second control bus 134 The divider 丄 〇4 is connected to the “Second Pre-divider” via the first control bus 1 3 6 and is connected to the feedback divider 11 〇 via the Tian Di Er control bus 138 and via篦 to heart ^ > Slightly Yitian Di four control bus 140 connected to the first counter Shushu divider 8. The "existence of the eighth" is the solution of the "on-chip" frequency modulation ^, which is more lucid and technically easier to implement than the actual situation described with reference to FIG. 4. The starting points for the frequency ㈣ used for this specific embodiment are used in the phase-locked loops i n: 12 and the feedback divider u, respectively. With 118. Through the method of "=" or a achievable random generator, under the control of the divider controller i32, 'change each of the pre-dividers 104 and 112 and the divider value of the feedback divider to obtain The above time and frequency behavior. In the specific embodiment illustrated in FIG. 5, the divider controller 132 includes a sample control, a programmable counter / divider, and a random generator. For the result of the frequency modulation, it is important to know the pre-dividers 104, 112 (npi < e, div). Among them, it should be noted that the minimum frequency band difference Msup to be set from the The feedback dividers u0, ιn8 (ndiv) of 108 and 116 are up-converted. For the number of frequency steps that will be effectively acquired in the pixel clock 卯 u — and the memory clock mpll ~ cik, respectively, under the same structural conditions with these circuits, the following formula holds:
Afstep = Afn * ndiv/nprediv , 87792 -23- 16 200415566 其中，例如，下式成立： 2( ndi 由此得出最小Afstep。 該等頻率除法器的變動具有之一問題即事實是，原則上 ’其係計數器’經程式化至一特定的終值並在達到該玖值 (臨界值）時提供一輸出脈衝。因此，僅當該計數器溢出時 ，才會發生該等鎖相迴路的輸入頻率之一重新程式化以及 由此引起的-調變。由於該等鎖相迴路的動態行為，該等 輸出時脈信號及該等輸出頻Wpll_clk、仙之一或多 或少時間連續的變化分別發生。因此’不必在該等階梯寬 度Mstep内實現—高解析度，因為無論如何該等鎖相迴路皆 會連續地穿過該等中間範圍。 ▲貫現該第二具體實施例以實施本發明之方法比藉由已調 變頻率的信號產生於外部的情況要容易得多，但是該鎖相 迴路的時間行為在此亦是決定性的因h由於該等預除法 益已存在於現有的電路及設計中，因此可不太費力地實施 並檢驗本發明之方法（除法器邏輯與控制）。 實施分解所需的頻率調變之―第三較佳具體實施例即一 替代性鎖相迴路概念的使用。將所謂展頻鎖相迴路用於類 似的應用中以提高 EMC/DMI (EMC = Electr〇magnetic (電磁相容性），(最小限度）） 猎由適當调整該等鎖相迴路的參數及其控制（線性、函數 87792 -24- 200415566 由此不發生可見干擾以 或隨機），可能獲取二個時脈分解 及可能正面影響該EMC/EMI行為 圖6中說明一正常相位鎖定電路（正常似）與_展頻鎖相 迴路（展頻PLL)之間的差別。可以看見，與該正常pa相比 ，該展頻PLL產生橫跨-默頻率範圍的輸出信號，而該 正常PLL僅提供取決於該輸人頻率的—單_輪出頻率。因 此，在此亦可實現以上較詳細說明的用於該等時脈信號之 分解的發明方法。 下面更詳細地說明用於分解該等時脈信號的實驗結果， 其中其已依據藉由該等已調變頻率的信號之一外部饋送來 貫施該方法的上述第一具體實施例而實行。 對於在一 LCD控制單元（特定言之係諸如SAA 6714之類 的控制單元）内所發生的干擾之分析，將資料儲存於一記憶 體中並因此對其進行統計評估之可能得以適用。因此，下 面首先說明一個別測試安裝，然後說明由此獲得的該分解 結果以及該已調變頻率的系統時脈之外部饋送。 該測試安裝包含以下裝置及組件·· -作為系統時脈產生器的Stanford研究系統合成函數產生 器，DS345 型， -作為AVI信號來源的量子資料視訊測試產生器，8〇 1 型， -SAA6714 評估板「Early Dragon」，第 1.2 版，具有 SAA6714A， -LGPhilips 面板，18 英吋，LM181E1 型，SXGA 解析度， 87792 -25- 200415566 -12 V/5 A Deutronic功率供應，DTP60型 選取以下設定及參數： 輸入： 量子資料測試產生器 格式： 83 = DMT1260 圖像：43 = 45Flat27 解析度：1280 X 1024 時脈產生：Afstep = Afn * ndiv / nprediv, 87792 -23- 16 200415566 where, for example, the following holds: 2 (ndi from which the minimum Afstep is obtained. One of the problems with the changes in these frequency dividers is the fact that, in principle, ' It is a counter that is programmed to a specific final value and provides an output pulse when the threshold value (threshold value) is reached. Therefore, only when the counter overflows will the input frequency of the phase-locked loops occur. A re-programming and the resulting modulation. Due to the dynamic behavior of the phase-locked loops, the output clock signal and the output frequency Wpll_clk, one of the more or less continuous changes in time occur separately. Therefore, 'it is not necessary to achieve within the step width Mstep-high resolution, because the phase-locked loop will continuously pass through the intermediate range anyway. ▲ Implement this second embodiment to implement the method of the present invention It is much easier than when the signal with a modulated frequency is generated externally, but the time behavior of the phase-locked loop is also decisive here because the pre-divided benefits already exist in the existing In the circuit and design, the method (divider logic and control) of the present invention can be implemented and tested with less effort. The frequency modulation required to implement the decomposition-the third preferred embodiment is an alternative phase-locked loop concept The use of so-called spread-spectrum phase-locked loops for similar applications to improve EMC / DMI (EMC = Electromagnetic Compatibility, (minimum)). Properly adjust the parameters of such phase-locked loops. And its control (linear, function 87792 -24- 200415566 from which no visible interference or random occurs), may obtain two clock decompositions and may positively affect the EMC / EMI behavior Figure 6 illustrates a normal phase lock circuit (normal Like) and _spread-spectrum phase-locked loop (spread-spectrum PLL). It can be seen that compared with the normal pa, the spread-spectrum PLL produces an output signal across the silent frequency range, while the normal PLL only provides The single-round frequency that depends on the input frequency. Therefore, the invention method for the decomposition of such clock signals described in more detail above can also be realized here. The following is a more detailed description of the method for decomposing the clock signal. The experimental results of the clock signal have been implemented according to the above-mentioned first specific embodiment of the method implemented by external feeding of one of the modulated frequency signals. For an LCD control unit (specifically, An analysis of interference occurring in a control unit such as SAA 6714), the possibility of storing data in a memory and therefore statistically assessing it may be applicable. Therefore, the following first describes a special test installation and then explains The decomposition result thus obtained and the external feeding of the system clock with modulated frequency. The test installation includes the following devices and components ...-Stanford Research System Synthesis Function Generator, DS345, as the system clock generator, -Quantum data video test generator as AVI signal source, type 801,-SAA6714 evaluation board "Early Dragon", version 1.2, with SAA6714A, -LGPhilips panel, 18 inches, LM181E1 type, SXGA resolution, 87792 -25- 200415566 -12 V / 5 A Deutronic power supply, DTP60 type selects the following settings and parameters: Input: Quantum data test Generator Format: 83 = DMT1260 image: 43 = 45Flat27 Resolution: 1280 X 1024 clock generator:
Stanford研究系統合成函數產生器 基礎頻率：25,000,〇〇5·〇〇〇 Hz (25.000005 MHz) 由於以Hz&差將该頻率設定於該研究產生器之 可能，可能產生一停滯的干擾圖案之特別情形，然後可對 其進行統計評估（即使在記憶體中沒有快取記憶體卜如在 正¥ 作過权中由一石英振堡器產生該系統時脈，則干擾 線的產生及類型很大程度上取決於該石英振盈器的溫度及 其老化、生產容限等。 測試一 LCD控制的行為，根據圖8已對其作說明。在此， 該外部頻率產生ϋ之輸出充當用於該記憶體時脈及該登幕 時脈（像素時脈）的參考信號，如上所述。在該外部產生器 處之一頻率調變分別產生該記憶體時脈及該資料流時脈之 一頻率調變，其由個別鎖相迴路之動態行為所決定。 圖7顯示-螢幕列印之-部份’其藉由將畫面凍結於該 咖定標器的外部記憶體内並讀出該記憶體區域。由於在 列Ρ中成乎不能看見該等干擾線，基於說明之目的 87792 -26- 200415566 ，以白線突出顯示其中三條。 與已經說明的離散模型相反，實際上該干擾圖案之一強 依賴性甚至顯示於小頻率變化中。隨著該輸入頻率的僅數 赫茲之一變化，不同的干擾圖案變得可見。 在下表中，顯示一些設定以及該等干擾線之個別形式。 頻率(Hz) 干擾線 25,000,004 順時針約20度傾斜並具有約5 mm之一間距 25,000,010 順時針約20度傾斜並具有約3 mm之一間距 25,000,012 順時針約150度傾斜並具有約2 mm之一間距 25,000,018 順時針約20度傾斜並具有約5 mm之一間距 25,000,025 如同在25,000,012與25,000,010 中一樣 藉由使用經由在該印刷電路板上取代該石英振盪器之一 已調變頻率系統時脈的分解，可能使圖7中所說明的干擾圖 案為肉眼所「不可見」。對於所需的效果，一決定性的因素 由此係，藉由頻率調變及垂直更新率的干擾頻率之組合、 干擾線之轉換。 舉例而言，將考慮發生於25,000,004 Hz系統時脈之干擾 圖案。選取一 25 Hz的掃描率、一 7777 Hz的已掃描頻率範 圍以及作為調變頻率g(t)之一正弦函數，藉由該些設定，於 該函數產生器獲得一很好的結果，其中該等干擾線不再能 為肉眼所見。 較佳的是，藉由使用一隨機調變以實施本發明之方法， 因為，藉由該頻率調變本身，可能產生一新的以及（當其發 -27- 87792 200415566 生時）複雜的’干擾圖案。由於該行為主 要期望於連續調變 “数中’由離散模型的該模擬結果得出， ^ ^ 5亥隨機調變是該 頻率調變的更有利變化。Stanford Research System Synthetic Function Generator Base Frequency: 25,000, 500,000 Hz (25.000005 MHz) Due to the possibility of setting this frequency to the research generator with a difference of Hz &, a special interference pattern may be generated Situation, and then it can be statistically evaluated (even if there is no cache memory in the memory, if the system clock is generated by a quartz oscillator in the right, the generation and type of interference lines are very large The degree depends on the temperature of the quartz resonator, its aging, production tolerances, etc. Test the behavior of an LCD control, which has been explained in accordance with Figure 8. Here, the output of the external frequency generating chirp serves as the The reference clock of the memory clock and the clock (pixel clock) is as described above. A frequency modulation at the external generator generates the frequency of the memory clock and the clock of the data stream, respectively. Modulation, which is determined by the dynamic behavior of individual phase-locked loops. Figure 7 shows-part of the screen print-which freezes the picture in the external memory of the coffee scale and reads out the memory region. Since it is impossible to see these interference lines in column P, for the purpose of illustration 87792 -26- 200415566, three of them are highlighted with white lines. In contrast to the discrete model already explained, in fact, one of the interference patterns is strongly dependent even Displayed in small frequency changes. As the input frequency changes by only one of a few hertz, different interference patterns become visible. In the table below, some settings and individual forms of these interference lines are shown. Frequency (Hz) Interference lines 25,000,004 tilted approximately 20 degrees clockwise and has a pitch of approximately 5 mm 25,000,010 tilted approximately 20 degrees clockwise and has a pitch of approximately 3 mm 25,000,012 tilted approximately 150 degrees clockwise and has a pitch of approximately 2 mm 25,000,018 clockwise approximately 20 It is tilted and has a pitch of about 5 mm 25,000,025 as in 25,000,012 and 25,000,010. By using the decomposition of the clock of the modulated frequency system by replacing one of the quartz oscillators on the printed circuit board, it is possible to make FIG. 7 The illustrated interference pattern is "invisible" to the naked eye. A decisive factor for the desired effect is therefore, by frequency Combination of interference frequency of modulation and vertical update rate, conversion of interference line. For example, interference patterns that occur in the system clock of 25,000,004 Hz will be considered. Select a scan rate of 25 Hz and a scanned frequency range of 7777 Hz And as a sine function of the modulation frequency g (t), with these settings, a good result is obtained in the function generator, where the interference lines are no longer visible to the naked eye. Preferably, by borrowing The method of the present invention is implemented by using a random modulation, because, with the frequency modulation itself, a new and (when it occurs -27- 87792 200415566) complex 'interference pattern' may be generated. Since this behavior mainly expects continuous modulation, "Number in the number" is obtained from the simulation results of the discrete model, and ^ 5H random modulation is a more favorable change of the frequency modulation.
該二發明方法均已顯示於模型以及實 ^ ,,, .. - ^ 貝1不中，即可使LCD 徑制早凡中的干擾發生分別得到有效減 分松士 乂平工亚猎由所說明的 專時脈k號之準分解而使之不可見。 該技術可較容易地實現，但對於該方法之有效使用，則 要為不同的模型確定適合的參數以保證該方法可靠運作而 且該等外部組件（記憶體及螢幕）沒有問題。 以上已經對本發明之一較佳具體實施 卞更砰細說明， ::中，產生該等像素資料時藉由改變該像素頻率從而獲取 U該等可見干擾。但是本發明並不受此限制。 一般地，能以與該等信號ppll&mpU同樣的方式來 該第二板上的晶片上的所有干擾信號， 木 尽發明不限於 v些日守脈彳§號而一般能應用於所有時脈信號。 【圖式簡單說明】 下文將參考隨附圖式來更詳細地制本發明 實施例。附圖顯示： 八體 圖1A至C一時間連續調變函數的範例； 圖2A至C一時間離散調變函數g(k)的範例； 圖3-方塊圖，其說明一營幕之一控制晶片中的時脈產生 圖4依據本發明之_第—具體實㈣並具有 變的一控制單元之—方塊圖； 4率调 圖5依據本發明之一第-呈㈣杏#办丨*曰‘ # 一具體““列亚具有内部頻率調 87792 -28- 200415566 變的一控制單元； 圖6在一展頻鎖相迴路中的頻率回應； 圖7在具有記憶體與螢幕介面之一 LCD控制單元中的干 擾圖案之一範例； 圖8—已知的LCD控制單元之一方塊圖； 圖9顯示圖8的LCD控制單元之螢幕介面之一等效圖式； 圖10A具有一螢幕介面之一 LCD控制單元中的一干擾圖 案； 圖10B具有一螢幕介面與一記憶體介面之一 LCD控制單 元的一干擾圖案；以及 圖11說明一干擾圖案的形成之一圖示。 【圖式代表符號說明】 100 多工器 102 線 104 第一預除法器 106 線 108 鎖相迴路 110 第一反饋除法器 112 第二預除法器 114 線 116 鎖相迴路 118 第二反饋除法器 120 鎖相迴路 122 延遲迴路 -29- 87792 200415566 128 外 部 頻 率 產 生器 132 除 法 器 控 制 器 134 第 一 控 制 匯 流排 136 第 二 控 制 匯 流排 138 第 二 控 制 匯 流排 140 第 四 控 制 匯 流排 126 準 振 盪 器 ;英振盪器） 800 控 制 晶 片 802 輸 入 來源（類比輸入AVI) 804 輸 入 來 源 806 入 來 源 808 輸 入 選 擇 單 元 810 控 制 晶 片 之 一輸入 812 5己 憶 體 之 一 處理單元 814 記 憶 體 介 面 818 出 介 面 822 驅 動 器 級 824 驅 動 器 級 ppll_clk 像素 時脈 822a 第 一 場 效 電 晶體 822b 第 二 場 效 電 晶體 824a 第 _ 一 場 效 電 晶體 824b 第 二 場 效 電 晶體 Ci 電 容 -30- 87792 200415566 C2 電容 C3 電容 c4 電容 Li 電感 L2 電感 Ri 電阻器 r2 歐姆部份 Rs 電阻器 TL 傳送線 avi_clk 輸入時脈 mpll_clk 記憶體時脈 sys_clk 外部振盪器時脈 uL⑴ 電壓 -31 87792The two methods of the invention have been shown in the model and the actual ^ ,,, ..-^ If the 1 is not successful, the interference in the LCD system can be effectively reduced. The quasi-decomposition of the illustrated special clock k makes it invisible. This technique can be easily implemented, but for the effective use of this method, it is necessary to determine suitable parameters for different models to ensure that the method operates reliably and that these external components (memory and screen) are not problematic. One of the preferred embodiments of the present invention has been described above. More specifically, in ::, when the pixel data is generated, the pixel frequency is changed to obtain visible interference such as U. However, the present invention is not limited to this. In general, all interference signals on the chip on the second board can be used in the same way as the signals ppll & mpU. The invention of wood is not limited to the number of clock guard pulses and can generally be applied to all clocks. signal. [Brief description of the drawings] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The figures show: Eight-body examples of 1A to C-time continuous modulation function; Figure 2A to C- examples of time-dispersed modulation function g (k); Figure 3-block diagram illustrating one control of a camp curtain The clock in the chip is generated. Figure 4 according to the present invention-the first concrete embodiment and a control unit with a change-a block diagram; 4 rate adjustment Figure 5 according to the first one of the present invention-Cheng㈣ apricot # 办 丨 * '# A specific "" Leia has a control unit with internal frequency adjustment 87792 -28- 200415566; Figure 6 Frequency response in a frequency-spreading phase-locked loop; Figure 7 LCD control with one of the memory and screen interface An example of an interference pattern in a unit; Figure 8-a block diagram of a known LCD control unit; Figure 9 shows an equivalent diagram of the screen interface of the LCD control unit of Figure 8; Figure 10A has one of the screen interfaces An interference pattern in an LCD control unit; FIG. 10B is an interference pattern of an LCD control unit with a screen interface and a memory interface; and FIG. 11 is a diagram illustrating the formation of an interference pattern. [Schematic representation of symbols] 100 multiplexer 102 line 104 first pre-divider 106 line 108 phase-locked loop 110 first feedback divider 112 second pre-divider 114 line 116 phase-locked loop 118 second feedback divider 120 Phase-locked loop 122 Delay loop-29- 87792 200415566 128 External frequency generator 132 Divider controller 134 First control bus 136 Second control bus 138 Second control bus 140 Fourth control bus 126 Quasi-oscillator; British oscillator) 800 control chip 802 input source (analog input AVI) 804 input source 806 input source 808 input selection unit 810 one of the control chip input 812 one of the memory cells processing unit 814 memory interface 818 output interface 822 driver level 824 driver level ppll_clk pixel clock 822a first field effect transistor 822b second field effect transistor 824a first _ field effect transistor 824b second field effect transistor Ci capacitor -30- 87792 200415566 C2 capacitor C3 Capacitor c4 Capacitor Li Inductor L2 Inductor Ri Resistor r2 Ohm Part Rs Resistor TL Transmission Line avi_clk Input Clock mpll_clk Memory Clock sys_clk External Oscillator Clock uL⑴ Voltage -31 87792