KR101274696B1 - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving device of a liquid crystal display device and a driving method thereof, which can correct a control signal generated unstable due to a spreading frequency to prevent display defects on a screen, and includes a liquid crystal panel including an image display unit for displaying an image. A gate and a data control signal are generated using a gate and a data integrated circuit driving the liquid crystal panel, and a synchronization signal from outside; And a timing controller for delaying the supply to the gate and the data integrated circuit.

Spread Spectrum, Spread Dot Clock

Description

Driving device for liquid crystal display and driving method thereof {Driving circuit for liquid crystal display device and method for driving the same}

1 is a block diagram showing a driving device of a liquid crystal display according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating the timing controller shown in FIG. 1. FIG.

3 is a waveform diagram illustrating synchronization signals and gate and data control signals;

4 is a configuration diagram illustrating a delay unit illustrated in FIG. 2.

5 is a waveform diagram illustrating an input / output signal of a delay unit illustrated in FIG. 4.

＊ Description of symbols for main parts of the drawings ＊

DDe1 to DDen: Even data integrated circuit (first data integrated circuit)

DDo1 to DDon: odd data integrated circuit (second data integrated circuit)

DLe1 to DLen: Even data line (first data line)

DLo1 to DLon: odd data line (second data line)

NG: NOT Gate SDCLK: Diffusion Dot Clock

DSOE: Delayed Source Output Enable DE: Data Enable

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device and a method of driving the liquid crystal display device capable of correcting a control signal unstable due to a spreading frequency to prevent display defects on a screen.

Conventional liquid crystal displays display images by adjusting the light transmittance of liquid crystals having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines and a plurality of data lines, and a liquid crystal capacitor connected to the TFT. The liquid crystal capacitor includes a liquid crystal and a pixel electrode and a common electrode for applying an electric field to the liquid crystal. The pixel electrodes are connected to a TFT which is a switching element. The TFT supplies the data signal from the data line to the pixel electrode in response to the output pulse from the gate line. The liquid crystal capacitor charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitors are connected to the liquid crystal capacitors in parallel so that the voltage charged in the liquid crystal capacitors is maintained until the next data signal is supplied. The storage capacitor is formed by overlapping pixel electrodes with a previous gate line and an insulating layer interposed therebetween. In contrast, a storage capacitor is formed by overlapping pixel electrodes with a storage line and an insulating layer interposed therebetween.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for supplying control signals for controlling the gate driver and the data driver.

The gate driver includes a shift register that sequentially generates scan pulses, that is, gate high pulses, in response to the gate control signal from the timing controller. To this end, the gate driver includes a plurality of gate driver integrated circuits having the shift register.

The data driver includes a plurality of data integrated circuits for supplying an analog image signal to each of the data lines of the liquid crystal panel. Each data integrated circuit converts the data signal arranged from the timing controller into an analog image signal according to the data control signal supplied from the timing controller, thereby converting the analog image signal for one horizontal line every horizontal period in which scan pulses are supplied to the gate lines. Is supplied to the data lines. That is, each data integrated circuit generates a plurality of gamma voltages having different voltage values corresponding to the number of gray levels of the data signal, selects one gamma voltage as the analog image signal according to the gray level value of the data signal, and selects a data line. To feed.

The timing controller arranges digital image data supplied from the outside to be suitable for driving the liquid crystal panel and supplies the digital image data to the data driver. In addition, the timing controller generates a gate control signal and a data control signal using a synchronization signal input from the outside, for example, a dot clock, a data enable signal, and horizontal and vertical synchronization signals to drive the data driver and the gate driver, respectively. Control timing.

In particular, the timing controller may include a gate and a gate within a specific frequency range according to a spread spectrum method to reduce electromagnetic interference (EMI) between various control signals and image data signals transmitted to the gate and the data driver. It generates data control signals. In other words, the timing controller may also generate gate and data control signals using the diffused dot clocks, wherein the gate and data control signals are shaken within a specific frequency range according to the diffused dot clocks. EMI can be canceled out.

For such frequency spreading, the driving device of the liquid crystal display further includes a spread spectrum integrated circuit for spreading the frequency of the dot clock input from the outside to supply the timing clock. Here, the spread spectrum integrated circuit frequency modulates an inputted dot clock and adjusts an oscillation frequency using a phase-locked loop (PLL) according to the modulated frequency, thereby changing the diffusion dot at a predetermined period within a specific range. Output the clock.

However, when the change range of the spreading frequency is changed to be below or above a specific frequency range, that is, the preset range, the spread range of the dot clock is also unstable to be below or above a specific range. As a result, the gate and data control signals generated by using the diffused dot clock are unstable, resulting in a defective display screen.

For example, when the diffusion frequency changes to 200 Hz or more, the diffusion range of the dot clock, that is, the diffusion period of the diffusion dot clock, is applied to 200 Hz or more in correspondence to the diffusion frequency. As a result, data control signal periods such as a data enable signal, a source output enable signal, and a source shift clock change, respectively, so that they do not match with each other and are unstable. In this case, analog image data from the data driver may not be properly supplied to each data line, resulting in a defective display screen.

An object of the present invention is to provide a driving device and a driving method thereof of a liquid crystal display device which can prevent display defects on a screen by correcting a control signal unstable due to frequency spreading. There is this.

The driving device of the liquid crystal display according to the embodiment of the present invention for solving the above problems is a liquid crystal panel including an image display unit for displaying an image, a gate and data integrated circuit for driving the liquid crystal panel, and from the outside And a timing controller configured to generate a gate and data control signal using the synchronization signal, and delay the at least one control signal among the gate and data control signals according to a synchronization signal from an external source and supply the gate and data control signals to the gate and data integrated circuit. It features.

In addition, the driving method of the liquid crystal display device according to an embodiment of the present invention for solving the above problems is to generate a diffusion dot clock by diffusing the frequency of the dot clock of the synchronization signal from the outside, the diffusion dot clock Generating a gate and data control signal using the synchronization signal, and delaying and outputting at least one control signal among the gate and data control signals according to the synchronization signal.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

1 includes a liquid crystal panel 4 including an image display unit 2 for displaying an image, and a plurality of gate integrated circuits GD for supplying scan pulses to the image display unit 2. ), A plurality of data integrated circuits DDe1 to DDon for supplying analog image data to the image display unit 2, and digital image data from the outside are aligned to be suitable for driving the liquid crystal panel 4, thereby providing each data integrated circuit. The gate and data control signals are generated to control the gates and the data integrated circuits GD and DDe1 to DDon, and the control signals generated unstable among the generated control signals from the outside. And a timing controller 8 for stably correcting and outputting the delayed signal according to the synchronization signal.

Here, the driving apparatus of the image display device according to an embodiment of the present invention generates a spectrum dot clock (SDCLK) by spreading a frequency of a dot clock (DCLK) input from the outside according to a spread spectrum method. In addition, a spread spectrum integrated circuit for supplying the generated SDCLK to the timing controller 8 may be further provided.

In addition, a driving apparatus of an image display apparatus according to an exemplary embodiment of the present invention includes a printed circuit board 10 having a timing controller 8 and a power circuit not shown, and each of the data integrated circuits DDe1 to. A plurality of data tape carrier packages (TCP) and each gate integrated circuit (GD) attached between the printed circuit board 10 and the liquid crystal panel 4 are mounted to mount the liquid crystal panel 4. It further comprises a plurality of gate TCP (16) attached to).

Each data TCP 12 is attached between the printed circuit board 10 and the liquid crystal panel 4 by a tape automated bonding (TAB) method. At this time, the input pads of each data TCP 12 are electrically connected to the printed circuit board 10, and the output pads are electrically connected to the data pads of the liquid crystal panel 4. On each data TCP 12, first data integrated circuits De1 to DDen representing even data integrated circuits and DDo1 to DDon representing odd data integrated circuits are mounted.

Each gate TCP 16 is electrically connected to the gate pad of the liquid crystal panel 4 by the TAB method. On this gate TCP 16, a gate integrated circuit GD is mounted.

The printed circuit board 10 includes a timing controller 8, a power supply circuit (not shown), and a reference gamma voltage generator (not shown) for supplying a reference gamma voltage to each of the data integrated circuits DDe1 to DDon. In addition, the printed circuit board 10 is formed with signal wires that are electrically connected between the respective components.

The image display unit 2 is a liquid crystal cell in which a first data line DLe1 to DLen, which is an even data line, and a second data line DLo1 to DLon, which is an odd data line, and a plurality of gate lines GL are formed to form a matrix. (LC). The image display unit 2 adjusts light transmittance of the even and odd liquid crystal cells LC formed in a matrix form. Each liquid crystal cell LC includes a thin film transistor TFT which is a switching element connected to a crossing point of a plurality of gate lines GL and first and second data lines DLe1 to DLen and DLo1 to DLon. Here, the first data lines DLe1 to DLen receive an analog image signal from the first data integrated circuits DDe1 to DDen. The second data lines DLo1 to DLon receive an analog image signal from the second data integrated circuits DDo1 to DDon. These liquid crystal cells LC are equivalently represented as capacitors and further include a storage capacitor, not shown, in order to keep the charged analog image signal, that is, the charged pixel signal, stably until the next pixel signal is charged. . As described above, the even and odd liquid crystal cells LC display an image by controlling light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through thin film transistors.

The gate integrated circuit GD may include a gate control signal from the timing controller 8, for example, a gate start signal (GSP), a gate shift clock (GSC), and a gate output enable (GOE); The scan pulse is supplied to each gate line GL using a Gate Output Enable) signal. In other words, the gate integrated circuit GD shifts the GSP from the timing controller 8 according to the GSC to sequentially supply the gate high voltage scan pulses to the gate lines GL. The gate low voltage is supplied to the gate lines GL when the scan pulse is not supplied. Here, the gate integrated circuit (GD) controls the pulse width of the scan pulse according to the GOE signal.

The first data integrated circuits DDe1 to DDen are data control signals from the timing controller 8, for example, a source start signal (SSP), a source shift clock (SSC), and a source output signal. The analog image data is supplied to the first data lines DLe1 to DLen which are even data lines by using a source output enable (SOE) signal. In other words, the first data integrated circuits DDe1 to DDen latch the digital image data input according to the SSC and output the line-by-line in response to the SOE signal. In this case, the first data integrated circuits DDe1 to DDen convert the digital image data in line units into analog image data and output the analog image data. In detail, the first data integrated circuits DDe1 to DDen convert the digital image data in a line unit into analog image data by using a gamma voltage from a gamma voltage unit (not shown). Will output Here, the first data integrated circuits DDe1 to DDen determine the polarity of the analog image data in response to a POL (Polarity) signal from the timing controller 8 when converting the digital image data into the analog image data. The first data integrated circuits DDe1 to DDen determine a period in which analog image data is supplied to the even data lines DLe1 to DLen in response to the SOE signal.

Also, like the first data integrated circuits DDe1 to DDen, the second data integrated circuits DDo1 to DDon use the data control signals from the timing controller 8 to form the second data lines DLo1 to DLon which are odd data lines. ) Supplies analog video data. In other words, the second data integrated circuits DDo1 to DDon also latch the digital image data input according to the SSC and output the line-by-line in response to the SOE signal. In this case, the second data integrated circuits DDo1 to DDon convert the digital image data in line units into analog image data and output the analog image data. Specifically, the second data integrated circuits DDo1 to DDon convert the digital image data in line units into analog image data by using the gamma voltage from the gamma voltage unit, and output them to the second data lines DLo1 to DLon. do. Here, the second data integrated circuits DDo1 to DDon determine the polarity of the analog image data in response to the POL signal from the timing controller 8 when converting the digital image data into the analog image data. The second data integrated circuits DDo1 to DDon determine a period in which analog image data is supplied to the second data lines DLeo1 to DLon in response to the SOE signal.

The spread spectrum integrated circuit spreads the frequency of DCLK input from an external system to a spreading range of a preset range to generate SDCLK. Accordingly, the frequency of the gate and data control signals generated by the timing controller 8 is not kept constant, but the period thereof is converted in accordance with the SDCLK. Here, the spread spectrum frequency may be set differently according to the size, use, and driving method of the liquid crystal display. However, in the present invention, only the case where the spread spectrum frequency setting range is set to 100 Hz to 200 Hz will be described.

The timing controller 8 uses synchronization signals such as data enable (DE), a vertical synchronization signal (hereinafter referred to as Vsync), and a horizontal synchronization signal (hereinafter referred to as Hsync) indicating a valid data section input from the outside. Generate gate and data control signals. In other words, the timing controller 8 controls the gate integrated circuit GD and the first and second data integrated circuits DDe1 to DDon using the SDCLK from the spread spectrum integrated circuit and the synchronization signals from the outside. And generate a data control signal. Here, the gate control signal for controlling the gate integrated circuit GD includes GOE, SSP, GSC, and the like, and the data control signal includes SSP, SOE, SSC, POL, and the like.

Hereinafter, a timing controller according to an embodiment of the present invention will be described in more detail with reference to FIG. 2.

2 is a configuration diagram illustrating the timing controller illustrated in FIG. 1, and FIG. 3 is a waveform diagram illustrating synchronization signals, a gate, and a data control signal.

The timing controller 8 illustrated in FIG. 2 is an image processing unit which aligns and outputs image data RGB from the outside to be suitable for driving the liquid crystal panel 4 using synchronization signals such as SDCLK, DE, Vsync, and Hsync. 22, a gate control signal generator 24 which generates a gate control signal GCS to control the gate integrated circuit GD, and generates a data control signal DCS to generate the first and second data integrated circuits. More stable by delaying at least one of the gate and data control signals GCS and DCS by using the data control signal generator 26 for controlling (DDe1 to DDon) and the synchronization signals such as the SDCLK and DE signals. And a delay unit 28 for correcting the control signal.

The image processor 22 arranges the input image data RGB to be suitable for driving the liquid crystal panel 4 and supplies the input image data RGB to the first and second data integrated circuits DDe1 to DDon. In other words, the image processor 22 divides the image data RGB into first data and second data in response to a synchronization signal such as DE or SDCLK. The first data is supplied to the first data integrated circuits DDe1 to DDen, and the second data odd data is supplied to the second data integrated circuits DDo1 to DDon.

The gate control signal generator 24 generates a gate control signal GCS including GSP, GSC, and GOE by using synchronization signals such as SDCLK, DE, Hsync, and Vsync, and supplies them to the gate integrated circuit GD. . At this time, the gate control signal generator 24 generates a GSP indicating the start of a frame based on Vsync, and generates a GSC based on Hsync.

The data control signal generator 26 generates a data control signal DCS including SSP, SSC, POL, and SOE by using synchronization signals such as SDCLK, DE, Hsync, Vsync, and the like. It is supplied to (DDe1 to DDon). At this time, the data control signal generator 26 generates an SSP indicating the start of a line based on the DE signal indicating a valid data period among all the lines, and based on Hsync, the first and second data integrated circuits DDe1. To DDon) to generate an SOE signal.

The delay unit 28 stably corrects the gate control signal GCS and the data control signal DCS generated unstable in accordance with the SDCLK and DE signals. In other words, when control signals such as GSP, GSC, GOE, SSP, SOE, and SSC are generated using the SDCLK, control signals such as GSP, GSC, GOE, SSP, SOE, and SSC are respectively changed according to the spreading frequency of the SDCLK. The generation period of the pulse, the pulse width, and the like become variable.

For example, the SOE and GOE signals are generated by counting SDCLK from the falling edge of the DE signal. At this time, as in the time point T1 of FIG. 5, when the frequency of the SDCLK is generated in a predetermined range or more, for example, 200 Hz or more, the rising time of the SOE signal may be generated at the same time as the falling edge time of the DE. As described above, when the SOE signal is generated before the predetermined period, the pulse width of the SOE signal may be varied or the output period of the first and second image data (even data, odd data) may be varied. Accordingly, the delay unit 28 corrects an unstable state in which generation periods, pulse widths, and the like of each of the control signals GCS and DCS, such as GSP, GSC, GOE, SSP, SOE, and SSC, vary according to the frequency variation of the SDCLK. Done.

In other words, the delay unit 28 stably corrects each control signal GCS and DCS by counting synchronization signals such as DE and SDCLK and delaying each control signal GCS and DCS. For example, in the case of the SOE signal of the data control signal DCS, a delay source output enable (DSOE) signal may be generated by delaying a predetermined time period using a synchronization signal such as DE or SDCLK.

In addition, the delay unit 28 may delay other control signals by using at least one control signal among the gate and data control signals GCS and DCS instead of the synchronization signals such as DE and SDCLK. For example, when delaying the SOE signal from the data control signal generator 28, the SSC may be counted and delayed rather than the synchronization signal such as DE and SDCLK.

4 is a configuration diagram illustrating a delay unit illustrated in FIG. 2, and FIG. 5 is a waveform diagram illustrating input / output signals of the delay unit illustrated in FIG. 4.

The delay unit 28 shown in FIG. 4 includes a detector 32 for generating a detection signal Q whose logic state is inverted according to the DE signal from the outside and the SOE signal from the data control signal generator 26; A first counter 34 for generating the first delay signal K by delaying the detection signal Q by counting the SDCLK from the spread spectrum integrated circuit and counting the SDCLK; The second counter 36 generates a second delay signal L by delaying the delay signal K, and generates a DSOE signal having a high or low logic state according to the first and second delay signals K and L. It includes an XOR gate (Exclusive OR Gate, 38).

The detector 32 may include a first input terminal for receiving a DE signal, a second input terminal for receiving an SOE signal from the data control signal generator 26, and a detection signal whose logic state is inverted according to the DE signal and the SOE signal. An output terminal for outputting (Q) is provided. Here, the NOT gate NG is further provided at the first input terminal.

The low section of the DE signal input to the NOT gate NG is a blank section, and the high section of the DE signal is a valid data section. However, in the present invention, since the NOT gate NG is provided at the input terminal of the DE signal, the signal input to the detector 32 refers to a signal in which a valid data section and a blank section are reversed, that is, a logic state is inverted.

 Accordingly, the first input terminal receives a DE signal in which a logic state is inverted, that is, inverted to a high or low state, in units of a horizontal line or a frame. The logic state is alternately inverted, i.e., a high or low state, every time the DE signal and the SOE signal are synchronized with the SOE signal input to the second input terminal, that is, when the DE state and the SOE signal are synchronized with the high or low logic state, such as the time point T1. The detection signal Q is generated so as to be inverted.

 Here, the detection unit 32 may be a control element such as a D-flip flop, an SR-flip flop, a JK flip flop, a switching element, or the like.

The first counter 34 counts the first input terminal for receiving the detection signal Q, the second input terminal for receiving the SDCLK, and the SDCLK, and delays the detection signal Q by a counted period to delay the first delay signal. Counter circuit including an output terminal for outputting (K). The first counter 34 counters the SDCLK input to the second input terminal every time when the logic state of the detection signal Q input from the detector 32 is inverted, that is, every time T1. The detection signal Q is delayed by the counted period T2 to output the first delay signal K. FIG. At this time, the period T2 for counting the SDCLK may be set in advance by a double number of clocks. For example, if it is set to count eight falling edges of the SDCLK, the first counter 34 counts eight SDCLKs and counts eight each time the logic state of the detection signal Q is inverted (T1). The first delayed signal K delayed during T2 is output. At this time, the first delay signal K is simultaneously supplied to the second counter 36 and the XOR gate 38. In this case, the eight SDCLKs are counted so that the rising time of the DSOE signal is not synchronized with the falling edge of the DE signal and is generated in the blank period of the DE signal in a high state. It can be changed and set according to the section or the blank section.

The second counter 36 counts the first input terminal receiving the first delay signal K, the second input terminal receiving the SDCLK and the SDCLK, and delays the first delay signal K by the counted period. The counter circuit may include an output terminal for outputting the second delay signal L. FIG. The second counter 36 counts the SDCLK input to the second input terminal whenever the logic state of the first delay signal K is inverted to a high or low state (T3). The second delay signal L is delayed by delaying the first delay signal K by the counted period T4. At this time, the period T4 for counting the SDCLK may be set in advance by a double number of clocks. For example, if it is set to count eight falling edges of the SDCLK, the second counter 36 counts eight SDCLKs and counts eight each time the logic state of the first delay signal K is reversed. The second delayed signal L delayed during T4) is supplied to the XOR gate 38. Here, the eight SDCLKs are counted so that the DSOE signal is not synchronized with the falling edge of the DE signal and is generated in the blank period of the DE signal in a high state. The count period of the SDCLK is valid for the data of the DE signal. It can change and set according to period or blank period.

The XOR gate 38 has first and second input terminals to which the first and second delay signals K and L are input, respectively, and logic states of the first and second delay signals K and L are mutually different. An output terminal for outputting a high state DSOE signal for another period T4 is provided. That is, the XOR gate 38 outputs a high state DSOE signal when the logic states of the signals input to the first and second input terminals are different from each other. When the logic states of the signals input to the first and second input terminals are the same, the DSOE signal in the low state is output. Accordingly, the period T4 during which the DSOE signal in the high state is generated is a period in which the second delay signal L is delayed from the first delay signal K, that is, a period in which the second counter 36 counts eight SDCLKs ( Same as T4).

The delay unit 28 according to the embodiment of the present invention uses a configuration and operation method as described above, for example, among the gate and data control signals (GCS, DCS), for example, GSP, GSC, GOE, SSP, SOE, SSC. At least one signal may be delayed. In addition, in the present invention, only the delay unit 28 is described in the timing controller 8, but the delay unit 28 may be configured outside the timing controller 8. In addition, a plurality of delay units 28 may be provided to correspond to the number of control signals to be corrected in the manner described above. In addition, the present invention has been described that only counting the SDCLK, but may be delayed by counting signals such as SSC, GSC, POL according to the control signal to be delayed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving apparatus and the driving method thereof of the liquid crystal display according to the exemplary embodiment of the present invention have the following effects.

That is, the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention can stably correct the scattering dot clock generated by using the spread spectrum method to delay the unstable control signals.

In addition, it is possible to prevent the display failure of the screen displaying the image data by correcting the control signal generated unstable according to the variable spreading frequency as described above.

Claims (22)

A liquid crystal panel including an image display unit for displaying an image; A gate and a data integrated circuit driving the liquid crystal panel; A timing controller which generates a gate and data control signal using an external synchronization signal and delays at least one control signal of the gate and data control signal according to an external synchronization signal; And And a spread spectrum integrated circuit for generating a spread dot clock by spreading the frequency of the dot clock among the synchronization signals according to a spread spectrum method, and supplying the spread dot clock to the timing controller. Device. delete The method of claim 1, The timing controller An image processor for arranging digital image data from an outside and outputting the digital image data to the data integrated circuit; A gate control signal generation unit generating the gate control signal to control the gate integrated circuit; A data control signal generation unit generating the data control signal to control the data integrated circuit; And a delay unit for delaying at least one control signal among the gate and data control signals using the synchronization signal to supply the gate and data integrated circuits to correct the control signal. . The method of claim 3, wherein The delay unit A detector for generating a detection signal according to the synchronization signal and the gate or data control signal; A first counter which counts the diffusion dot clock and delays the detection signal by a counted period to generate a first delay signal; A second counter for counting the diffusion dot clock and delaying the first delay signal by a counted period to generate a second delay signal; And an XOR gate for generating a control signal corrected according to the logic states of the first and second delay signals. 5. The method of claim 4, The detection unit A first input terminal receiving the synchronization signal; A second input terminal for receiving the gate and data control signal, and And a flip-flop device which inverts and outputs a detection signal in a high or low state according to a result of comparing and comparing a logic state of the synchronization signal with the gate and data control signals. 6. The method of claim 5, The detection unit And a NOT gate for inverting a logic state of the synchronization signal input to the first input terminal. 6. The method of claim 5, The first counter is A first input terminal receiving the detection signal; A second input terminal configured to receive the diffusion dot clock; And a counter circuit including an output terminal outputting the first delayed signal by delaying the detection signal by a counted period when the logic state of the detection signal is inverted. Drive of the device. The method of claim 7, wherein The second counter A first input terminal receiving the first delay signal; A second input terminal configured to receive the diffusion dot clock; And a counter circuit including an output terminal for outputting the second delay signal by delaying the first delay signal by a counted period by counting the diffusion dot clock when the logic state of the first delay signal is inverted. Driving device of the liquid crystal display device. 9. The method of claim 8, The synchronization signal is And at least one of a data enable signal, a diffuse dot clock, a vertical synchronization signal, and a horizontal synchronization signal. The method of claim 9, The gate control signal And at least one of a gate start pulse, a gate shift clock, and a gate output enable signal. 11. The method of claim 10, The data control signal is And at least one of a source output enable, a source start pulse, a source shift clock, and a polarity control signal. The method of claim 1, The data integrated circuit First data integrated circuits supplying even image data to first data lines of the liquid crystal panel; And second data integrated circuits supplying odd image data to second data lines of the liquid crystal panel. 13. The method of claim 12, The liquid crystal display device A printed circuit board having a power circuit mounted thereon; A plurality of data tape carrier packages on which the first and second data integrated circuits are mounted and attached between the printed circuit board and the liquid crystal panel, respectively; And a plurality of gate tape carrier packages on which the gate integrated circuit is mounted and attached to the liquid crystal panel. Generating a diffused dot clock by diffusing a frequency of a dot clock among synchronization signals from the outside; Generating a gate and data control signal using the synchronization signal including the diffusion dot clock; And And delaying and outputting at least one control signal among the gate and data control signals according to the synchronization signal. 15. The method of claim 14, Delaying and outputting at least one control signal of the gate and data control signals Generating a detection signal according to the synchronization signal and the gate or data control signal; Counting the diffusion dot clock of the synchronization signals and delaying the detection signal by a counted period to generate the first delayed signal; Counting the diffusion dot clock to delay the first delay signal by a counted period and generating the second delay signal as a second delay signal; And generating a control signal corrected according to the logic states of the first and second delay signals. 16. The method of claim 15, Generating the detection signal Receiving the synchronization signal; Receiving the gate and data control signals; And inverting the detection signal to a high or low state according to a result of comparing the synchronous signal with the logic states of the gate and data control signals, and outputting the detected signal in a high or low state. 16. The method of claim 15, Generating the detection signal And inverting the logic state of the synchronization signal to receive the input signal. The method of claim 17, The generating of the first delay signal may include Receiving the detection signal; Receiving the diffusion dot clock; And counting the diffusion dot clock at a time when the logic state of the detection signal is inverted and delaying the detection signal by the counted period to output the first delayed signal as the first delayed signal. Driving method. The method of claim 18, Generating the second delay signal Receiving the first delay signal; Receiving the diffusion dot clock; And counting the diffusion dot clock at the time when the logic state of the first delay signal is inverted, delaying the first delay signal by the counted period, and outputting the second delay signal as the second delay signal. Method of driving display device. 20. The method of claim 19, The synchronization signal is And at least one of a data enable signal, a diffuse dot clock, a vertical synchronization signal, and a horizontal synchronization signal. 21. The method of claim 20, The gate control signal And at least one of a gate start pulse, a gate shift clock, and a gate output enable signal. 22. The method of claim 21, The data control signal is And at least one of a source output enable, a source start pulse, a source shift clock, and a polarity control signal.

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