KR102465513B1 - Display device - Google Patents

Abstract

According to the present invention, the image state is determined based on image pattern state information updated in the memory immediately before power-off before power-on, and when it is determined as a worst pattern, the horizontal 1-dot inversion method is changed to the horizontal 2-dot inversion method by executing the DPMC algorithm. can be converted to and driven. Generation of a swing pulse of a common voltage due to excessive data transition between data supplied to the display panel by such driving may be blocked or minimized. Accordingly, the voltage drop of the reference voltage is prevented, and thus, an abnormal operation of the display panel or image quality deterioration such as screen flickering can be prevented.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device capable of preventing image quality deterioration.

A display device is a device that displays an image or information. Among display devices, a liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field.

In the liquid crystal display device, a gate signal from a gate driver and a data voltage from the data driver are supplied to the liquid crystal display panel based on a timing control signal provided from a timing controller, and an image is displayed.

Various voltages to drive various components included in the liquid crystal display device or to be used for various components are generated in the power supply unit.

The power supply generates a reference voltage VCC and a common voltage Vcom. The reference voltage VCC is used to drive each of the timing controller, the gate driver, and the data driver. The common voltage Vcom is applied to the common line of the liquid crystal display panel.

In addition, the power supply generates a reference voltage VDD, a gate high voltage VGH, and a gate low voltage VGL. The reference voltage is used to generate a gamma voltage, and the generated gamma voltage is supplied to the data driver. The gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver and sequentially supplied to each gate line of the liquid crystal display panel.

The reference voltage VDD, the common voltage Vcom, the gate high voltage VGH, and the gate low voltage VGL are generated using the reference voltage VCC. Accordingly, the reference voltage VCC is very sensitive to variations in the reference voltage VDD, the common voltage Vcom, the gate high voltage VGH, and the gate low voltage VGL.

When an image frame including grayscale data for each pixel is displayed on the liquid crystal display panel, frequent data transition occurs because grayscale data for each pixel is different.

In this case, an image pattern in which data transitions frequently occur is called a worst pattern, and an image pattern in which data transitions do not occur frequently is called a normal pattern.

If the power-on operation is performed in the worst image pattern, an image according to the worst image pattern is displayed on the liquid crystal display panel. In this case, a significant swing pulse is generated in the common voltage Vcom supplied to the liquid crystal display panel due to frequent data transition due to the worst image pattern at the time when an image is displayed. This may be due to the common line being placed intersecting the data line. The current consumption increases due to the swing pulse of the common voltage Vcom.

Accordingly, a temporary voltage drop occurs in the reference voltage VCC used to generate the common voltage Vcom in the power supply unit due to an increase in current consumption due to the swing pulse of the common voltage Vcom. Due to the voltage drop of the reference voltage VCC, the timing controller, the gate driver, and the data driver driven by the reference voltage VCC are not driven normally, and thus image quality is deteriorated.

In addition, when the reference voltage (VCC) falls below the UVLO (Under-Voltage Lock-Out) voltage due to the voltage drop of the reference voltage (VCC), it is determined that the power is OFF and the power to each component is cut off. Defects such as momentary screen flickering may occur.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems.

Another object of the present invention is to provide a display device capable of preventing image quality deterioration by preventing a voltage drop of a reference voltage.

According to one aspect of the present invention to achieve the above or other objects, a display device includes a display panel for displaying an image including a plurality of image frames, and controlling the gate driver and the data driver, and image pattern state for each image frame. It includes a timing controller for generating information, and a memory in which the generated image pattern state information is updated. When the power is turned on after the power is turned off, the controller breaks the image pattern based on the image pattern state information updated in the memory, and when the image pattern is a worst pattern, executes a DPMC (Dynamic Power Mode Control) algorithm make it This configuration blocks or minimizes the swing pulse of the common voltage due to excessive data transition and prevents the reference voltage (VCC) from dropping due to excessive current consumption by the swing pulse of the common voltage, thereby preventing abnormal operation of the display panel. It is possible to prevent image quality defects such as screen flickering or screen flickering.

The effect of the display device according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, when the image pattern is determined to be a worst image pattern based on image pattern state information updated in the memory immediately before power-off, the DPMC algorithm may be executed at or before the time the image is displayed. . By driving the DPMC algorithm, the horizontal one-dot inversion method is converted into the horizontal two-dot inversion method and driven, so that even if data transition occurs, the swing pulse is minimized or not generated at the common voltage supplied to the common line. Due to the remarkably reduced current consumption, the voltage drop of the reference voltage VCC used to generate the common voltage Vcom does not occur or is minimized. Poor image quality such as momentary screen flickering can be prevented.

According to at least one of the embodiments of the present invention, the gate high voltage VGH or the data voltage may not be supplied to the liquid crystal display panel for several frames from the time of displaying the image. Due to this operation, the voltage drop of the reference voltage VCC is suppressed by minimizing or blocking the generation of the swing pulse of the common voltage due to the data transition of the image data. Accordingly, image quality defects such as abnormal driving of the liquid crystal display panel or screen flickering can be prevented.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments such as preferred embodiments of the present invention are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention may be clearly understood by those skilled in the art.

1 is a waveform diagram showing a state in which a voltage drop of a reference voltage VCC occurs in the related art.
2 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.
3A is a diagram illustrating a horizontal 1-dot inversion method, and FIG. 3B is a diagram illustrating a horizontal 2-dot inversion method.
4 is a waveform diagram illustrating a state in which a VCC voltage drop is prevented in a liquid crystal display according to an embodiment of the present invention.
5 is a flowchart illustrating a control method of a liquid crystal display according to a first embodiment of the present invention.
6 is a waveform diagram illustrating a control method of a liquid crystal display according to a second embodiment of the present invention.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

2 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 2 , the liquid crystal display according to the present invention includes a timing controller 10 , a memory 20 , a gate driver 30 , a data driver 40 , a liquid crystal display panel 50 , and a power supply unit 60 . include

Other components other than the components shown in FIG. 2 may be further added, but the present invention is not limited thereto.

The power supply unit 60 may be used for the timing control unit 10 , the gamma generation unit, the gate driver 30 , and the data driver 40 , or may generate voltages for driving each of these components.

The power supply unit 60 may generate, for example, at least one or more reference voltages VCC and VDD, a common voltage Vcom, a gate high voltage VGH, or a gate low voltage VGL. The power supply unit 60 may further generate voltages for driving each component, but is not limited thereto.

The reference voltage VDD, the common voltage Vcom, the gate high voltage VGH, or the gate low voltage VGL may be generated based on the reference voltage VCC. That is, the reference voltage may be boosted to generate the reference voltage VDD, the gate high voltage VGH, or the gate low voltage VGL. When the common voltage Vcom is greater than the reference voltage VCC, the common voltage Vcom may be generated by boosting the reference voltage VCC. When the common voltage Vcom is less than the reference voltage VCC, the common voltage Vcom may be generated by reducing the reference voltage VCC.

The gate high voltage VGH may be generated based on the reference voltage VDD, but is not limited thereto.

For example, the reference voltage VCC is supplied to the timing controller 10 , the gate driver 30 and the data driver 40 , and the timing controller 10 , the gate driver 30 and the data driver 40 are supplied by the reference voltage VCC. 40) can be driven.

For example, the reference voltage VDD may be supplied to a gamma generator (not shown) to generate a plurality of gamma voltages based on the reference voltage VDD.

For example, the gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver 30 , and the gate high voltage is sequentially supplied to the liquid crystal display panel 50 in units of one horizontal section from the gate driver 30 . can be The gate high voltage VGH is supplied on the corresponding gate line of the liquid crystal display panel 50 for one horizontal period in one frame, and the gate low voltage VGL is supplied on the corresponding gate line of the liquid crystal display panel 50 during the remaining period. This can be supplied.

The timing controller 10 may be driven by the reference voltage VCC supplied from the power supply unit 60 . When the timing controller 10 is driven, the timing controller 10 may generate a gate control signal and a data control signal based on various control signals Vsync, Hsync, CLK, and DE received from the outside. The gate control signal may be supplied to the gate driver 30 , and the data control signal may be supplied to the data driver 40 . The timing controller 10 may also receive an RGB image signal from the outside. The RGB image received by the timing controller 10 may be supplied to the data driver 40 after data alignment or data processing is performed.

The gamma generator may generate a plurality of gamma voltages based on the reference voltage VDD supplied from the power supply unit 60 . The gamma voltage may be supplied to the data driver 40 .

The gate driver 30 may be driven by the reference voltage VCC supplied from the power supply unit 60 . When the gate driver 30 is driven, the gate driver 30 receives a gate high voltage VGH or a gate low voltage VGL supplied from the power supply unit 60 in response to a gate control signal supplied from the timing control unit 10 . may be supplied to the liquid crystal display panel 50 .

The data driver 40 may be driven by the reference voltage VCC supplied from the power supply unit 60 . When the data driver 40 is driven, the data driver 40 uses a plurality of gamma voltages supplied from the gamma generator in response to the data control signal supplied from the timing controller 10 to generate a data voltage corresponding to the RGB image signal. may be supplied to the liquid crystal display panel 50 .

The liquid crystal display panel 50 may include two substrates and a plurality of liquid crystals interposed between the substrates. A plurality of gate lines and data lines crossing each other may be disposed on one of these substrates, and a thin film transistor may be connected to each of the gate lines and the data lines. A pixel electrode may be connected to the thin film transistor. A pixel area may be defined by the intersection of the gate line and the data line.

A common line may be disposed parallel to each gate line. Each common line may be connected to a common electrode bar disposed on an outer edge of the substrate on which the gate line is disposed. Accordingly, when the common voltage Vcom is directly supplied to the common electrode, the common voltage Vcom may be applied to each common line.

When the gate high voltage VGH is supplied from the gate driver 30 to the gate line, the thin film transistor of each pixel area connected to the gate line may be turned on by the gate high voltage VGH. In this case, the data voltage supplied from the data driver 40 to the plurality of data lines of the liquid crystal display panel 50 may be applied to the corresponding pixel electrode through each thin film transistor.

A common voltage Vcom generated from the power supply unit 60 may be applied to each common line of the liquid crystal display panel 50 .

Accordingly, the liquid crystals interposed between the substrates are displaced by the potential difference between the common voltage Vcom applied to each common line and the data voltage applied to each pixel electrode, so that the amount of light transmission is adjusted, so that an image can be displayed. The grayscale may vary depending on the amount of light transmitted.

According to the present invention, the timing controller 10 continuously stores the pattern state of the image frame displayed on the liquid crystal display panel 50 as image pattern state information in the memory 20 before the power is turned off or until the power is turned off. can be updated.

As will be described later, since the DPMC algorithm must be executed at or before the time of displaying the image, the image pattern state information used to determine whether to execute the DPMC algorithm must be updated in the memory before power-off.

The image pattern state information may be, for example, a 1-bit binary data signal, but is not limited thereto. For example, when the image pattern state information is a normal image pattern, a low level signal, for example, “0” may be updated in the memory 20 . For example, when the image pattern state information is a worst image pattern, a high level signal, for example, “1” may be updated in the memory 20 .

Conversely, the normal image pattern may be updated with a high level signal and the worst image pattern may be updated with a low level signal, but the present invention is not limited thereto.

The worst image pattern and the normal image pattern may be determined based on the number of data transitions. For example, when data transition occurs in, for example, 70% or more of the total pixels of the image frame, the corresponding image frame may be determined as a worst image pattern. For example, when data transition occurs in, for example, 70% or less of the total pixels of the image frame, the corresponding image frame may be determined as a normal image pattern. A reference value for the number of data transitions for determining the normal image pattern and the worst image pattern may be variable.

Accordingly, when the power is turned off, image pattern state information for the last image frame immediately before the power is turned off is stored in the memory 20 .

In the last image frame, the data driver ( 40), but is not limited thereto.

When the power is turned on, the reference voltage VCC is generated from the power supply unit 60, and the timing controller 10, the gate driver 30, and the data driver 40 are driven by the generated reference voltage VCC. can

When the timing controller 10 is driven, the timing controller 10 determines the pattern state of the last image frame by referring to image pattern state information of the last image frame immediately before power-off stored in the memory 20 .

When the pattern state of the last image frame is determined to be a worst image pattern, the timing controller 10 drives a DPMC (Dynamic Power Mode Control) algorithm to control the image to be displayed on the liquid crystal display panel 50 according to the DPMC algorithm. have.

The horizontal 1-dot inversion method may be converted into a horizontal 2-dot inversion method by the DPMC algorithm and may be driven.

For example, when the liquid crystal display panel 50 is currently driven in the horizontal 1-dot inversion scheme, when the DPMC algorithm is executed, the horizontal 1-dot inversion scheme may be changed to the horizontal 2-dot inversion scheme and may be driven.

The common voltage Vcom applied to the common line arranged parallel to the gate line is affected by the number of data transitions between data lines connected to each pixel area on the gate line, so that a swing pulse may be generated.

As shown in FIG. 3A , when driving in the horizontal one-dot inversion method, the first common line is disposed parallel to the first gate line, and the first to sixth pixel regions are connected on the first gate line. can

In this case, a positive (+) data voltage may be applied to the first pixel region connected to the first data line, and a negative (-) data voltage may be applied to the second pixel region connected to the second data line. . A positive (+) data voltage may be applied to the third pixel region connected to the third data line, and a negative (−) data voltage may be applied to the fourth pixel region connected to the fourth data line. A positive (+) data voltage may be applied to the fifth pixel region connected to the fifth data line, and a negative (−) data voltage may be applied to the sixth pixel region connected to the sixth data line.

Five data transitions may occur between the first to sixth pixel regions connected on the first gate line. Accordingly, the common voltage Vcom applied to the first common line parallel to the first gate line is affected by the data voltage at which data transitions occur 5 times, and a swing pulse may be generated due to 5 times of data transitions. .

On the other hand, as illustrated in FIG. 3B , when driving in the horizontal two-dot inversion method, data transfer may occur twice between the first to sixth pixel regions connected on the first gate line. Accordingly, the common voltage Vcom applied to the first common line parallel to the first gate line is affected by the data voltage at which two data transitions occur, and a swing pulse may be generated due to the two data transitions. .

Accordingly, when the horizontal 2-dot inversion method is used, the number of data transitions is remarkably reduced, so that the swing pulse of the common voltage Vcom is minimized or not generated.

As shown in FIG. 4 , the DPMC algorithm is executed at or before an image is displayed, and the horizontal 1-dot inversion scheme is converted into the horizontal 2-dot inversion scheme. An image according to the horizontal 2-dot inversion method converted as described above may be displayed. Accordingly, no swing pulse is generated in the common voltage Vcom applied to the common line disposed parallel to the gate line of the liquid crystal display panel 50, and a voltage drop of the reference voltage VCC due to the swing pulse occurs. it won't happen

In summary, by converting the horizontal one-dot inversion method into the horizontal two-dot inversion method at or before the time when the image is displayed, data transfer between each pixel area in the horizontal direction can be remarkably reduced. As the data transition is reduced, the swing pulse of the common voltage Vcom applied to the common line may not be generated or may be minimized. When the swing pulse of the common voltage Vcom is minimized, the current consumption is reduced as much as the swing pulse of the common voltage Vcom is minimized. The voltage drop of the reference voltage VCC used to generate the common voltage Vcom does not occur or is minimized due to the reduction in current consumption, so that the liquid crystal display panel 50 is abnormally driven or the liquid crystal display panel 50 is not driven. ), such as momentary screen flickering, can be prevented.

In the present invention, the description is limited to converting the horizontal 1-dot inversion method to the horizontal 2-dot inversion method by driving the DPMC algorithm. It is possible.

In addition, according to the present invention, it is possible to simultaneously convert the horizontal 2 dot inversion method to the vertical 2 dot or more vertical dot inversion method.

5 is a flowchart illustrating a control method of a liquid crystal display according to a first embodiment of the present invention.

1 and 5, when the power button is pressed for viewing an image or a power-on signal is received from a remote controller (S111), various voltages generated by the power supply unit 60 ( VCC, VDD, Vcom, VGH, VGL) are applied to each component, that is, the timing controller 10 , the gate driver 30 , the data driver 40 and the liquid crystal display panel 50 , and each component is driven can be operated. Accordingly, an image may be displayed on the liquid crystal display panel 50 (S113).

The timing controller 10 may generate image pattern state information based on an image frame received from the outside and update it in the memory 20 ( S115 ). Image pattern state information may be generated based on the number of data transitions between pixels included in the image frame.

For example, when the number of data transitions between each pixel included in the image frame is less than or equal to the reference value, it is determined as a normal image pattern and a low-level signal, for example, “0”, may be stored or updated in the memory 20 as image pattern state information. .

For example, when the number of data transitions between pixels included in the image frame is less than or equal to the reference value, the worst image pattern is determined and a high level signal, for example, “1”, may be stored or updated in the memory 20 as image pattern state information. .

When viewing of the image is completed and the power button is pressed or a power-off signal is received from the remote controller (S117), the power cut-off unit (not shown) included in the power supply unit 60 is powered off, that is, It is determined whether the reference voltage VCC is equal to or less than the UVLO (Under-Voltage Lock-Out) voltage, and when the power is off, each component, that is, the timing controller 10 , the gate driver 30 , the data driver 40 and the liquid crystal The supply of various voltages VCC, VDD, Vcom, VGH, and VGL supplied to the display panel 50 may be cut off.

Accordingly, the display of the image on the image display panel may be blocked (S119).

Then, when the power button is pressed or a power-on signal is received from the remote controller to view the image (S121), various voltages (VCC, VDD, Vcom, VGH) generated by the power supply unit 60 are , VGL) is applied to each component, that is, the timing controller 10 , the gate driver 30 , the data driver 40 , and the liquid crystal display panel 50 , so that each component can be driven and operated.

When the timing controller 10 is driven, the timing controller 10 may retrieve the updated image pattern state information from the memory 20 (S123).

The updated image pattern state information may be image pattern state information about the last image frame just before power is turned off.

In the last image frame, the data driver ( 40), but is not limited thereto.

The timing controller 10 may determine whether it is a worst image pattern based on the image pattern state information read from the memory 20 ( S125 ).

When the read image pattern state information has a low level signal, it may be determined as a normal image pattern. When the read image pattern state information has a high level signal, it may be determined as a worst image pattern.

If it is determined as the worst image pattern, the timing controller 10 may execute the DPMC algorithm (S127).

The horizontal 1 dot inversion method is converted to the horizontal 2 dot inversion method by the DPMC algorithm, and an image may be displayed on the liquid crystal display panel 50 by the converted horizontal 2 dot inversion method.

The DPMC algorithm may be executed at or before the time when the image is displayed on the liquid crystal display panel 50 . More specifically, the DPMC algorithm may be executed when the timing controller 10 transmits image data to be displayed on the liquid crystal display panel 50 to the data driver 40 .

The timing controller 10 may control the data driver 40 according to the execution of the DPMC algorithm to supply image data to the liquid crystal display panel 50 in a horizontal 2-dot inversion method. Accordingly, an image driven according to the DPMC algorithm may be displayed on the liquid crystal display panel 50 (S129). Accordingly, as the data voltage is supplied to the liquid crystal display panel in the horizontal 2-dot inversion method, the number of data transitions is minimized and no swing pulse of the common voltage is generated. Voltage drop can be prevented.

Here, the horizontal 2-dot inversion method is only an example, and the present invention is applicable to, for example, a horizontal 3-dot inversion method or a higher horizontal dot inversion method.

In addition, the present invention can be applied to a vertical two-dot inversion method or a higher vertical dot inversion method at the same time as a horizontal two-dot inversion method.

On the other hand, if it is a normal image pattern as a result of determination based on the image pattern state information read from the memory 20, the DPMC algorithm is not applied (S131). Accordingly, an image having a normal image pattern may be displayed on the liquid crystal display panel 50 according to the horizontal 1-dot inversion method. Accordingly, since the swing pulse of the common voltage is not large when the number of data transitions is small, the image may be driven by the currently driven horizontal 1-dot inversion method without having to be driven by the horizontal 2-dot inversion method.

Although not shown, even after being powered on ( S121 ), the image pattern state information for the corresponding image frame may be updated in the memory 20 until the power is turned off.

Although not shown, when the horizontal 1 dot inversion method is converted to the horizontal 2 dot inversion method by the DPMC algorithm due to the worst image pattern, the horizontal 2 dot inversion method is horizontally 1 when it is powered off and then powered on again It may be converted using a dot inversion method. In this case, when the power is turned on later, the current horizontal 2 dot inversion method is driven as it is, or the horizontal 2 dot inversion method is driven in the horizontal 1 dot inversion method according to the image pattern state information updated in the memory immediately before the power is turned off. it might be For example, as a result of checking the updated image pattern state information just before the power is turned off, in the case of a normal image pattern, the currently driven horizontal 2-dot inversion scheme may be converted into the horizontal 1-dot inversion scheme. For example, as a result of checking the updated image pattern state information just before the power is turned off, in the case of the worst image pattern, the currently driven horizontal two-dot inversion method may be driven as it is.

According to the first embodiment of the present invention, the image pattern state information updated in the memory 20 just before the power off is read when the power is turned on. When the image pattern is determined to be a worst image pattern based on the image pattern state information, the DPMC algorithm is executed at or before the time the image is displayed. By driving the DPMC algorithm, the horizontal 1 dot inversion method is converted into the horizontal 2 dot inversion method, and an image can be displayed using the converted horizontal 2 dot inversion method. As the image is driven in the horizontal two-tod inversion method, even if data transition occurs, the swing pulse is minimized or not generated at the common voltage supplied to the common line, thereby dramatically reducing current consumption. Due to the remarkably reduced current consumption, the voltage drop of the reference voltage VCC used to generate the common voltage Vcom does not occur or is minimized, so that abnormal driving of the liquid crystal display panel 50 or the liquid crystal display panel Image quality defects such as momentary screen flickering at (50) can be prevented.

6 is a waveform diagram illustrating a control method of a liquid crystal display according to a second embodiment of the present invention.

A second embodiment of the present invention will be described with reference to FIGS. 1 and 6 .

In the second embodiment of the present invention, image pattern state information is not updated in the memory 20 unlike the first embodiment of the present invention.

In the second embodiment of the present invention, the gate driver 30 does not supply the gate high voltage VGH to the liquid crystal display panel 50 or the data driver 40 By preventing the voltage from being supplied to the liquid crystal display panel 50 , when the data voltage is applied to the liquid crystal display panel 50 from the time of displaying an image, the data voltage supplied through the data lines of the liquid crystal display panel 50 is It is possible to prevent a swing pulse from being generated in the common voltage applied to the common line due to the data transition.

The gate driver 30 does not supply the gate high voltage VGH to the liquid crystal display panel 50 and the data driver 40 does not supply the data voltage to the liquid crystal display panel 50 is either one or can be operated simultaneously.

For example, if the gate driver 30 does not supply the gate high voltage VGH to the liquid crystal display panel 50 , the thin film transistor connected to each pixel region of the liquid crystal display panel 50 does not turn on, and the data driver Even if the data voltage is supplied in step (40), the data voltage is not supplied to each pixel region of the liquid crystal display panel, so that data transition between the respective pixel regions does not occur.

For example, if the data driver 40 does not supply the data voltage to the liquid crystal display panel 50 , the data voltage is not supplied to each pixel region of the liquid crystal display panel 50 , and thus data transition occurs between each pixel region. it won't happen

As shown in the waveform diagram of the vertical synchronization signal Vsync, a plurality of image data may be input to the timing controller 10 in units of frames when power is turned on. After the image data in units of frames is aligned in the timing controller 10 , it may be transmitted to the data driver 40 .

When the power is turned on, for example, after 2 to 5 frames (shown as 3 frames in FIG. 6 ) pass, the image data aligned from the timing controller 10 is transmitted to the data driver 40 , and this time is defined as the image display time. can

The timing controller 10 receives gate control signals (GSP, GSC, GOE) to be supplied to the gate driver 30 and data control signals (SSP, SSC, SOE, POL, etc.) to be supplied to the data driver 40 . can create

These gate control signals GSP, GSC, and GOE may be transmitted to the gate driver 30 from an image display time. The data control signals (SSP, SSC, SOE, POL, etc.) may be transmitted to the data driver 40 from an image display time.

The gate start pulse (GSP) signal is a signal for controlling a start time of an image of one frame and may be generated in units of frames from an image display time.

The gate shift clock (GSC) signal is a signal for controlling the generation time of the gate high voltage VGH to be supplied to each gate line of the liquid crystal display panel 50 , and is a signal for controlling each gate line of the liquid crystal display panel 50 within one frame. number can be created.

The gate output enable signal GOE is a signal for controlling the output of the gate driver 30 and may control the output of the gate high voltage VGH generated in response to each gate shift clock GSC.

As shown in FIG. 6 , the gate high voltage VGH generated by the gate driver 30 due to the high-level gate output enable (GOE) signal for, for example, 3 frames from the time of displaying the image is generated by the liquid crystal display panel 50 . will not be supplied with The gate high voltage VGH may be supplied to the liquid crystal display panel 50 when the gate output enable signal GOE is at a low level.

For convenience of description, it is described with three frames, but the present invention is not limited thereto.

As described above, the gate high voltage VGH is not supplied to the liquid crystal display panel 50 for 3 frames from the time of displaying the image, and the thin film transistor connected to the gate line of the liquid crystal display panel 50 is turned off and the data driver ( 40) is not transferred to each pixel area on the gate line. Accordingly, as the generation of a swing pulse of the common voltage due to excessive data transition due to the supply of image data is minimized, the voltage drop of the reference voltage VCC is suppressed, thereby preventing abnormal driving and image quality deterioration such as screen flickering. .

Since the gate output enable (GOE) signal periodically changes from the high level to the low level after 3 frames have passed from the time of displaying the image, whenever the gate output enable (GOE) has a low level, the gate high voltage (VGH) may be supplied to the liquid crystal display panel 50 . In response to the gate high voltage VGH supplied to the liquid crystal display panel 50 , the thin film transistor of each pixel region is turned on, and the data voltage supplied from the data driver 40 is applied to each pixel region, thereby causing the liquid crystal display panel 50 . An image may be displayed on the screen.

Meanwhile, the data control signals (SSP, SSC, SOE, POL, etc.) may also be transmitted from the timing controller 10 to the data driver 40 from an image display time.

The source start pulse (SSP) signal is a signal for controlling the start time of data for one line and may be generated as many as the number of gate lines of the liquid crystal display panel 50 .

The source shift clock (SSC) signal is a signal for controlling each shift of data for one line and may be generated as many as the number of data lines of the liquid crystal display panel 50 .

The source output enable (SOE) signal is a signal for controlling the output of the data driver 40 and may control the output of the data voltage.

As shown in FIG. 6 , the data voltage is not supplied from the data driver 40 to the liquid crystal display panel 50 due to the source output enable (SOE) signal of the high level signal for, for example, 3 frames from the time of displaying the image. .

For convenience of description, it is described with three frames, but the present invention is not limited thereto.

As such, the data voltage is not supplied to the liquid crystal display panel 50 for three frames from the time of displaying the image, and thus the data voltage is not applied to each pixel region of the liquid crystal display panel 50 . Accordingly, as the occurrence of a swing pulse of the common voltage due to excessive data transition due to the supply of image data is minimized, the voltage drop of the reference voltage VCC does not occur, and thus, abnormal driving and poor image quality such as screen flickering can be prevented. have.

Since the source output enable (SOE) signal is periodically changed from the high level to the low level after 3 frames have elapsed from the time of displaying the image, each time the source output enable (SOE) has a low level, data unit for one line The raw data voltage may be sequentially supplied to the liquid crystal display panel 50 . The data voltage supplied to the liquid crystal display panel 50 may be applied to each pixel area to display an image on the liquid crystal display panel 50 .

Meanwhile, according to the second embodiment of the present invention, the DPMC algorithm may be executed several frames from the time of displaying the image, so that the horizontal one-dot inversion method may be converted into the horizontal two-dot inversion method and may be driven.

For several frames from the time of displaying the image, the data voltage is increased due to the gate high voltage (VGH) and/or the high level source output enable signal (SOE) signal due to the high level gate output enable (GOE) signal. 50) may not be supplied. Accordingly, the data voltage is not applied to each pixel on the liquid crystal display panel 50 so that a swing pulse of the common voltage due to data transition is not generated.

In addition, the DPMC algorithm is executed several frames from the time of displaying the image, so that the horizontal 1-dot inversion method can be converted into the horizontal 2-dot inversion method. In addition to the execution of the DPMC algorithm, the gate high voltage (VGH) and the high level source output enable signal (SOE) signal due to the low-level high-level gate output enable (GOE) signal and the high-level source output enable signal (SOE) signal from several frames after the video display time Accordingly, the data voltage may be supplied to the liquid crystal display panel 50 . Accordingly, the data voltage of the same polarity is applied in units of two adjacent pixel areas, so that the number of data transitions can be remarkably reduced. Accordingly, the generation of a swing pulse in the common voltage applied to the common line is minimized to suppress the voltage drop of the reference voltage VCC, and thus, abnormal driving of the liquid crystal display panel or poor image quality such as screen flickering can be prevented.

According to the second embodiment of the present invention, by preventing the gate high voltage VGH or the data voltage from being supplied to the liquid crystal display panel for several frames from the time of displaying the image, a swing pulse of the common voltage is generated due to the data transition of the image data. The voltage drop of the reference voltage VCC is suppressed by minimizing or blocking . Accordingly, image quality defects such as abnormal driving of the liquid crystal display panel or screen flickering can be prevented.

Meanwhile, the second embodiment of the present invention may be combined with the first embodiment of the present invention to constitute a new embodiment, but the present invention is not limited thereto.

According to the new embodiment configured as described above, in the case of a worst image based on the image pattern state information immediately before being powered off when power is turned on, the DPMC algorithm is executed at or before the image display time to convert the horizontal 1 dot inversion method into 2 horizontal dots. At the same time, it is possible to prevent the gate high voltage (VGH) or data voltage from being supplied to the liquid crystal display panel for a certain period from the time of displaying the image. Accordingly, when the power is turned on, the occurrence of a swing pulse of the common voltage due to data transition of the image data provided from the time of displaying the image is blocked or minimized to suppress the voltage drop of the reference voltage (VCC) to prevent abnormal operation of the liquid crystal display panel or the screen. It is possible to prevent image quality defects such as flickering.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

10: timing control
20: memory
30: gate driver
40: data driver
50: liquid crystal display panel
60: power supply

Claims (10)

a display panel for displaying an image composed of a plurality of image frames;
a gate driver generating a gate signal to be supplied to the display panel;
a data driver generating a data voltage to be supplied to the display panel;
a timing controller controlling the gate driver and the data driver and generating image pattern state information for each image frame; and
and a memory in which the generated image pattern state information is updated,
The timing control unit,
updating the image pattern state information in the memory until the power is turned off, and determining the image pattern state information as a worst pattern when data transition occurs at a reference value or more among the total pixels of the image frame;
The timing control unit,
When the power is turned on after the power is turned off, the image pattern is determined based on the image pattern state information updated in the memory, and when the image pattern is the worst pattern, a DPMC (Dynamic Power Mode Control) algorithm is executed. display device. According to claim 1,
The DPMC algorithm is executed at or before the time the image is displayed. According to claim 1,
The image pattern state information used for the determination is generated from an image frame immediately before power is turned off. delete According to claim 1,
The image pattern state information is a bit data signal for discriminating a normal image pattern and a worst image pattern. delete According to claim 1,
A display device in which a horizontal 1-dot inversion scheme is converted into a horizontal 2-dot inversion scheme by executing the DPMC algorithm. According to claim 1,
The timing control unit,
generating a gate control signal including at least a gate output enable (GOE) signal for controlling the gate driver;
A display device for generating a data control signal including at least a source output enable (SOE) signal for controlling the data driver. 9. The method of claim 8,
The gate driver is
A display device configured to block supply of a gate high voltage (VGH) to the display panel for a predetermined time from an image display time in response to the gate output enable (GOE) signal. 9. The method of claim 8,
The data driver is
A display device configured to block supply of a data voltage to the display panel for a predetermined time from an image display time in response to the source output enable (SOE) signal.

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