JP4825415B2 - Display driver generating charge pumping signals synchronized to different clocks for multiple mode - Google Patents

Description

  The present invention relates to a display driver for driving a panel, and more particularly, to a display driver and a driving method for generating a charge pumping signal synchronized with different clocks for a multiple mode.

  FIG. 1 is a block diagram illustrating a display driver operating in a conventional video interface mode.

  Referring to FIG. 1, a panel 102, a CPU 104, and a graphic processor 106 that are not included in the display driver 100 are further disclosed for convenience of explanation. The display driver 100 operates in a video interface mode that creates video data with an image on the panel 102.

  The CPU 104 applies a control signal CTRLS to the graphic processor 106. The graphic processor 106 applies a horizontal synchronization signal H_SYNC, a vertical synchronization signal V_SYNC, video data VIDEO_DATA, and a system clock DOTCLK to the timing controller 108 of the display driver 100 in response to the control signal CTRLS.

  The display driver 200 includes a timing controller 108, an oscillator 110, a voltage controller 112, a scan line driving circuit 116, a data line driving circuit 114, and a common voltage VCOM generator 118.

  The timing controller 108 receives the horizontal synchronization signal H_SYNC, the video data VIDEO_DATA, and the system clock DOTCLK, and controls the timing of the data line signal generated by the data line driving circuit 114 and applied to the data lines S1 to Sm of the panel 102. A synchronous data signal S_DATA is applied to the data line driving circuit 114.

  Further, the timing controller 108 receives the vertical synchronization signal V_SYNC and the system clock DOTCLK, and generates a gate signal for controlling the timing of the gate line signal generated by the scan line driving circuit 116 and applied to the gate lines G1 to Gn of the panel 102. Is applied to the scan line driving circuit 116.

  The timing controller 108 uses the system clock DOTCLK to generate an initial common voltage VCOM ′ that controls the timing at which the common voltage generator 118 generates the common voltage VCOM applied to the common node of the panel 102.

  The voltage control unit 112 includes at least one charge pump that generates at least one DC voltage. A general charge pump used in the display driver 100 is pumped by a charge pumping signal DCCLK and generates a DC voltage corresponding to several times the reference voltage Vref.

  A general charge pump structure is disclosed in Patent Document 1 and Patent Document 2. The DC voltage DCV1 generated by the voltage controller 112 controls the size of each data line signal applied to the data lines S1 to Sm. The DC voltage DCV2 generated by the voltage controller 112 controls the size of each gate line signal applied to the gate lines G1 to Gn.

  The DC voltage DCV3 generated by the voltage control unit 112 controls the size of the common voltage VCOM applied to the common node of the panel 102. The timing controller 108 applies the reference voltage Vref to the voltage controller 112 and controls the size of the driving signal that the voltage controller 112 applies to the panel 102.

  Here, the driving signal applied to the panel 102 includes a gate line signal, a data line signal, and a common voltage VCOM. The oscillator 110 generates a charge pumping signal DCCLK that operates at least one charge pump in the voltage controller 112, and the voltage controller 112 generates DC voltages DCV1, DCV2, and DCV3.

  In this manner, the display driver 100 receives the horizontal synchronization signal H_SYNC, the vertical synchronization signal V_SYNC, the video data VIDEO_DATA, and the system clock DOTCLK from the graphic processor 106, and generates a driving signal applied to the panel 102 to generate a video interface mode. The video is controlled as shown on the panel 102.

  Such operations and components are known to those skilled in the art.

  FIG. 2 is a block diagram showing a display driver operating in a conventional CPU interface mode.

  The display driver 120 operates in a CPU interface mode that creates data with an image on the panel 102. Components that use the same reference numbers as in FIG. 1 have the same function and structure.

  The timing controller 122 is directly connected to the CPU 104 in the CPU interface mode and directly receives image data from the CPU 104. The timing controller 122 uses the oscillator clock signal OSC_CLK generated by the oscillator 110 to synchronize the driving signal applied to the panel 102.

  The driving signal applied to the panel 102 includes a gate line signal applied to each gate line G1 to Gn, a data line signal applied to each data line S1 to Sm, and a common voltage VCOM applied to a common node of the panel. It is. The operation and components of the display driver 120 are known to those skilled in the art.

  FIG. 3 is a timing chart for explaining the operation timing of the display driver operating in the CPU interface mode of FIG.

  Referring to FIG. 3, the oscillator clock signal OSC_CLK 132 and the charge pumping signal DCCLK 134 are synchronized with each other. That is, the falling edge 136 and the rising edge 138 of the charge pumping signal 134 are synchronized with the rising edge of the oscillator clock signal 132.

  A driving signal such as the common voltage VCOM 140 is also synchronized with the oscillator clock signal 132 in the CPU interface mode. The falling edge 142 and the rising edge 144 of the common voltage 140 are synchronized with the rising edge of the oscillator clock signal 132.

  The common voltage 140 in FIG. 3 is an ideal waveform in which noise is not considered, and the common voltage 146 is an actual waveform in which noise is considered. The charge pumping signal 134 is used to generate a DC voltage DCV3 that determines the size of the common voltage 146.

  The charge pumping signal 134 is synchronized to the oscillator clock signal 132, and in particular is generated from the oscillator clock signal 132. For example, a charge pumping signal 134 having a period that is an integral multiple of the oscillator clock signal 132 may be generated using a frequency divider (not shown).

  Since the charge pumping signal 134 is generated from the oscillator clock signal 132, the noise-considered common voltage 146 is synchronized with the half cycle of the oscillator clock signal 132. Since the common voltage 146 in consideration of noise is synchronized with the oscillator clock signal 132 in the CPU mode, the waveform of the common voltage 146 in consideration of noise has a regular pattern.

  Such regular noise applied to the panel 102 repeatedly occurs throughout the panel 102 and generates a constant effect. In the CPU interface mode, the constant influence generated on the entire image of the panel 102 due to the noise is difficult to detect with the naked eye.

  FIG. 4 is a timing chart for explaining the operation timing of the display driver operating in the video interface mode of FIG.

  As in the CPU mode, the oscillator clock signal OSC_CLK 132 and the charge pumping signal DCCLK 134 are synchronized with each other. However, in the video interface mode of FIG. 4, the driving signal such as the common voltage VCOM 154 is synchronized with the system clock signal DOTCLK 152 generated by the graphic processor 106.

  The falling edge 156 and the rising edge 158 of the common voltage 154 are synchronized with the rising edge of the system clock signal DOTCLK 152. The common voltage 154 in FIG. 4 is an ideal waveform in which noise is not considered, and the common voltage 160 is an actual waveform in which noise is considered.

  The common voltage 160 in consideration of noise is synchronized with the system clock signal 152 generated by the graphic processor 106 that is not the oscillator 110 that generates the oscillator clock signal 132. Therefore, the common voltage 160 is not synchronized with the oscillator clock signal 132 and the charge pumping signal 134.

  As a result, noise generated in the charge pump cannot form a regular pattern in the common voltage 160. Noise is irregular on the rising edge 164 or falling edge 162 of the common voltage 160.

  Such irregular noise applied to the panel 102 causes a non-constant influence on the entire panel 102. In the video interface mode, the non-constant influence caused by the noise on the entire image of the panel 102 is perceived by the naked eye.

The perceptible noise-free display driver panel 102 is required in the CPU mode and the video mode. In addition, a display driver that can operate in one of the CPU interface mode and the video interface mode by the CPU is required.
US publication number US2003 / 0011586 US Publication Number US2002 / 0044118 Specification

  A technical problem to be solved by the present invention is to provide a driver for driving a display panel which is not affected by noise in a CPU mode or a video interface mode.

A display driver according to an embodiment of the present invention for solving the technical problem includes a first signal generator for generating a first charge pumping signal selected in a video interface mode, and a second signal selected in a CPU interface mode. A second signal generator for generating a charge pumping signal; a charge pump for generating at least one DC voltage by pumping the first and second charge pumping signals; and the first charge pumping signal in the video interface mode. A signal selection unit coupled to the charge pump and coupling the second charge pumping signal to the charge pump in the CPU interface mode , wherein the first signal generation unit graphically displays the first charge pumping signal. Process In synchronization with the first system clock signal output from the second signal generating unit includes an oscillator for generating said second charge pumping signal is synchronized with the second system clock signal the second system clock signal To do.

  The signal selection unit is connected to a data processing unit that generates a control signal indicating whether the video interface mode or the CPU interface mode is selected. The display driver further includes a common voltage generator that generates a common voltage applied to the common node of the panel from the DC voltage, and a timing controller that controls the timing of the common voltage.

  In the video interface mode, the common voltage is synchronized with the first charge pumping signal, and in the CPU interface mode, the common voltage is synchronized with the second charge pumping signal.

  The display driver further includes a data line driver that generates a data signal applied to the data line of the panel from the DC voltage, and a scan line driver that generates a gate signal applied to the scan line of the panel from the DC voltage. .

  The timing controller controls the timing of the data signal and the gate signal. The data signal and the gate signal are synchronized with the first charge pumping signal in the video interface mode, and are synchronized with the second charge pumping signal in the CPU mode.

  The first signal generator includes a clock divider and a signal converter.

  The clock divider indicates a transition timing of each of the first charge pumping signals according to the number of clocks of the system clock signal during one period of the synchronization signal from the start of the period of the synchronization signal.

  The signal converter generates a transition of the first charge pumping signal every time the number of clocks of the system clock signal reaches a certain number from the start of the period of the synchronization signal. The clock divider is coupled to a graphic processor that generates the system clock signal and the synchronization signal.

  The clock divider is a register that stores a total number T_NUMCLK of clocks of the system clock signal during one period of the synchronization signal, and for each transition of the first charge pumping signal during one period of the synchronization signal. A clock divider for determining the number of clocks of the system clock signal from a desired frequency of the first charge pumping signal and a total number of clocks of the system clock signal;

  The signal converter includes a counter, a comparator, a pulse generator, and a toggle flip-flop.

  The counter counts the number of clocks NUMCLK of the system clock signal from the start of each cycle of the synchronization signal. The comparison unit compares a fixed clock number R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal determined by the clock divider and a clock number NUMCLK of the system clock signal.

  The pulse generator generates a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating the transition of the first charge pumping signal. Let The toggle flip-flop transitions the first charge pumping signal for each pulse generated from the pulse generator.

  The clock divider includes a data storage device for storing a predetermined number of clocks R1 to RNx of the system clock signal for generating each transition of the first charge pumping signal during one period of the synchronization signal.

  The signal converter includes a counter, a comparator, a pulse generator, and a toggle flip-flop.

  The counter counts the number of clocks NUMCLK of the system clock signal from the start of each cycle of the synchronization signal. The comparison unit compares the fixed clock numbers R1 to RNx of the system clock signal for generating the transition of the first charge pumping signal stored in the data storage device with the clock number NUMCLK of the system clock signal.

  The pulse generator generates a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating the transition of the first charge pumping signal. Let

  The toggle flip-flop transitions the first charge pumping signal for each pulse generated from the pulse generator. The display driver is for a liquid crystal display device.

A display system according to another embodiment of the present invention for solving the technical problem includes a panel and a display driver that generates a driving signal applied to the panel. The display driver is in a video interface mode. A first signal generator for generating a first charge pumping signal to be selected; a second signal generator for generating a second charge pumping signal to be selected in a CPU interface mode; data in the video interface mode; A graphics processor for providing a clock signal and a synchronization signal to the display driver, a data processor for providing data to the display driver in a CPU interface mode, and the first and second charge pumping signals are pumped. Connected to the charge pump to generate at least one DC voltage, and to connect the first charge pumping signal to the charge pump in the video interface mode, and to pass the second charge pumping signal to the charge pump in the CPU interface mode. A signal selection unit to be coupled, wherein the first signal generation unit synchronizes the first charge pumping signal with a first system clock signal output from a graphic processor, and the second signal generation unit is a second system. And an oscillator for generating a clock signal and the second charge pumping signal synchronized with the second system clock signal .

According to another embodiment of the present invention, a method for generating a charge pumping signal of a display driver for solving the technical problem includes generating a first charge pumping signal used in a video interface mode, and in a CPU interface mode. Generating a second charge pumping signal to be used; synchronizing the first charge pumping signal to a first system clock signal output from a graphics processor; and generating a second system clock signal in an oscillator; Synchronizing the second charge pumping signal to the second system clock signal, and the first charge pumping signal used as a charge pumping signal for generating at least one DC voltage in the video interface mode. Comprising selecting a grayed signal, and a step of selecting the second charge pumping signal used as the charge pumping signals for generating at least one DC voltage by the CPU interface mode.

  The display driver according to the embodiment of the present invention is not affected by noise in both the CPU mode and the video interface mode, and can display an image on the panel.

  For a full understanding of the invention, its operational advantages, and the objectives achieved by the practice of the invention, reference should be made to the drawings illustrating the preferred embodiments of the invention and the contents described in the drawings. Don't be.

  Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numerals provided in each drawing denote the same members.

  Referring to FIG. 5, a display driver 200 according to an embodiment of the present invention generates a charge pumping signal synchronized with the same clock signal in an interface mode with a CPU and a driving signal for a panel.

  Although the present invention is described for a liquid crystal panel 202, it can also be used for other types of panels. The panel 202, the graphic processor 206, and the CPU 204 that are not constituent elements of the display driver 200 are displayed by dotted lines. However, the panel 202, the graphic processor 206, and the CPU 204 constitute an LCD system together with the display driver 200.

  The display driver 200 according to the embodiment of the present invention includes a scan line driver 216, a common voltage generator 218, a voltage controller 212, and a data line driver 214, and operates in the same manner as the components corresponding to FIG.

  However, the timing controller 208 includes a charge pumping signal generator 220 that generates the first charge pumping signal DCCLK1 connected to the charge pump of the voltage controller 212 in the video interface mode.

  The graphic processor 206 provides the synchronization signals H_SYNC, V_SYNC, the first system clock signal DOTCLK1, and the video data VIDEO_DATA to the timing controller 208 in the video interface mode.

  The oscillator 210 generates a second system clock signal DOTCLK2 and a second charge pumping signal DCCLK2 used in the CPU interface mode. The signal selector 222, which is a multiplexer, receives the first and second charge pumping signals DCCLK1 and DCCLK2, and applies the selected charge pumping signal DCCLK to the voltage controller 212.

  The CPU 204 applies data DATA to the timing controller 208. The CPU 204 is connected to the graphic processor 206, the timing controller 208, the signal selection unit 222, and the oscillator 210 to select a CPU interface mode or a video interface mode.

  FIG. 6 is a diagram illustrating the charge pumping signal generator of FIG. 5 for generating a first charge pumping signal when the display driver is in the video interface mode.

  The charge pumping signal generator 220A generates a first charge pumping signal DCCLK1 synchronized with the first system clock signal DOTCLK1 generated by the graphic processor 206. The charge pumping signal generator 220A includes a clock divider 232 and a signal converter 234.

  The clock divider 232 includes a register 236 and a clock divider 238. The signal converter 234 includes a counter 240, a comparator 242, a pulse generator 244 and a toggle flip-flop 246. The toggle flip-flop 246 includes an inverter 248 in the feedback path of the D-type flip-flop 250.

  The operation of the charge pumping signal generator of FIG. 6 will be described with reference to FIGS.

  In the video interface mode, the counter 240 counts how many first system clock signals DOTCLK1 exist (NUMCLK) during a period between the synchronization signal H_SYNC and the next synchronization signal H_SYNC (step 262 in FIG. 8).

  In FIG. 7, one cycle of the synchronization signal H_SYNC is from T1 to T4. The counter 240 counts the number of clocks of the first system clock signal DOTCLK1 during one cycle of the synchronization signal H_SYNC. The number of first system clock signals DOTCLK1 increases from the start of the cycle of the synchronization signal H_SYNC.

  The register 236 stores the total number T_NUMCLK of the first system clock signals DOTCLK1 existing during one cycle of the synchronization signal H_SYNC. In the embodiment of the present invention, T_NUMCLK = 224.

  After T_NUMCLK is determined, the clock divider 238 determines the respective numbers RN1 to RNx of the first system clock signal DOTCLK1 from the start of the period of the synchronization signal H_SYNC every time a transition of the first charge pumping signal DCCLK1 occurs. . RN1 to RNx are determined from a desired frequency of the first charge pumping signal DCCLK1 and T_NUMCLK.

  The desired frequency of the first charge pumping signal DCCLK1 is determined by the number m of the data lines S1 to Sm, the number n of the gate lines G1 to Gn, and the frame ratio of the panel 202 in the video interface mode. This can be expressed mathematically as follows.

  Desirable frequency of the first charge pumping signal DCCLK1 = m × n × FRAME_RATE.

  Since the frequency of the first system clock signal DOTCLK1 is known, the clock divider 238 determines the first charge pumping signal DCCLK1 for one period of the synchronization signal H_SYNC every time a transition of the first charge pumping signal DCCLK1 occurs. The respective numbers RN1 to RNx of the first system clock signal DOTCLK1 are determined from the desired frequency and T_NUMCLK.

  In FIG. 7, the frequency of the first charge pumping signal DCCLK1 is preferably 1/148 of the frequency of the first system clock signal DOTCLK1 when T_NUMCLK = 224. Therefore, the clock divider 238 sets RN1 = 74, RN2 = 148, and RN3 = 224 to generate three transitions of the first charge pumping signal DCCLK1 for one period of the synchronization signal H_SYNC.

  In the embodiment of the present invention, the respective numbers RN1 to RNx of the first system clock signal DOTCLK1 are determined during one period of the synchronization signal H_SYNC at the start of the video interface mode. Therefore, the image quality of the panel 202 is not greatly affected by the determination as described above.

  6 to 8, the respective numbers RN <b> 1 to RNx of the first system clock signal DOTCLK <b> 1 determined by the clock divider 238 are applied to the comparison unit 242. At the start of the synchronization signal H_SYNC, the NUMCLK value of the counter 240 is set to “0” to generate the first charge pumping signal DCCLK1 (step 266 in FIG. 8).

  Then, the counter 240 increases the coefficient by one for each number of clocks of the first system clock signal DOTCLK1 (step 268 in FIG. 8). The comparison unit 242 compares NUMCLK with the number of R1 to RNx.

  If the number of NUMCLK is the same as the number of R1 to RNx (step 270 in FIG. 8), the comparator 242 sends the control signal CTRLS to the pulse generator 244 to generate a pulse with the pulse control signal 256. Send (step 272).

  The pulse of the pulse control signal 256 controls the transition of the first charge pumping signal DCCLK1 coming out from the Q output of the toggle flip-flop 246. If the first system clock signal DOTCLK1 and the synchronization signal H_SYNC are not provided at the end of the video interface mode (step 274), the operation of the first charge pumping signal generator 220A is also terminated.

  If the cycle of the synchronization signal H_SYNC has not ended yet (step 276), the process returns to step 268 and the operations of steps 268 to 276 are repeated for each clock of the first system clock signal DOTCLK1 until the synchronization signal H_SYNC ends.

  If the cycle of the synchronization signal H_SYNC ends at the start of the cycle of the next synchronization signal (step 276), the operation returns to step 266 where NUMCLK = "0" is reset, and the operations of steps 268 to 276 are performed for the next continuous synchronization. Repeat for one cycle of signal H_SYNC.

  In this manner, the transition of the first charge pumping signal DCCLK1 occurs during the period of the synchronization signal H_SYNC whenever the number of NUMCLK is the same as the number of each of R1 to RNx. In the example of FIG. 7, three transitions 255, 257, 259 of the first charge pumping signal DCCLK1 occur at RN1 = 74, RN2 = 148 and RN3 = 224 during the period of the synchronization signal H_SYNC.

  The 74 clocks of the first system clock signal DOTCLK1 are between T2 which is the first transition time 255 of the first charge pumping signal DCCLK1 during the period of the synchronization signal H_SYNC from the time T1 when the period of the synchronization signal starts. appear.

  Further, 74 clocks of the first system clock signal DOTCLK1 are generated from T2 during T3 which is the second transition time 257 of the first charge pumping signal DCCLK1 during the period of the synchronization signal H_SYNC.

  The 76 clocks of the first system clock signal DOTCLK1 are generated from T3 during T4 which is the third transition time 259 of the first charge pumping signal DCCLK1 during the period of the synchronization signal H_SYNC.

  The clock divider 238 may not generate the same number of clocks of the first system clock signal DOTCLK1 between RN1 and RNx. Nevertheless, the first charge pumping signal DCCLK1 has a regular period and frequency so as to have the same frequency as the desired frequency.

  FIG. 9 shows still another embodiment of the first charge pumping signal generator of FIG.

  Components having the same reference numbers in FIGS. 6 and 9 perform similar functions. However, the clock divider 280 is different from the clock divider 232 of FIG. 9, the clock divider 280 includes a data storage device 282 that stores R1 to RNx each time a transition of the first charge pumping signal DCCLK1 occurs. The designer of the data system of FIG. 5 can determine and program the number of R1 to RNx.

  FIG. 10 is a flowchart for explaining the operation of the first charge pumping signal generator of FIG.

  Steps having the same reference numbers in FIGS. 8 and 10 perform similar functions. One difference between FIG. 10 and FIG. 8 is 292 stages, and the comparison unit 242 reads R1 to RNx from the data storage device 282. In addition, the operation of the charge pumping signal generator 220B of FIG. 9 is similar to that of the charge pumping signal generator 220A of FIG.

  Referring to the display driver 200 of FIG. 5, the charge pumping signal generator 220 generates the first charge pumping signal DCCLK1 according to the structure of 220A and 220B. Accordingly, the first charge pumping signal DCCLK1 is generated in synchronization with the first system clock signal DOTCLK1 output from the graphic processor 206.

  The oscillator 210 generates a second system clock signal DOTCLK2 similar to the oscillator clock OSC_CLK of FIGS. The oscillator 210 synchronizes the second charge pumping signal DCCLK2 with the second system clock signal DOTCLK2.

  For example, a frequency divider for generating the second charge pumping signal DCCLK2 having a period that is an integral multiple of the period of the second system clock signal DOTCLK2 is used in the oscillator 210.

  The operation of the display driver 200 of FIG. 5 in the video and CPU interface mode will be described with reference to FIG. The CPU 204 generates a mode signal MODE for selecting whether the display driver 200 is in the CPU interface mode or the video interface mode.

  If a still image appears on the panel 202, the CPU 204 causes the display driver 200 to operate in the CPU interface mode. Conversely, if a moving image appears on the panel 202, the CPU 204 causes the display driver 200 to operate in the video interface mode.

  5 and 11, the display driver 200 receives a mode signal MODE for selecting the CPU interface mode or the video interface mode (step 302 in FIG. 11). If the mode signal indicates the video interface mode (step 304 in FIG. 11), steps 306 to 314 are performed. If the mode signal indicates the CPU interface mode (step 304 in FIG. 11), steps 316 to 322 are performed.

  If the mode signal indicates the video interface mode (step 306 in FIG. 11), the oscillator 210 is disabled for energy saving. In the video interface mode, the graphic processor 206 provides the video data VIDEO_DATA, the first system clock signal DOTCLK1, the synchronization signals H_SYNC, and V_SYNC to the timing controller 208.

  The charge pumping signal generator 220 receives the first system clock signal DOTCLK1 and the synchronization signal H_SYNC from the graphic processor 206 (step 308 in FIG. 11), and generates the first charge pumping signal DCCLK1 as described above (FIG. 1). 310 stage).

  The signal selector 222, which is a multiplexer, selects the first charge pumping signal DCCLK1 generated from the charge pumping signal generator 220 in the video interface mode as the charge pumping signal DCCLK (step 312). The selected charge pumping signal DCCLK1 controls a charge pump in the voltage controller 212 for generating the DC voltages DCV1 to DCV3.

  In the video interface mode, the timing controller 208 controls the data line driver 214, the scan line driver 216, and the common voltage generator 218 that generate a driving signal synchronized with the first system clock signal DOTCLK1 output from the graphic processor 206.

  The driving signal applied to the panel 202 includes a gate line signal, a data line signal, and a common voltage VCOM.

  In this manner, the display driver 200 uses the first charge pumping signal DCCLK1 that is synchronized with the system clock signal DCCLK1 that is synchronized with the driving signal in the video interface mode.

  Therefore, the noise superimposed on the driving signal is regular and constant noise for the entire panel 202, similar to that appearing in the VCOM signal 146 of FIG. The effect of such regular noise on the panel 202 is not so noticeable to the naked eye in the video interface mode.

  Conversely, if the mode signal indicates the CPU interface mode, the charge pumping signal generator 220 is disabled for energy saving (step 315 in FIG. 11). Instead, the oscillator 210 generates the second system clock signal DOTCLK2 (step 316 in FIG. 11).

  In the CPU interface mode, the oscillator 210 generates a second charge pumping signal DCCLK2 that is synchronized with the second system clock signal DOTCLK2 (operation 318).

  The signal selection unit 222 selects the second charge pumping signal DCCLK2 as the charge pumping signal DCCLK in the CPU interface mode (operation 320). The selected charge pumping signal DCCLK2 controls a charge pump in the voltage controller 212 for generating the DC voltages DCV1 to DCV3.

  In the CPU interface mode, the timing controller 208 is synchronized with the second system clock signal DOTCLK2 output from the oscillator 210 (step 322 in FIG. 11). The unit 218 is controlled.

  The driving signal applied to the panel 202 includes a gate line signal, a data line signal, and a common voltage VCOM.

  In this manner, the display driver 200 uses the second charge pumping signal DCCLK2 that is synchronized with the system clock signal DCCLK2 that is synchronized with the driving signal in the CPU interface mode.

  Therefore, the noise superimposed on the driving signal is regular and constant noise for the entire panel 202, similar to that appearing in the VCOM signal 146 of FIG. The influence of such regular noise on the panel 202 is not recognized so much by the naked eye in the CPU interface mode.

  The display driver 200 generates respective charge pumping signals and driving signals synchronized with clock signals corresponding to the CPU interface mode and the video interface mode.

  Therefore, the noise superimposed on the driving signal is regular and constant noise for the entire panel 202, and the influence of such regular noise on the panel 202 is not recognized so much by the naked eye in the CPU and video interface modes.

  The following are examples of the invention and are not intended to be limiting. Embodiments of the present invention are described for LCD panels. However, embodiments of the present invention can be applied to other types of panels.

  In addition, the components described in the embodiments of the present invention can be realized by a combination of hardware and software, and can also be realized in an integrated circuit. Any number of the signals is only an example and is not intended to be limiting.

  Further, the signal paths described in the embodiments are only examples. For example, FIG. 12 is a display system 340 that includes the display driver 200 of FIG. 5 operating in a CPU interface mode.

  Components with the same reference number perform the same function. In FIG. 12, the data DATA input to the display driver 200 in the CPU interface mode may be provided by the CPU 204 after being read from the memory device 342.

  Conversely, data DATA input to the display driver 200 in the CPU interface mode can be read directly from the memory device 342 by the display driver 200.

  Similarly, FIG. 13 is a display system 350 comprising the display driver 200 of FIG. 5 operating in a video interface mode.

  Components with the same reference number perform the same function. In FIG. 13, video data VIDEO0_DATA input to the display driver 200 in the video interface mode may be provided to the graphic processor 206 by the CPU 204 after being read from the memory device 352.

  Conversely, video data VIDEO_DATA input to the display driver 200 in the video interface mode can be read directly by the graphic processor 206 in the memory device 352. Alternatively, the video data VIDEO_DATA can be provided to the graphics processor 206 by the video camera 354.

  As described above, the optimum embodiment has been disclosed in the drawings and specification. Certain terminology has been used herein for the purpose of describing the present invention only and is intended to limit the scope of the invention as defined in the meaning and claims. It was not used for Accordingly, those skilled in the art can understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention relates to the operation of a display driver, and can be used in a liquid crystal driving system for displaying an image on a liquid crystal.

It is a block diagram showing a display driver that operates in a conventional video interface mode. It is a block diagram showing a display driver that operates in a conventional CPU interface mode. FIG. 3 is a timing diagram illustrating operation timings of a display driver that operates in the CPU interface mode of FIG. 2. FIG. 2 is a timing diagram illustrating operation timings of a display driver that operates in the video interface mode of FIG. 1. 3 is a diagram illustrating a display driver for generating a charge pumping signal and a panel driving signal synchronized with the same clock signal in an interface mode with a CPU according to an embodiment of the present invention; 6 is a diagram illustrating a charge pumping signal generation unit of FIG. 5 that generates a first charge pumping signal when a display driver is in a video interface mode. 7 is a timing diagram illustrating signals during operation of the charge pumping signal generation unit of FIG. 6 for generating a first charge pumping signal when the display driver is in a video interface mode. 7 is a flowchart illustrating an operation of the charge pumping signal generation unit of FIG. 6 for generating a first charge pumping signal when the display driver is in a video interface mode. 6 is still another example of the first charge pumping signal generator of FIG. 10 is a flowchart illustrating an operation of a first charge pumping signal generation unit of FIG. 9. 6 is a flowchart illustrating an operation of the display driver of FIG. 5 in a CPU and video interface mode. 6 is a display system including the display driver of FIG. 5 operating in a CPU interface mode. 6 is a display system comprising the display driver of FIG. 5 operating in a video interface mode.

Explanation of symbols

200: Display driver,
202 ... LCD panel,
204 ... CPU,
206 ... graphic processor,
208 ... Timing controller,
210 ... Oscillator,
212 ... Voltage controller,
214 ... Data line driver,
216 ... scan line driver,
218 ... Common voltage generator,
220: Charge pumping signal generator,
MODE ... mode signal,
DOTCLK1, DOTCLK2,... First system clock signal, second system clock signal,
DCCLK: Charge pumping signal,
DATA ... data,
VIDEO_DATA ... video data,
H_SYNC: Horizontal sync signal,
V_SYNC ... vertical synchronization signal,
DCV1, DCV2, DCV3 ... DC voltage,
VCOM ... Common voltage,
G1 ... Gn ... gate line,
S1 ... Sm ... data line.

Claims (30)

A first signal generator for generating a first charge pumping signal selected in the video interface mode;
A second signal generator for generating a second charge pumping signal selected in the CPU interface mode;
A charge pump that pumps the first and second charge pumping signals to generate at least one DC voltage;
A signal selection unit for connecting the first charge pumping signal to the charge pump in the video interface mode and for connecting the second charge pumping signal to the charge pump in the CPU interface mode ;
The first signal generator synchronizes the first charge pumping signal with a first system clock signal output from a graphic processor,
The display driver, wherein the second signal generator includes an oscillator that generates a second system clock signal and the second charge pumping signal synchronized with the second system clock signal . The signal selector is
The display driver according to claim 1 , wherein the display driver is connected to a data processing unit that generates a control signal indicating whether the video interface mode or the CPU interface mode is selected. A common voltage generator for generating a common voltage applied to the common node of the panel from the DC voltage;
The display driver according to claim 1 or 2, further comprising a, a timing controller for controlling timing of the common voltage. The display of claim 3 , wherein the common voltage is synchronized with the first charge pumping signal in the video interface mode, and the common voltage is synchronized with the second charge pumping signal in the CPU interface mode. driver. A data line driver for generating a data signal applied to the data line of the panel from the DC voltage;
A scan line driver that generates a gate signal applied to the scan line of the panel from the DC voltage; and
The display driver according to claim 3 or 4 wherein the timing controller and the controller controls the timing of the data signal and the gate signal. The data signal and the gate signal are:
6. The display driver of claim 5 , wherein the display driver is synchronized with the first charge pumping signal in a video interface mode and is synchronized with a second charge pumping signal in a CPU mode. The first signal generator is
A clock frequency divider that indicates the transition timing of each of the first charge pumping signals as the number of clocks of the system clock signal during one period of the synchronization signal from the start of the period of the synchronization signal;
And a signal converter for generating a transition of the first charge pumping signal each time the number of clocks of the system clock signal reaches a certain number from the start of the period of the synchronization signal. The display driver according to any one of 1 to 6 . The display driver of claim 7 , wherein the clock divider is connected to a graphic processor that generates the system clock signal and the synchronization signal. The clock divider is
A register for storing a total number T_NUMCLK of clocks of the system clock signal during one period of the synchronization signal;
During one period of the synchronization signal, the number of clocks of the system clock signal for each transition of the first charge pumping signal is determined from a desired frequency of the first charge pumping signal and the total number of clocks of the system clock signal. the display driver according to claim 7 or 8, characterized by comprising a clock divider, a. The signal converter is
A counter that counts the number of clocks NUMCLK of the system clock signal from the start of each period of the synchronization signal;
A comparison unit for comparing a fixed clock number R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal determined by the clock divider and a clock number NUMCLK of the system clock signal;
A pulse generator for generating a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal When,
The display driver according to claim 9 , further comprising a toggle flip-flop that transitions the first charge pumping signal for each pulse generated from the pulse generator. The clock divider is
The data storage device according to claim 1, further comprising: a predetermined number of clocks R1 to RNx of the system clock signal for generating each transition of the first charge pumping signal during one period of the synchronization signal. 8. The display driver according to 7 . The signal converter is
A counter that counts the number of clocks NUMCLK of the system clock signal from the start of each period of the synchronization signal;
A comparison unit for comparing a fixed clock number R1 to RNx of the system clock signal and a clock number NUMCLK of the system clock signal for generating a transition of the first charge pumping signal stored in the data storage device;
A pulse generator for generating a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal When,
The display driver of claim 1 1, characterized by comprising: a toggle flip-flop to transition said first charge pumping signals for each pulse generated from the pulse generator. The display driver The display driver according to any one of claims 1 to 1 2, characterized in that for the liquid crystal display device. In the display system,
A panel,
A display driver that generates a driving signal applied to the panel;
A first signal generator for generating a first charge pumping signal selected in the video interface mode;
A second signal generator for generating a second charge pumping signal selected in the CPU interface mode;
A graphic processor for providing data, a first system clock signal and a synchronization signal to the display driver in the video interface mode;
A data processor for providing data to the display driver in a CPU interface mode;
A charge pump that pumps the first and second charge pumping signals to generate at least one DC voltage;
A signal selection unit for connecting the first charge pumping signal to the charge pump in the video interface mode and for connecting the second charge pumping signal to the charge pump in the CPU interface mode ;
The first signal generator synchronizes the first charge pumping signal with a first system clock signal output from a graphic processor,
The display system according to claim 1, wherein the second signal generator includes an oscillator for generating a second system clock signal and the second charge pumping signal synchronized with the second system clock signal . The signal selector is
The display system of claim 14 , wherein the display system is connected to a data processing unit that generates a control signal indicating whether the video interface mode or the CPU interface mode is selected. The first signal generator is
A clock frequency divider that indicates the transition timing of each of the first charge pumping signals as the number of clocks of the system clock signal during one period of the synchronization signal from the start of the period of the synchronization signal;
And a signal converter for generating a transition of the first charge pumping signal each time the number of clocks of the system clock signal reaches a certain number from the start of the period of the synchronization signal. The display system according to 14 or 15 . The clock divider is
A register for storing a total number T_NUMCLK of clocks of the system clock signal during one period of the synchronization signal;
During one period of the synchronization signal, the number of clocks of the system clock signal for each transition of the first charge pumping signal is determined from a desired frequency of the first charge pumping signal and the total number of clocks of the system clock signal. The display system according to claim 16 , further comprising a clock divider. The signal converter is
A counter that counts the number of clocks NUMCLK of the system clock signal from the start of each period of the synchronization signal;
A comparison unit for comparing a fixed clock number R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal determined by the clock divider and a clock number NUMCLK of the system clock signal;
A pulse generator for generating a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal When,
18. The display system of claim 17 , further comprising a toggle flip-flop that transitions the first charge pumping signal for each pulse generated from the pulse generator. The clock divider is
The data storage device according to claim 1, further comprising: a predetermined number of clocks R1 to RNx of the system clock signal for generating each transition of the first charge pumping signal during one period of the synchronization signal. 17. The display system according to 16 . The signal converter is
A counter that counts the number of clocks NUMCLK of the system clock signal from the start of each period of the synchronization signal;
A comparison unit for comparing a fixed clock number R1 to RNx of the system clock signal and a clock number NUMCLK of the system clock signal for generating a transition of the first charge pumping signal stored in the data storage device;
A pulse generator for generating a pulse if the clock number NUMCLK of the system clock signal is the same as one of the predetermined clock numbers R1 to RNx of the system clock signal for generating a transition of the first charge pumping signal When,
20. The display system of claim 19 , further comprising a toggle flip-flop that transitions the first charge pumping signal for each pulse generated from the pulse generator. The display system according to any one of claims 14 to 20 , wherein the display driver is for a liquid crystal display device. In a method for generating a charge pumping signal for a display driver,
Generating a first charge pumping signal used in video interface mode;
Generating a second charge pumping signal used in the CPU interface mode;
Synchronizing the first charge pumping signal to a first system clock signal output from a graphics processor;
Generating a second system clock signal with an oscillator;
Synchronizing the second charge pumping signal to the second system clock signal;
Selecting the first charge pumping signal to be used as a charge pumping signal for generating at least one DC voltage in the video interface mode;
Selecting the second charge pumping signal used as the charge pumping signal for generating the at least one DC voltage in the CPU interface mode . Generating a common voltage applied to the common node of the panel from the DC voltage;
23. The charge of claim 22 , wherein the common voltage is synchronized with the first charge pumping signal in the video interface mode, and the common voltage is synchronized with the second charge pumping signal in the CPU interface mode. Pumping signal generation method. Generating a data signal applied to the data line of the panel from the DC voltage;
Generating a gate signal applied to the scan line of the panel from the DC voltage,
The data signal and the gate signal are:
The video interface mode is synchronized to the first charge pumping signal, the charge pumping signal generation method according to claim 22 or 23, characterized in that it is synchronized to the second charge pumping signal in CPU mode. Generating the first charge pumping signal comprises:
Indicating the transition timing of each of the first charge pumping signals as the number of clocks of the first system clock signal during one period of the synchronization signal from the start of the period of the synchronization signal;
And a step of generating a transition of the first charge pumping signal each time the number of clocks of the first system clock signal reaches a certain number from the start of the period of the synchronization signal. The charge pumping signal generation method according to any one of 22 to 24 . The step of indicating each transition timing of the first charge pumping signal includes:
Counting the total number T_NUMCLK of clocks of the system clock signal during one period of the synchronization signal;
During one period of the synchronization signal, the number of clocks of the first system clock signal for each transition of the first charge pumping signal is set to the desired frequency of the first charge pumping signal and the clock of the first system clock signal. 26. The method of claim 25 , further comprising: determining from the total number. Generating a transition of the first charge pumping signal comprises:
Counting the number of clocks NUMCLK of the first system clock signal from the start of each period of the synchronization signal;
Comparing a fixed clock number R1 to RNx of the first system clock signal and a clock number NUMCLK of the first system clock signal for generating a transition of the first charge pumping signal determined by a clock divider. When,
A pulse is generated if the number of clocks NUMCLK of the first system clock signal is the same as a predetermined number of clocks R1 to RNx of the first system clock signal for generating a transition of the first charge pumping signal. And the stage
27. The method of claim 26 , further comprising: transitioning the first charge pumping signal for each pulse generated from a pulse generator. The step of indicating each transition timing of the first charge pumping signal includes:
And storing a predetermined number of clocks R1 to RNx of the first system clock signal for generating each transition of the first charge pumping signal during one period of the synchronization signal. 26. A method for generating a charge pumping signal according to 25 . Generating a transition of the first charge pumping signal comprises:
Counting the number of clocks NUMCLK of the first system clock signal from the start of each period of the synchronization signal;
Comparing a fixed clock number R1 to RNx of the first system clock signal and a clock number NUMCLK of the first system clock signal for generating a transition of the first charge pumping signal stored in a data storage device; ,
A pulse is generated if the number of clocks NUMCLK of the first system clock signal is the same as a predetermined number of clocks R1 to RNx of the first system clock signal for generating a transition of the first charge pumping signal. And the stage
30. The method of claim 28 , further comprising: transitioning the first charge pumping signal for each pulse generated from a pulse generator. The display driver charge pumping signal generating method according to any one of claims 22-29, characterized in that is for a liquid crystal display device.

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