JP3756203B2 - Memory circuit and flat panel drive circuit - Google Patents

Description

[0001]
[Industrial application fields]
The memory element of the present invention is used for SRAM, DRAM, PROM, EPROM, and EEPROM, which are memory elements for writing and reading. The address signal generation circuit of the present invention is used for the operation of the memory element for writing and reading. The flat panel drive circuit of the present invention is used for a drive circuit connected to a data electrode of a flat panel of a liquid crystal panel.
[0002]
[Prior art]
Hereinafter, a memory element that performs writing and reading is abbreviated as a memory element. Hereinafter, the high level of the signal is indicated by “H” and the low level is indicated by “L”. In order to make the logic easy to understand, the signal can be operated at “H” unless otherwise specified, and the switching of the count or the like will be described using the falling edge of the signal.
[0003]
8 and 9 are a configuration diagram of a conventional memory circuit and a diagram showing signals around the memory circuit, respectively. An example of counting five input clocks is used.
[0004]
An input clock 102 that is a first external signal and an external reset signal 101 that is a second external signal are input to the memory element operation signal creation unit 103 and are used to read and write data to the memory element 104. Signals such as RD 106 and PC 107 are created. The WR105 signal is a signal used for writing data to the memory element 104. The RD 106 signal is a signal used for reading data from the storage element 104. The PC107 signal is a precharge signal required for switching between the WR105 signal and the RD106 signal. When the data indicated by the diagonal lines of the storage element input data 110 synchronized with the input clock 102 is transferred, the storage element input data 110 is addressed by the pulse indicated by the arrow of the WR105 signal including the address changing means and the address cycle changing means. The address first stage signal 162-1, the address second stage signal 162-2, and the address third stage signal 162-3 generated by the signal generation circuit 161 are all taken into the memory element 104 in the “L” portion. Address first stage signal 162-1 indicates the lowest address. Thereafter, the address first stage signal 162-1, address second stage signal 162-2, and address third stage signal 162-3 are all indicated by hatching from the memory element 104 in the “L” portion by the pulse indicated by the arrow of the RD106 signal. Data written to the memory element 104 is read. When the hatched portion of the storage element output data 163 is synchronized with the input clock 102 by the synchronizing unit 112, the data is output to the shaded portion of the output data 164. In this manner, the output data 164 of the conventional memory circuit is output to a portion delayed by one cycle of the input clock 102 from the input portion. In other words, b1, b2, b3,... Of the storage element input data 110 are read to b1, b2, b3,.
[0005]
FIG. 10 and FIG. 11 are diagrams showing a configuration of a conventional address signal generation circuit and signals around the address signal generation circuit, respectively. An example of counting five input clocks is used. The input clock 102 that is the first external signal is input to a synchronous or asynchronous frequency divider 171 that is frequency dividing means, and the input clock 102 is frequency-divided. The frequency divider 171 is composed of a flip-flop with reset. By inputting the input clock 102 and the external reset signal 101 which is the second external signal to the frequency divider reset signal creating unit 172, the frequency divider reset signal 173 necessary for resetting the frequency divider 171 is obtained. The frequency divider reset signal creation unit 172 creates a signal at the falling edge of the input clock 102 and performs logical synthesis of this signal and the external reset signal 101. This divided cycle reset signal 173 is input to the reset terminal of the frequency divider 171. With these signals, an address signal 174 is obtained from the address signal generation circuit.
[0006]
12 and 13 are a configuration diagram of a conventional flat panel driving circuit and a diagram showing signals around the flat panel driving circuit, respectively. The VSYNC 142 signal is a vertical synchronization signal of the flat panel 141. The HSYNC143 signal is a horizontal synchronization signal of the flat panel 141. In order to drive the flat panel 141, it is necessary to give a signal to the electrodes arranged in the vertical and horizontal directions of the flat panel 141. The flat panel data line driving circuit 181 and the common line driving circuit 145 give signals to the electrodes. The conventional flat panel driving circuit described here corresponds to the data line driving circuit 181. In the input pixel data 146 which is panel display pixel data, pixel data for one horizontal period is transferred serially within one cycle of HSYNC143, and pixel data for one screen is transferred serially within one cycle of VSYNC142. The serial pixel data is input to the serial / parallel converter 182 and converted into parallel pixel data 183. The parallel pixel data 183 is converted into a panel driving signal 185 by which the flat panel 141 can be driven by the panel driving signal conversion unit 184 and output. Data input to the shaded portion of the input pixel data 146 is sent to the shaded portion of the parallel pixel data 183 and the shaded portion of the panel drive signal 185. Therefore, the panel driving signal 185 is output to a portion delayed by one cycle of the HSYNC 143 from the period when the serial input pixel data 146 is input.
[0007]
[Problems to be solved by the invention]
In order to improve the image quality and reduce the power consumption of the flat panel, it is necessary to incorporate a storage element in the flat panel driving circuit. However, a flat panel drive circuit that simply incorporates a memory circuit that operates with the above-described conventional address signal generation circuit has the following problems. In other words, in a flat panel drive circuit using a conventional address signal generation circuit and incorporating a storage element, pixel data converted in parallel is output after one cycle of the horizontal synchronization signal after serial pixel data for display is input. When the data is input to and output from the storage element, the horizontal synchronization signal is output with a delay of one cycle. As a result, the pixel data is output after two cycles of the horizontal synchronization signal after the serial pixel data is input. Normally, in the flat panel drive circuit, the pixel data is output after one cycle of the horizontal sync signal after the serial pixel data is input, so the matching with the other common line drive circuit that drives the flat panel cannot be achieved and display is possible. In this case, data that should originally be displayed on the second line is displayed shifted by one line so that it is displayed on the first line. In order to avoid this, it is necessary to change the drive circuit for the common panel of the flat panel or to change the signal for controlling the flat panel drive circuit, leading to an increase in cost.
[0008]
In view of the above problems, by changing the output timing of the address signal generation circuit necessary for the operation of the memory circuit, the signal and address cycle for changing the address even when the memory element is built in the circuit network are set. The use area of the memory circuit can be varied and specified only by the two external signals to be varied, and a peripheral circuit can be assembled in the same manner as when no memory element is built in the circuit network. Among the control signals sent from the flat panel controller in the flat panel drive circuit incorporating the memory elements corresponding to the panel display pixels, the latch pulse and the frame start signal can be used as the external signal without newly increasing the signal line. Automatic use range adjustment of the built-in memory element area according to the display line can be performed. This is suitable for the demand for narrowing the frame area in the flat panel. In addition, by incorporating a memory element, various panel driving methods are possible, so that a flat panel capable of improving image quality and reducing power consumption using the same signal as an external signal can be provided.
[0009]
The memory circuit of the present invention is a memory circuit including an address signal generation circuit that generates an address signal necessary for writing and reading data to and from the memory element, and changes the address based on a first external signal. Address change means, address cycle variable means for determining an address cycle based on a second external signal, signals received from the address change means and the address cycle variable means, and determined by the address cycle variable means The address signal generation circuit that changes an address in an address cycle; the storage element that inputs an address from the address signal generation circuit as a read address and inputs input data that is synchronized with the first external signal; A signal converter that converts the data read from the storage element into output data and outputs the output data; And the output data is output in the same phase that is synchronized with the first input signal and delayed by a predetermined period from the phase of the second external signal when the input data is input. The generation circuit includes a first signal conversion unit that converts the first external signal into a frequency dividing signal, a signal frequency dividing unit that divides the frequency dividing signal, and the first and second external signals. The signal generation means for creating a timing for holding the reset signal and the signal holding means in the frequency dividing means, and the signal holding means for holding the maximum frequency division value determined by the signal holding timing signal output from the signal frequency dividing means. Signal comparison means for comparing the value held in the signal holding means with the output signal from the frequency dividing means, and signal synthesis for logically converting the output signal from the frequency dividing means with the signal from the signal comparing means And And wherein the Rukoto.
[0011]
The flat panel drive circuit of the present invention includes the above storage circuit having a storage element corresponding to pixel data of the entire area or a part of the flat panel, and converts the data read from the storage element into a drive signal for output. And a signal converting unit.
[0012]
[Action]
According to the present invention, even when a memory circuit is incorporated in various circuit networks, a peripheral circuit can be configured in the same manner as when it does not exist inside.
[0013]
Further, in the address signal generation circuit used for the memory circuit, it is possible to cope with an arbitrary number of memory elements and addresses with the same external signal as in the past.
[0014]
Further, by incorporating the memory element in the flat panel drive circuit, various panel drive methods are possible, and the image quality of the panel can be improved and the power consumption can be reduced.
[0015]
【Example】
Hereinafter, a memory element that performs writing and reading is abbreviated as a memory element. Hereinafter, the high level of the signal is indicated by “H” and the low level is indicated by “L”. In order to make the logic easy to understand, the signal can be operated at “H” unless otherwise specified, and the switching of the count or the like will be described using the falling edge of the signal.
[0016]
1 and 2 are a circuit configuration diagram of a memory circuit according to the present invention and a diagram showing signals around the memory circuit, respectively. An input clock 102 that is a first external signal and an external reset signal 101 that is a second external signal are input to the memory element operation signal creation unit 103, and signals WR105, necessary for writing and reading data to and from the memory element 104, Signals such as RD 106 and PC 107 are created. The WR105 signal is a signal used for writing data to the memory element 104. The RD 106 signal is a signal used for reading data from the storage element 104. The PC107 signal is a precharge signal required for switching between the WR105 signal and the RD106 signal. The input clock 102 and the external reset signal 101 are input to an address signal generation circuit 108 including address changing means and address cycle varying means. The address signal 109 is output from the address signal generation circuit 108 so that the switching of the address signal 109 output from the address signal generation circuit 108 comes immediately after the data writing to the storage element 104 is completed. When the hatched portion of the storage element input data 110 input in synchronization with the input clock 102 is transferred, the storage element input data 110 is transferred to the address signal generation circuit 108 by the pulse indicated by the arrow of the WR105 signal. The first-stage address signal 109-1, the second-stage address signal 109-2, and the third-stage address signal 109-3, which are generated by the above, are taken into the storage element of the “L” portion. After that, the address indicated by the arrow of the RD106 signal outputs the memory element from the memory element selected with “L” for the address first stage signal 109-1, the address second stage signal 109-2, and the address third stage signal 109-3. The data written in the storage element indicated by the oblique line of the storage element input data 110 previously input to the portion indicated by the oblique line of the data 111 is read. The storage element output data 111 is synchronized with the input clock 102 by the synchronization unit 112 and the data is output to the shaded portion of the output data 113. In this way, the output data 113 is output during the period of the same address in the portion that is delayed by one cycle of the external reset signal 101, that is, one cycle of the address from the input portion. That is, b1, b2, b3,... Of the input data 110 to the memory circuit of the present invention are read to b1, b2, b3,.
[0017]
3, 4 and 5 are a block diagram of the address signal generating circuit of the present invention, an address signal generating circuit diagram, and a signal around the address signal generating circuit, respectively. An example of counting five input clocks is used. The input clock 102 which is the first external signal is converted into the count clock 122 by using a delay or the like by the frequency dividing signal creating unit 121 which is the first converting means for converting the signal into the frequency dividing signal. The count clock 122 is frequency-divided by a synchronous or asynchronous frequency divider 123 which is a frequency dividing means. The frequency divider 123 includes a flip-flop 124 with reset. By inputting the input clock 102 and the external reset signal 101 to the frequency divider reset signal and latch signal generation unit 125 as signal generation means, a frequency divider reset signal 126 required for resetting the frequency divider and a latch described later A signal 127 is obtained. The frequency divider reset signal and latch signal generator 125 performs logic synthesis of the input clock 102 and the external reset signal 101. The logically synthesized signal becomes a latch signal 127, and a signal generated by the rising edge of the latch signal 127 becomes a frequency divider reset signal 126. This frequency divider reset signal 126 is input to the reset terminal of the frequency divider 123. By these signals, the frequency divider 123 outputs a divided first stage signal 128-1, a divided second stage signal 128-2, and a divided third stage signal 128-3. These signals 128-1, 128-2, 128-3 are input to the latch unit 129, which is a signal holding means, by the latch signal 127 described above. As a result, the maximum count value counted by the frequency divider 123 is latched in the latch unit 129. In this case, the latched signals are a latch first stage signal 130-1 “H”, a latch second stage signal 130-2 “L”, and a latch third stage signal 130-3 “H”. Latch first stage signal 130-1, latch second stage signal 130-2, latch third stage signal 130-3 are divided first stage signal 128-1, divided second stage signal 128-2, divided third stage signal, respectively. 128-3 is latched. The signal comparator 131, which is a signal comparison means, compares the latched signals 130-1, 130-2, 130-3 with the frequency-divided signals 128-1, 128-2, 128-3 of the frequency divider 123, and compares the signals at the portions where the signals match. The device output signal 132 operates to become “H”. In the signal synthesizer 133 as the second signal conversion means, the signal comparator output signal 132 output from the signal comparator 131 and the frequency divider output signals 128-1, 128-2, 128-3 output from the frequency divider 123, respectively. And the address first stage signal 134-1, the address second stage signal 134-2, and the address third stage signal 134-3 are obtained. This address first stage signal 134-1 is a divided first stage signal 128-1, latch first stage signal 130-1, and this address second stage signal 134-2 is divided second stage signal 128-2, latch second stage. The address third stage signal 134-3 corresponds to the signal 130-2, and the divided third stage signal 128-3 and the latch third stage signal 130-3, respectively.
[0018]
6 and 7 are a block diagram of the flat panel drive circuit according to the present invention and signals around the flat panel drive circuit, respectively. The VSYNC 142 signal is a vertical synchronization signal of the flat panel 141. The HSYNC143 signal is a horizontal synchronization signal of the flat panel 141. In order to drive the flat panel 141, it is necessary to give a signal to the electrodes arranged in the vertical and horizontal directions of the flat panel 141. The flat panel data line driving circuit 144 and the common line driving circuit 145 give signals to the electrodes. The flat panel drive circuit of the present invention corresponds to the data line drive circuit 144. As input pixel data 146 displayed on the panel, pixel data for one horizontal period is serially transferred within one cycle of HSYNC143, and pixel data for one screen is transferred serially within one cycle of VSYNC142. The input pixel data 146 is input to the serial / parallel conversion and storage element operation signal generation unit 147, and the serial input pixel data 146 is converted into parallel pixel data 148 for one horizontal period and is necessary for the operation of the storage element. WR105, RD106, PC107 signal and address signal 109 are generated. The address signal 109 is output from the address signal generation circuit of the present invention. The parallel pixel data 148 is read into the memory circuit of the present invention. The hatched portion of the input pixel data 146 is converted into the shaded portion of the parallel pixel data 148 by serial / parallel conversion, written into the storage element by the pulse indicated by the arrow of the WR105 signal, and the pulse indicated by the arrow of the RD106 signal. Data is read from the storage element unit 150 to the portion indicated by the oblique lines in the storage element unit output data 149. The data is synchronized by the synchronization unit 151 by the HSYNC 143 signal, and the data is output to the hatched portion of the post-synchronization data 152. The post-synchronization data 152 is converted into a panel drive signal 154, which is a signal that can be driven by the panel drive signal converter 153, and the data is output to the hatched portion. Therefore, the data for the flat panel is output in a period delayed by one cycle of VSYNC 142 and one cycle of HSYNC 143 from the period when the serial input pixel data 146 is input.
[0019]
【The invention's effect】
The memory circuit of the present invention changes the output timing of the address signal generation circuit necessary for its operation, thereby changing the address change signal and the address cycle even when the memory element is built in the circuit network. The external area of the memory circuit, that is, the first and second external signals alone can be used to change and specify the memory circuit use area, and a peripheral circuit can be assembled in the same manner as when no memory element is built in the circuit network. . Further, when added inside various circuit networks, peripheral circuits can be configured in the same manner as when the memory circuit does not exist inside. Therefore, it is possible to reduce the cost by reducing the number of new peripheral circuits .
[0020]
The address signal generation circuit according to the present invention is used for the operation of the memory element, but it is possible to change and specify the use area of the memory circuit only by a signal for changing the address and two external signals for changing the cycle of the address. In addition, any number of storage elements and addresses can be handled with the same external signal as in the prior art, and the circuit can be simplified.
[0021]
Since the flat panel drive circuit of the present invention incorporates a storage element corresponding to the panel display pixel, it is possible to variously convert signals supplied to the flat panel, which are signals output from the flat panel drive circuit. For example, the drive method of selecting several lines of the panel at the same time improves the image quality of the flat panel, and when a still image is displayed on the panel screen, the panel is driven by a signal from the built-in storage circuit without using an external image signal The driving method for performing the above-described effects can reduce the power consumption of the flat panel. In addition, the latch pulse and frame start signal among the control signals sent from the flat panel controller can be used as the external signal, and automatic use range adjustment of the built-in storage element area according to the display line without newly increasing the signal line Can do. This is suitable for the demand for narrowing the frame area of the flat panel.
Further, since various panel driving methods are possible by incorporating a memory element, a flat panel capable of improving image quality and reducing power consumption using the same signal as an external signal can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a memory circuit of the present invention.
FIG. 2 is a diagram showing signals around a memory circuit of the present invention.
FIG. 3 is a configuration diagram of an address signal generation circuit of the present invention.
FIG. 4 is a circuit diagram of an address signal generation circuit of the present invention.
FIG. 5 is a diagram showing signals around an address signal generation circuit of the present invention.
FIG. 6 is a configuration diagram of a flat panel driving circuit of the present invention.
FIG. 7 is a diagram showing signals around the flat panel drive circuit of the present invention.
FIG. 8 is a configuration diagram of a conventional memory circuit.
FIG. 9 is a diagram showing signals around a conventional memory circuit.
FIG. 10 is a configuration diagram of a conventional address signal generation circuit.
FIG. 11 is a diagram showing signals around a conventional address signal generation circuit.
FIG. 12 is a configuration diagram of a conventional flat panel drive circuit.
FIG. 13 is a diagram showing signals around a conventional flat panel drive circuit.
[Explanation of symbols]
101 ・ ・ ・ ・ ・ External reset signal
102 ・ ・ ・ ・ ・ Input clock
103 ... Memory element operation signal generator
104 ・ ・ ・ ・ ・ Memory element
105 WR
106 ・ ・ ・ ・ ・ RD
107 ・ ・ ・ ・ ・ PC
108 ... Address signal generator
109 ... Address signal
110 ・ ・ ・ ・ ・ Storage element input data
111 ・ ・ ・ ・ ・ Memory element output data
112 ・ ・ ・ ・ ・ Synchronizer
113 ・ ・ ・ ・ ・ Output data
121 ・ ・ ・ ・ ・ Divide signal generator
122 ... count clock
123 ・ ・ ・ ・ ・ Divider
124 ・ ・ ・ ・ ・ Flip-flop with reset
125 ... Divider reset signal and latch signal generator
126 ・ ・ ・ ・ ・ Divider reset signal
127 ... Latch signal
128-1 ・ ・ ・ Division first stage signal
128-2 ... Divided second stage signal
128-3: Divided third stage signal
129 ... Latch part
130-1 ・ ・ ・ Latch first stage signal
130-2 ・ ・ ・ Latch second stage signal
130-3 ・ ・ ・ Latch third stage signal
131 ・ ・ ・ ・ ・ Signal comparator
132 ・ ・ ・ ・ ・ Signal comparator output signal
133 ・ ・ ・ ・ ・ Signal synthesis unit
134-1 ... Address first stage signal
134-2 ・ ・ ・ Address second stage signal
134-3 ・ ・ ・ Address third stage signal
141 ・ ・ ・ ・ ・ Flat panel
142 ... VSYNC
143 ... HSYNC
144 ・ ・ ・ ・ ・ Data line drive circuit
145 ・ ・ ・ ・ ・ Common line drive circuit
146 ・ ・ ・ ・ ・ Input pixel data
147 ・ ・ ・ ・ ・ Serial / parallel conversion and memory element operation signal generator
148 ・ ・ ・ ・ ・ Parallel pixel data
149 ・ ・ ・ ・ ・ Storage element output data
150 ... Memory element section
151 ・ ・ ・ ・ ・ Synchronizer
152 ・ ・ ・ ・ ・ Data after synchronization
153 ... Panel drive signal converter
154: Panel drive signal
161 ... Address signal generator
162-1 ... Address first step signal
162-2 ・ ・ ・ Address second stage signal
162-3 Address third stage signal
163 ・ ・ ・ ・ ・ Storage element output data
164 ・ ・ ・ ・ ・ Output data
171: Divider
172 ・ ・ ・ ・ ・ Divider reset signal generator
173 ・ ・ ・ ・ ・ Divider reset signal
174 ・ ・ ・ ・ ・ Address signal
182 ・ ・ ・ ・ ・ Serial / parallel converter
183 ... Parallel pixel data
184 ... Panel drive signal converter
185 ・ ・ ・ ・ ・ Panel drive signal

Claims (2)

A storage circuit including an address signal generation circuit that generates an address signal necessary for writing and reading data to and from the storage element,
Address changing means for changing the address based on the first external signal;
An address period variable means for determining an address period based on the second external signal;
Receiving the signals from the address changing means and the address cycle varying means, and changing the address in an address cycle determined by the address cycle varying means;
The storage element that inputs an address from the address signal generation circuit as a read address and inputs input data synchronized with the first external signal;
A signal converter that converts the data read from the storage element into output data and outputs the output data;
Have
The output data is output in the same phase that is synchronized with the first input signal and delayed by a predetermined period from the phase of the second external signal when the input data is input,
The address signal generation circuit includes:
First signal converting means for converting the first external signal into a frequency dividing signal;
Signal dividing means for dividing the frequency dividing signal;
A signal generating means for creating a timing for holding the reset signal and the signal holding means of the frequency dividing means from the first and second external signals;
The signal holding means for holding the maximum frequency division value determined by the signal holding timing signal output from the signal frequency dividing means;
Signal comparison means for comparing the value held in the signal holding means with the output signal from the frequency dividing means;
A signal synthesizer for logically converting the output signal from the frequency dividing means with the signal from the signal comparing means;
A memory circuit comprising: The storage circuit according to claim 1, further comprising a storage element corresponding to pixel data of all areas or a part of the area of the flat panel; and a signal conversion unit that converts the data read from the storage element into a drive signal and outputs the drive signal; A flat panel drive circuit comprising:

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