JP2535848B2 - Method and device for changing synchronous clock - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock changing method and device suitable for use when changing a master clock (dot clock pulse) in, for example, an image display circuit or the like. .

"Prior Art" In an image display circuit for displaying an image on a CRT display device or the like, a dot clock pulse having a cycle corresponding to a 1-dot display timing of a display surface is used as a master clock. Then, each part of the image display circuit operates based on the dot clock pulse.

On the other hand, in image display, various display modes are usually set, and the number of dots in one screen (the number of dots in the horizontal and vertical directions) often differs depending on each mode. Therefore, the image display circuit needs to have a function of appropriately switching the dot clock pulse to one having a frequency according to the display mode.

In this case, the conventional dot clock pulse switching method is, for example, a method of supplying dot clock pulses of various frequencies to a plurality of input terminals of a multiplexer and switching the multiplexer to select the dot clock pulse.

[Problems to be Solved by the Invention] When dot clock pulses are switched by a multiplexer, a pulse with an extremely short "1" level period or "0" level period may be output immediately after switching. Then, when such a pulse is output, malfunction occurs in the register, the memory section, and the like in the circuit, and the data to be held is destroyed or erased. For example, in the case where the color palette that converts a color code into RGB digital color data must maintain the dot clock pulse "1" level period (active side level period) for a predetermined period for its stable operation, When a dot clock pulse with a short "1" level period was output, the data in the color palette was destroyed or erased, and the subsequent image display became impossible.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a method of changing a synchronous clock that does not cause a malfunction in the circuit even when the clock (dot clock pulse or the like) used as the synchronous clock in the circuit is changed.

"Means for Solving Problems" The present invention has the following means in order to solve the above problems.

First, a synchronous clock changing method according to the present invention is a method of changing a plurality of synchronous clocks having different frequencies in which a first level and a second level are alternately repeated. One of
Performing a first clock selection process for selecting and outputting two clocks, and (b) a clock supplied from the first clock selection process to a first input end and a predetermined frequency supplied to a second input end. Among the alternative clocks, the first clock switching process of outputting the clock supplied to the outer first input terminal in the steady state as a master clock is performed, and (c) the first clock selection process outputs the clock. When switching the clocks, a first level fixing process of fixing the master clock to the first level is performed at the timing when the clock supplied to the first input terminal reaches the first level. And (d) at a timing when the alternative clock becomes the first level after the first level fixing process, the alternative clock is set to the master clock. Second output as
And (e) a second clock selection process for selecting any clock other than the clock as an output to the first input terminal while the alternative clock is being output as a master clock. And (f) fixing the master clock to the first level at the timing when the alternative clock used as the master clock becomes the first level after the second clock selection process. A second level fixing process is performed, and (g) at a timing when the clock supplied to the first input terminal becomes the first level after the second level fixing process, the first input A third clock that outputs the clock supplied to the end as the master clock
The clock switching process is performed.

Also, in the synchronous clock changing device according to the present invention, the synchronous clock changing device is a plural synchronous clock changing device having different frequencies, in which the first level and the second level are alternately repeated. Clock selecting means for selecting one of the clocks based on a selection signal and supplying the selected clock to the first input terminal; and a clock supplied to the first input terminal or the second clock.
Of the alternative clocks supplied to the input terminal of the clock switching means for selecting one of the alternative clocks based on the switching signal and outputting it as a master clock, and the master clock output from the clock switching means as a level fixed signal. Based on the level fixing means for fixing to the first level based on the above, the switching signal for instructing the selection of the clock supplied to the first input terminal is output in the steady state, and the first switching instruction signal is output. When input, the level fixed signal is output in synchronization with the first falling timing of the master clock, and the switching signal for instructing selection of the alternative clock is output in synchronization with the next falling timing, When the second switching instruction signal is input,
The level fixed signal is output in synchronization with the first falling timing of the master clock, and the switching signal for instructing the selection of the clock supplied to the first input terminal in synchronization with the next falling timing. And a switching control means for outputting the first switching instruction signal, and after outputting the first switching instruction signal, the clock switching means switches the master clock to the alternative clock. Switching instruction means for outputting the selection signal and for outputting the second switching instruction signal after a predetermined time has elapsed from the output of the selection signal.

"Operation" When the frequency of the master clock is switched, the second level period is not shortened.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, in which 1 is an image display circuit.
The part of the image display circuit 1 shown in the figure is a part related to the present invention among the constituent elements, and the part for performing image control is the same as a general part, so that the illustration thereof is omitted.

The image display circuit 1 is configured to display an image on a CRT display device or the like based on the image data in the video RAM under the control of the CPU, and the circuit parts (color palette, register, etc.) It operates based on the "1" level period (active side period) of MCK.

Next, 2 and 3 are registers, respectively, to which select data for selecting _{one of the} dot clock pulses DCK1 to DCKn is supplied from the CPU. In this case, the previous select data is stored in the register 3, and the first select data is stored in the register 2. Reference numeral 5 is a comparator which compares the output data of the registers 2 and 3 and outputs a signal S ₁ when these are different. 6 is a control signal generator which outputs a signal SCA (“1” signal) after a predetermined time when the signal S ₁ is supplied, and outputs a signal SCB (“1” signal) after a further predetermined time elapses after the output of the signal SCA. Circuit. The details of the output timing and pulse width of each of the signals SCA and SCB will be described later.

Reference numeral 10 is a register, and the select data in the register 2 is written by the writing operation of the image display circuit 1. 11 is a selector which dot clock pulses DCK1~DCKn to the input terminal is supplied, and selects the dot clock pulses corresponding to the select data register 10, and supplies to the input end T ₂ of the clock switching circuit 7. Further, the selector 11 changes the dot clock pulse DCKn to the clock pulse FCK.
Is supplied to the input terminal T ₁ of the clock switching circuit 7. The clock switching circuit 7 is a circuit which supplies the dot clock pulse supplied from the selector 11 to each part of the image display circuit 1 as the master clock MCK, and the details thereof are as shown in FIG.

In FIG. 2, reference numeral 20 is a selector, and the terminal SA is "1".
When the signal is supplied, the input terminal B is selected, and when the "0" signal is supplied to the terminal SA, the input terminal A is selected. This selector 20
An alternative clock pulse FCK and a dot clock pulse DCK are supplied to the input terminals A and B of the respective terminals via terminals T ₁ and T ₂ . Therefore, the output pulse of the selector 20 is either one of the clock pulse FCK and the dot clock pulse DCK. In this case, when the image display circuit 1 is performing a normal image display operation, the input terminal B of the selector 20 is selected and the dot clock pulse DCK is output. Output signal YCK of this selector 20
Is output as the master clock MCK via the AND gate ANI.

Reference numerals 21, 22, 23, 24 and 25 are D flip-flops which output signals CCE, CLCI, CKI, CKS and CC, respectively. OR1 to OR3 are OR gates, and INV1 to INV4 are inverters. Signal RESE
T is a reset signal output from a part (not shown) of the image display circuit 1 at a predetermined timing (when the power is turned on, etc.), and is a D flip-flop 21, 22, 23, 24 directly or via OR gates OR1, OR3. , 25 reset terminals R are supplied. Further, in the D flip-flop 24, the signal SCB is supplied to its clock terminal via the delay 27, the signal SCA is supplied to the reset terminal R via the delay 28 and the OR gate OR1, and the data input terminal D is always "1". A signal is supplied.

 Next, the operation of the above circuit will be described.

First, the CPU writes select data in the register 2. As a result, the image display circuit 1 writes the select data written in the register 2 into the register 10 based on the control signal sent from the control signal generating circuit 6. If the select data written in the register 2 by the CPU is data for selecting a dot clock pulse different from the one currently selected, the register 2,
Since the output data of 3 is different, the comparator 5 outputs the signal S1.
Is output. When the signal S1 is supplied, the control signal generation circuit 6 outputs the signal SCA. Assuming that the signal SCA is output at time t _{1 as} shown in FIG. 3 (e), this signal SCA is supplied to the reset terminal R of the D flip-flop 24 via the OR gate OR 1 after passing through the delay 28. , D flip-flop 24 is reset. When the D flip-flop 24 is reset, the signal CKS becomes the "0" signal as shown in FIG. Further, the signal SCA is supplied to the data input terminal D of the D flip-flops 21 and 23 via the OR gate OR2. And the pulse YC after time t _1.
At the first falling time t ₂ of K (see FIG. 3),
When the output signals of the inverters INV1 and INV2 rise, the D flip-flops 21, 22 and 23 take in data all at once. At this time, since the signal SCA (“1” signal) is supplied to the data input terminal D of the D flip-flops 21 and 23, at time t ₂ , the output signals CCE and CKI of the D flip-flops 21 and 23 are output. Rises to the "1" signal (Fig. 3 (re),
(See (f)). Then, when the signal CKI rises, the output signal of the inverter INV4 falls to the "0" signal, and the AND gate AN1 is closed thereafter, and the master clock MCK is fixed to the "0" level (level on the inactive side). It
Further, when the output signal of the inverter INV4 falls, the output signal of the inverter INV3 rises, whereby the D flip-flop 25 takes in the signal CKS. At this time, signal C
Since KS is a “0” signal, D flip-flop 25
The output signal CC of is a "0" signal as shown in FIG. When this signal CC becomes “0” signal, the terminal of selector 20
The "0" signal is supplied to SA, whereby the input terminal A is selected and thereafter the alternative clock pulse FCK is output as the signal YCK. Then, at time t ₃ when the signal YCK next falling again performs D flip-flop 21, 22 and 23 are data acquisition, as a result, signal CCE, the value of the CKI maintains "1" signal unchanged However, the value of the signal CLCI is inverted to become a "1" signal (see FIG. 3 (n)). Then, when the signal CLCI becomes the "1" signal, this "1" signal is supplied to the reset terminal of the D flip-flop 23 via the OR gate OR3,
Thus, the output signal CKI of the D flip-flop 23 becomes "0" signal (see time t ₄ of FIG. 3 (f)). Signal CK
When I becomes "0" signal, the output signal of the inverter INV4 becomes "1", and the AND gate AN1 is opened. When AND gate AN1 is closed, output signal YCK of selector 20
Is output as the master clock MCK. The signal YCK is switched from the dot clock pulse DCK to the alternative clock pulse FCK when the signal CC becomes the “0” signal, so that the alternative clock pulse is output as the master clock MCK at time t ₄ . It is FCK. Also,
AND gate AN1 is triggered by the falling edge of signal YCK.
Is open, the signal YCK is at “0” level at time t ₄ . Therefore, the next "1" signal period (active side level period) of the signal YCK is output without omission.

Thus, from time t ₁ when signal SCA rises to time t ₄
By the operation up to, the master clock MCK is switched from the dot clock pulse DCK to the alternative clock pulse FCK. The master clock MCK for this switching is
As shown in FIG. 3D, a pulse having an extremely short “1” signal period is not output, and the pulse width of the alternative clock pulse FCK or DCK is always secured. In this way, a certain pulse width is secured because the AND gate AN1 is closed in synchronization with the rising edge of the signal SCA instructing the switching start of the dot clock pulse, and the clock pulse DCK → FCK
This is because the AND gate returns to the open state during the "0" level period of the alternative clock pulse FCK after the conversion of (1).

Next, at time t ₅ , when the signal YCK falls, D
Flip-flops 21,22,23 take in data,
At this point, the respective output signals CCE, CLCI, CKI retain the previous values. Then, at time t ₆ , the signal SCA falls, and at time t ₇ , the D flip-flop 21 outputs the signal.
The signal CCE is taken into the SCA and the signal CCE is set to the “0” signal (see FIG. 3 (i)). The pulse width of this signal SCA corresponds to the time sufficient for the master clock MCK to be converted from the dot clock pulse DCK to the alternative clock pulse FCK,
It is set in advance in the control signal generation circuit 6 (see FIG. 1).

Then, at time t ₈ , when the signal YCK falls,
As shown in FIG. 3 (n), the signal CLCI falls and the reset state of the D flip-flop 23 is released.

On the other hand, the selector 11 shown in FIG. 1 selects one of the dot clock pulses DCK _{1 to} DCKn based on the selector data written in the register 10 by the image display circuit 1. Now select data is dot clock pulse
If the data indicates DCK ₁ , the selector 11 outputs the dot clock pulse DCK ₁ after a predetermined operation time. The timing is set such that the time when this switching is completed is after the time when the signal CKI shown in FIG. 3F rises and the AND gate AN1 is closed.

Next, the control signal generation circuit 6 outputs the signal SCB (“1”) at a timing sufficient to complete the operation shown in FIG.
Signal) is output. Then, the time t shown in FIG.
_{At 10} , if the signal SCB is output, this output S
CB is supplied to the clock terminal of the D flip-flop 24 via the delay 27, the D flip-flop 24 is reset, and the signal CKS becomes the "1" signal (see (g) in the same figure). Next, when the signal YCK falls at time t _11, D flip-flops 21, 22, 23 perform data capture rises the output signal of the inverter INV1, INV2. As a result, the signal
CCE, CLCI, and CKI become "1", "0", and "1" signals, respectively. Signal CK
When I becomes the "1" signal, the output signal of the inverter INV4 becomes the "0" signal, and the AND gate AN1 is closed. When the AND gate AN1 is closed, the master clock MCK is fixed at "0" level. Also, the signal C
When KI becomes the "1" signal, the output signal of the inverter INV3 rises, and the D flip-flop 25 takes in the signal CKS.
At this time, the signal CKS is at "1" level,
The output signal CC of the D flip-flop 25 becomes the "1" signal.
When the signal CC becomes the "1" signal, the input terminal B of the selector 20 is selected and the dot clock pulse DCK is output as the output signal YCK. At this time, as the dot clock pulse DCK,
Dot clock pulse DCK ₁ by the switching action of selector 11
Is selected, the dot clock pulse DCK ₁ is output as the signal YCK after time t ₁₁ .

In this case, the signal YCK immediately after switching may output a pulse having a short “1” level period as shown in FIG. 4C, depending on the switching timing. At this point, the AND gate AN1 is turned on. Signal Y because it is closed
CK is not output as master clock MCK.

Next, at time t ₁₂ , when the signal YCK becomes “0” signal, the output signals of the inverters INV1 and INV2 rise, and D
The flip-flops 21, 22, 23 perform data reading.
In this case, the output signal changes only in the D flip-flop.
There is only 22 and the signal CLCI changes from the “0” signal to the “1” signal (see FIG. 4 (n)). As a result, the D flip-flop 23 is reset and the signal CKI falls to the "0" signal as shown in FIG. As a result, the inverter IN
The output signal of V4 becomes "1" signal, and AND gate AN1 is opened. Therefore, after this time point, the signal YCK, that is, the newly selected dot clock pulse DCK ₁ is output as the master clock MCK. In this case, the timing when the AND gate AN1 opens is
Since the signal YCK is at the “0” level, the signal YCK (dot clock pulse DCK ₁ ) is output with a regular pulse width from the next rising time t ₁₃ of the signal YCK. With the above operation, the switching from the alternative clock pulse FCK to the dot clock pulse DCK is completed.

Next, at time t ₁₄ , the control signal generation circuit 6 outputs the signal S
Stop CB. Time t ₁₀ ~t ₁₄ this signal SCB is output
Alternate clock pulse FCK to dot clock pulse D
A time sufficient for the switching operation to CK is set in advance in the control signal generation circuit 6. And the signal
SCB becomes “0” signal, and at time t ₁₅ ,
When YCK falls, the D flip-flops 21, 22, 23 take in data, and as a result, the signal CCE becomes a "0" signal. At time t ₁₆ similar data capture and the is performed, thereby, the signal CLCI becomes "0" signal. With the above time t ₁₄ after the operation, returning all the output signals of the D flip-flop 21 to 25 the initial state (the value of the start point of FIG. 3). When the CPU writes the select data for selecting a dot clock pulse different from the one currently selected in the register 2, the operations shown in FIGS. 3 and 4 described above are performed again to change the dot clock pulse. Is done.

[Advantages of the Invention] As described above, the synchronous clock changing method according to the present invention is a method of changing a plurality of synchronous clocks having different frequencies in which the first level and the second level are alternately repeated. A first clock selection process of selecting and outputting any one of a plurality of clocks having different frequencies is performed, and a clock supplied to the first input terminal from the first clock selection process and a second clock Of the alternative clocks of the predetermined frequency supplied to the input terminal of the first clock, the clock supplied to the first input terminal in the steady state is output as the master clock, When switching the clock output by the selection process, at the timing when the clock supplied to the first input terminal reaches the first level. , Performing a first level fixing process of fixing the master clock to the first level, and changing the alternative clock at the timing when the alternative clock becomes the first level after the first level fixing process. A second clock switching process for outputting as the master clock, and selecting any clock other than the clock as an output to the first input terminal while the alternative clock is being output as the master clock. The second clock selection process is performed, and the master clock is set to the first level at the timing when the alternative clock used as the master clock becomes the first level after the second clock selection process. A second level fixing process for fixing is performed, and after the second level fixing process, it is supplied to the first input terminal. At the timing when the lock is turned to the first level, a third clock switching process of outputting a clock that is supplied to the input terminal of the first as the master clock.

Further, in the synchronous clock changing device according to the present invention, the synchronous clock changing device is a changing device of a plurality of synchronous clocks having different frequencies, in which the first level and the second level are alternately repeated. Clock selecting means for selecting any one of the clocks based on a selection signal and supplying it to the first input terminal, and a clock supplied to the first input terminal or an alternative supplied to the second input terminal A clock switching unit that selects one of the clocks based on a switching signal and outputs it as a master clock, and the master clock output from the clock switching unit is set to the first level based on a level fixing signal. Both the level fixing means for fixing and the output of the switching signal for instructing the selection of the clock supplied to the first input terminal in the steady state. , The first switching instruction signal is input, the level fixed signal is output in synchronization with the first falling timing of the master clock, and the selection of the alternative clock is instructed in synchronization with the next falling timing. When the switching signal is output and the second switching instruction signal is input, the level fixed signal is output in synchronization with the first falling timing of the master clock,
Switching control means for outputting the switching signal for instructing selection of the clock supplied to the first input terminal in synchronization with the next fall timing, and for outputting the first switching instruction signal, After the switching instruction signal of No. 1 is output, the selection signal is output at the timing when the master clock is switched to the alternative clock in the clock switching unit, and the second signal is output after a predetermined time has elapsed from the output of the selection signal. Since the switching instruction means for outputting the switching instruction signal is provided, the second level period of the master clock does not become short when the frequency of the master clock is switched by switching a plurality of clocks, whereby each circuit portion It is possible to obtain the effect of preventing the malfunction of.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a block diagram showing the configuration of the clock switching circuit 7 shown in FIG. 1, and FIG. 3 is a waveform diagram of each part of the circuit when the master clock is switched from a dot clock pulse to a predetermined clock pulse in the same embodiment. FIG. 4 is a waveform diagram of each part of the circuit when the master clock is switched from a predetermined clock pulse to a dot clock pulse in the embodiment. 1 ... Image display circuit, 2, 3, 10 ... Register, 5 ... Comparator, 6 ... Control signal generation circuit, 7 ... Clock switching circuit, 11 ... Selector, 20 ... Selector, 21-25 ... …
D flip-flop.

Claims (2)

(57) [Claims] 1. A method of changing a plurality of synchronous clocks having different frequencies, wherein a first level and a second level are alternately repeated, wherein any one of a plurality of clocks having different frequencies is used.
Performing a first clock selection process for selecting and outputting two clocks, and (b) a clock supplied from the first clock selection process to a first input end and a predetermined frequency supplied to a second input end. Of the alternative clocks, the first clock switching process for outputting the clock supplied to the first input terminal in the steady state as the master clock is performed, and (c) the first clock selection process outputs the clock. When switching the clocks, a first level fixing process of fixing the master clock to the first level is performed at the timing when the clock supplied to the first input terminal reaches the first level. And (d) at a timing when the alternative clock becomes the first level after the first level fixing process, the alternative clock is set to the master clock. Second output as
And (e) a second clock selection process for selecting any clock other than the clock as an output to the first input terminal while the alternative clock is being output as a master clock. And (f) fixing the master clock to the first level at the timing when the alternative clock used as the master clock becomes the first level after the second clock selection process. A second level fixing process is performed, and (g) at a timing when the clock supplied to the first input terminal becomes the first level after the second level fixing process, the first input A third clock that outputs the clock supplied to the end as the master clock
A method for changing a synchronous clock, characterized in that the clock switching process is performed. 2. A change device for a plurality of synchronous clocks having different frequencies, which alternately repeats a first level and a second level, wherein any one of a plurality of clocks having different frequencies is used as a selection signal. A clock selecting means which is selected based on a switching signal and is supplied to the first input terminal; and a clock which is supplied to the first input terminal or an alternative clock which is supplied to the second input terminal, based on a switching signal. Clock switching means for selecting one of them and outputting it as a master clock; level fixing means for fixing the master clock output from the clock switching means to the first level based on a level fixing signal; Outputs the switching signal instructing the selection of the clock supplied to the first input terminal,
When the first switching instruction signal is input, the level fixing signal is output in synchronization with the first falling timing of the master clock, and the selection of the alternative clock is instructed in synchronization with the next falling timing. When the switching signal is output and the second switching instruction signal is input, the level fixing signal is output in synchronization with the first falling timing of the master clock and in synchronization with the next falling timing. And a switching control means for outputting the switching signal for instructing selection of the clock supplied to the first input terminal; and for outputting the first switching instruction signal and the first switching instruction signal. After that, the selection signal is output at the timing when the master clock is switched to the alternative clock in the clock switching means, and from the output of the selection signal. A switching instruction changing means for outputting the second switching instruction signal after a lapse of a predetermined time, and a synchronizing clock changing device.