JPH0193928A - Dynamic programmable logic array - Google Patents

Abstract

PURPOSE:To most suitably operate an input latch, an AND logic matrix, an OR logic matrix, and an output latch by providing an output latch circuit which latches an output from the OR logic matrix by a third clock. CONSTITUTION:An input latch circuit 2 operated by a clock signal CLK1, an AND logic matrix 1, a clock driver 41 which generates a clock signal CLK2 by the clock signal CLK1 and the output of a delay circuit 3 on the AND logic matrix 1, and an OR logic matrix 6 operated by the clock CLK2 are provided. A clock driver 42 which generates a clock signal CLK3 by the clock signal CLK1 and the output of a delay circuit 6 on the OR logic matrix 5 and an output latch circuit 7 operated by the clock CLK3 are provided. Thus, the input latch circuit 2, the AND logic matrix 1, the OR logic matrix 5, and the output latch circuit 7 are operated at optimum timing only by the clock signal CLK1 given from the outside.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic program logic array (
The present invention relates to a dynamic PLA (hereinafter referred to as a PLA), and particularly to a dynamic PLA having a circuit that automatically generates optimal timing for the operation of an OR logic matrix and an output latch circuit.

[Conventional technology]

Conventionally, as shown in FIG. 5, this dynamic type PLA is a synthesis system in which an AND logic matrix 1 operated by a clock signal CLKI, and a delay circuit 3 on the tarock signal CLKI and the AND logic matrix 1 are synthesized by a clock driver 4. For example, the 1986 IEICE Comprehensive National Conference Collected Papers.

361).

[The good luck point that the invention attempts to solve]

The above-mentioned conventional dynamic PLA has the disadvantage that, since there is no latch circuit on the output side, an invalid signal is output from the PLA during the period from when the OR logic matrix 5 starts precharging until the logic is determined. . A circuit that receives the output of the PLA as an input requires a circuit that latches the output of the PLA and a clock generation circuit that optimally operates the latch circuit.

The purpose of the present invention is to solve such problems and provide a dynamic PLA in which the input latch, AND logic matrix, OR logic matrix, and output latch operate optimally by providing only one tarlock. .

[Means for solving problems]

The dynamic PLA of the present invention includes an input latch circuit that latches an input signal using a first clock, an AND logic matrix that inputs the output from the input latch circuit, and a combination of the first clock and the AND logic matrix. a first clock driver that generates a second clock from the output of the first delay circuit; an OR logic matrix that receives signals from the AND logic matrix and operates based on the second clock; a second tally driver that generates a third tally from a clock and the output of the second delay circuit on the OR logic matrix; and an output latch that latches the output of the OR logic matrix using the third tally. It is characterized by comprising a circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are a taro chart and its circuit diagram showing one embodiment of the present invention. In the figure, 1 is an AND logic matrix, 2 is an input latch circuit, 3 is a delay circuit configured on the AND logic matrix, 41 and 42 are clock drivers, 5 is an OR logic matrix, and 6 is a delay circuit configured on the OR logic matrix. 7 is an output latch circuit.

FIG. 3 is a timing diagram showing the operation of FIG. 1.

When the clock signal CLKI falls, the tarlock signal C
LK2. CLK3 falls, AND logic matrix 1 and OR logic matrix 5 start precharging, and output latch circuit 7 latches the output signal. clock signal C
When LKI rises, the input latch circuit 2 latches the value at that time.

The input signal from the input terminal 8 of the PLA enters the AND logic matrix 1 at this time. At this time, clock signal CL
K2. CLK3 is at LOW level, OR logic matrix 5 is precharging, and output latch circuit 7 is latching. When the input signal enters the AND logic matrix 1 and the value in the AND logic matrix 1 is determined, the delay circuit 3 outputs the clock signal CLK.
2 rises, and the value of AND logic matrix 1 is input into OR logic matrix 5. At this time, clock signal CL
K3 is at LOW level and the output latch circuit 7 is latching. When the value in the OR logic matrix 5 is determined, the delay circuit 6 causes the clock signal CLK3 to rise, and the output latch circuit 7 outputs a new output signal.

FIG. 4 is a block diagram of an application example of the PLA of this embodiment. Since the dynamic type PLA of this embodiment includes the input latch circuit 2 and the output latch circuit 7, simply connecting a part of the output of the output latch circuit 7 to the input of the input latch circuit 2 through the feedback line 20, A j-sequential circuit can be constructed. Moreover, as mentioned above, it can operate with only one externally applied clock.

The delay circuit 3 on the AND logic matrix 1 of this embodiment is as follows:
The number of transistor connections is determined by the number of transistors (PLA basic cells) connected to each product term line 9 of the AND logic matrix 1, and even if the size of the AND logic matrix 1 and the transistor utilization rate of the matrix change, the optimal timing can occur. Further, the delay circuit 6 on the OR logic matrix 5 can be similarly optimized by considering one output line.

〔Effect of the invention〕

As explained above, in the present invention, the clock signal CLK
1, an input latch circuit and an AND logic matrix that operate based on the clock signal CLKI, a clock driver that generates the clock signal CLK2 from the output of the delay circuit on the AND logic matrix, an OR logic matrix that operates based on the clock signal CLK2, and a clock signal CLKI. CLKI
By including a clock driver that generates a clock signal CLK3 from the output of a delay circuit on an OR logic matrix, and an output latch circuit that operates based on the clock signal CLK3, the input latch circuit and the AND Logical matrix, ○
The R logic matrix and output latch circuit can be operated at optimal timing. Furthermore, since it has an output latch circuit, no invalid signal is output from the PLA.

Furthermore, as an application, a dynamic sequential circuit can be constructed simply by feeding back the output to the input.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram showing the operation of FIG. 1, FIG. 4 is a block diagram of a sequential circuit using the dynamic PLA of this embodiment, and FIG. 5 is a conventional circuit diagram. FIG. 2 is a block diagram of an example of a dynamic PLA. 1...AND logic matrix, 2...Input latch circuit, 3, 6...Delay circuit, 4, 41.42...Clock driver, 5...OR logic matrix, 7...
Output latch circuit, 8... PLA input terminal, 9...
Product term line, 10... Output terminal of PLA, 19... Output line, 20... Feedback line.

Claims (1)

[Claims] an input latch circuit that latches an input signal using a first clock; an AND logic matrix that receives the output from the input latch circuit; and an output of the first clock and a first delay circuit on the AND logic matrix. a first clock driver that generates a second clock;
The signal from the AND logic matrix is input to the second
a second clock driver that generates a third clock from the first clock and the output of a second delay circuit on the OR logic matrix; Said OR
1. A dynamic programmable logic array comprising: an output latch circuit that latches output from a logic matrix.