JPH07104851B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a reset function for initializing an internal state, and more particularly to a structure of a microprocessor having means capable of defining a function of an external terminal.

[Prior art and technology] Conventionally, a microprocessor is provided with a plurality of external terminals, and each terminal is used as an input or an output, or a signal generated inside the processor according to the usage purpose of a user. It was necessary to decide which of the signals to select and use. Therefore, the following method has been adopted. That is, the first method of writing data that defines the usage status to the status setting register inside the processor by a program, or the second method of providing an external terminal separately and defining the role of each terminal with a signal from this terminal,
Alternatively, hardware switching (for example, wiring switching) is performed by a third method or the like which is specified when the processor is designed.

[Problems to be solved by the invention]

 The above-mentioned conventional techniques have the following drawbacks.

In the first state defining register method, the program must be started to write an appropriate value to the register, and therefore the time for setting the value in the register must be set independently. Therefore, careful attention must be paid to the timing control.

The second method has a drawback that the number of terminals is increased because a terminal used for control is separately prepared.

In the third method, since the function is fixed by hardware, once it is decided, it cannot be changed, and there is a drawback that it lacks versatility. In particular, in a processor including a large-scale integrated circuit, it is necessary to define such a function during the manufacturing process, which has a drawback that manufacturing becomes complicated.

[Means for solving problems]

The microprocessor of the present invention has means for determining the function of the terminal according to the data input from the outside during the reset period.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The present embodiment discloses means for selecting either S5 or S6 as the signal output from the output terminal 7. In the embodiment, an NMOS transistor is used. Terminals 1, 2, 3, and 4 are external input terminals that receive data from the outside.In normal operation, data is input to these terminals from the outside and signals S1, S2, S3, S
Taken internally as 4 and propagated to the internal data bus. On the other hand, during the RESET period for initializing the internal state, the data input from the terminals 1 to 4 is stored in the state setting register (a circuit of two stages of inverters connected to each terminal), and the signals M1, M2, M3 are input. , Used as M4. The operation during this RESET period will be described in detail below.

This embodiment is a microprocessor that operates in a two-phase clock of a non-overlapping clock phi ₁ and phi ₂ as shown in the timing chart of FIG. 2, the period from the rise of phi ₂ to the rising of the next phi ₂ RESET A signal shall be generated. R
The ESET signal is sent by the NOR circuit 5 from the rise of φ ₂ to the next φ
_It goes high for half a clock before the rising edge of ₁ . If the data of the terminals 1 to 4 is input during this high level period, the data input to the register can be used as the signals of M1 to M4. Based on the values of M1 to M4, the gates of the transistors to which they are input are driven. In this embodiment, the signal line 6 becomes active only when all of M1 to M4 become high level. As a result, the internal signal S5 is selected and output from the terminal 7. On the other hand, when M1 to M4 are other than the above, the internal signal S6 is output.
Therefore, the output state of the output terminal 7 can be determined / changed according to the data input during the reset period.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which the complementary transistor circuit is described in positive logic.
Input terminals 1 and 2 are registers. In this configuration, the internal state is initialized by the active low signal (), and the data applied to the terminal 1 is set in the register 2 during the period (). If the value set in the register during this period is positive logic "0", ▲
▼ After the signal rises from low level to high level, terminal 1
Functions as an input terminal, and the signal input from the terminal 1 is transmitted internally as the signal 4. On the other hand, when "1" is set in the register, the terminal 1 functions as an output terminal and the internal signal 5 is output from the terminal 1.

Such terminal function switching can be applied to the setting of the data width of the input / output data, the switching of the input / output synchronous / asynchronous method, etc., and the present invention has the advantage that it can be defined during the reset period for initializing the internal state. There is.

〔The invention's effect〕

As described above, the present invention can determine the usage state of the terminals during the input period of the reset signal for initializing the internal state of the microprocessor, so that it does not require an extra terminal and is simple. The effect is that the function of the terminal can be specified. Moreover, it is possible to change the terminal function once determined, which has the effect of increasing versatility.

[Brief description of drawings]

FIG. 1 is an NMOS transistor circuit diagram showing a first embodiment of the present invention. 1,2,3,4 …… input terminal, 5 …… NOR circuit, 6 …… signal line,
7 ... Output terminal, 8 ... RESET signal, S1, S2, S3, S4, S5, S
6, S7, M1, M2, M3, M4 …… Internal signal. FIG. 2 is a timing chart when the RESET signal is input in FIG. 1, and FIG. 3 is a complementary transistor circuit diagram showing a second embodiment of the present invention. 1 …… input terminal, 2 …… register, 3 …… ▲
▼ Signal, 4,5 …… Internal signal.

Claims (1)

[Claims] 1. A data processing device having at least one external terminal capable of switching a terminal function, wherein a means for temporarily storing data input from the external terminal during a reset period and a content of the stored data are provided. Circuit means for selecting the function of the external terminal capable of switching the terminal function is provided, and the function of the external terminal capable of switching the terminal function is defined by the input data from the external terminal input during the reset period. Characteristic data processing device.