JPS6139297A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten write time per bit and to realize high speed writing by dividing external input data lines into plural and distributing external input data into plural input buffer circuits with time division. CONSTITUTION:Two input buffer circuits 10 and 11 are installed in parallel between an input terminal 1 and an output side I/O bus 8 and switching circuits 12-16, which are respectively driven by clocks phi1 and phi2 from clock terminals 4 and 5, are installed at an input side and an output side. The input buffer circuits 10 and 11 are respectively activated by respective activating clocks phi' and phi'' from input terminals 2 and 3. The clocks phi1 and phi2 which are mutually dislocated [Figure (b) and (c)] and the activating clocks phi' and F'' [Figure (d) and (e)] are generated from a reference control clock [Figure (a)] and the data in correspondence to these clocks are outputted [Figure (f)].

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an input method for a semiconductor integrated circuit.

(Prior Art) Conventionally, in a semiconductor device, particularly in a semiconductor memory, an input circuit sequentially writes an input signal bit by bit.

As shown in FIG. 4, a system was adopted in which a signal from an external input bin 1 was supplied to an input back 7 circuit 10 through an input protection circuit. In this input method, only one input buffer circuit is usually placed on the IC-T.
This input balance circuit 10 is activated by an externally applied write enable (activation) clock φ', and an external input data signal is written therein.

In this conventional method, after manually inputting 11 pieces of input data as shown in the waveform diagram of Figure 5 TaL (b), the time Tc until the next input data can be input (Figure 5 (a)
) is determined by the activation signal clock K of the input buffer circuit (Fig. 5(b)), and when data is transferred at high speed to a memory circuit like a dynamic memory. This will require some cycle time.

However, in the input back 7 circuit 10 used in this conventional method, a precharge period is required during one cycle period, so in addition to the time for inputting and writing external input data, the precharge time is also required. 2. It has the disadvantage that it requires waiting time such as, and cannot operate at high speed.

(Objective of the Invention) An object of the invention is to provide a semiconductor integrated circuit which eliminates the above-mentioned drawbacks and allows data to be inputted from the outside at a high speed.

(Structure of the Invention) The semiconductor integrated circuit of the present invention divides input data from the outside into a plurality of input lines and receives them respectively, and uses a plurality of externally generated activation clock signals that are out of phase with each other. A plurality of input buffer circuits are configured to be sequentially activated and output respective input data.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 (a), (b), TC) are the first to
FIG. 3 is a circuit diagram showing the configuration of a third embodiment. 1st. The second embodiment is a case in which two input buffer circuits 10 and 11 are provided in parallel between the input terminal l and the output side I10 bus 8, and the (1st
Figures (a) and (b) show the clock φ1.5 from the clock terminal 4.5. Switching circuits 12 to 15 each driven by the φ weight are provided.

Note that the input back 7 circuits 10.11 are activated by respective activation clocks φ' and φ1 from the input terminals 2.3, respectively.

The operation of this circuit is illustrated by the waveform diagrams in FIGS. 2(a)-(f). In this waveform diagram, the clocks φ1. φ (Fig. 2 (b), (c)) and activation clocks φ', φN (Fig. 2 (d), (e)
l) is generated from the reference control clock (FIG. 2(a)).

Data corresponding to these clocks is output (FIG. 2(f)).

In FIG. 1(a), switching circuits 12 to 15 are provided on the input side and output side of an input buffer circuit 10.11. In this case, the input signal from the data input line is connected to the switching circuit φ1. φ2 (Fig. 2 1b), (C)
) are switched in the switching circuits 12 to 15, and are sequentially connected to each of the 7 human-powered buffer circuits 10 and 11 at different timings.At this time, the input backup circuit w110.11 is activated at the same cycle time as these switching signals. It is assumed that the timing is set with a predetermined phase shift so that the

FIG. 1(b) shows the input buffer circuit 10.11 with the input data side switching circuit 12.14 removed. In other words, it is a circuit that integrates an input-side switching circuit, an input cover, and a fa circuit.

In this case, external input data is sequentially input to each person's cover and 77 circuits 10.11, but each person's power buffer circuit 1
Timing φ' to activate 0.11.

In order to activate the primary input cover 77 circuit using φ', the switching circuit 12.14 on the input side of each human-powered buffer 7 circuit 10.11 can be removed. In this case, since the I10 bus 8 is shared, the output section of the input cover and the extension circuit 10.
．． 15 is required.

FIG. 1C shows a circuit that performs writing using only the activation signal of the input puff 7 circuit 10.11.

In this case, external input data is supplied to all input buffers, but only one of the input back 7 circuits IO or I/ill is activated by the activation signals φ' and φ' of the input buffer circuits 10 and 11. , is a circuit that performs a write operation. In this case, each of the input buffer 7 circuits 10.11 has the I10 path 8.9 separated and connected in advance, and the memory cell to be written is determined, so the switching on the output side of the input buffer 7 circuit 10.11 is The circuit becomes unnecessary.

FIG. 3 is a circuit diagram of a specific example in the case of FIG. 1(C).

In this manual buffer circuit, a precharge clock is first input and node A is charged. Next, when the activation signal φ' or φ' of the input buffer circuit is input, node B is charged.

When external data is input here, a comparison with the data reference input is performed and the output l1O-1 (or -2)
K high level and low level data are written. In the case of this input buffer circuit, since the input data is input to the gate of the transistor, the input data will not be output to the I10 bus unless the activation signal φ' or φ' of the human buffer 7 circuit is input. do not have.

(Effects of the Invention) As explained above, according to the present invention, by dividing the external input data line into a plurality of lines and distributing the external input data to a plurality of input covers and 77 circuits in a time-sharing manner, one bit can be processed. Since the IT input time can be shortened, high-speed writing can be achieved.

In addition, the timing clock for activating the input cover and NOR circuits requires a longer tickle time than conventional circuits.
Timing design of the input cover circuit becomes easy.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) show the first embodiment of the present invention. A circuit diagram showing the input circuit on the second and third side, FIG. 2 (a) to If) are operation waveform diagrams of FIG. 1 (a) to (C),
Fig. 3 is a circuit configuration diagram of a specific example of Fig. 1(C), Fig. 4 is a block diagram of a conventional data input circuit, Fig. 5(a),
tb) is an operating waveform diagram of FIG. 4. In the field, 1...Data input terminal, 2, 3...Clock φ'. φ1 input terminal, 4.5...Clock φ1. φ2
Input terminal, 8.9...I10 bus, 10.11
...Input buffer circuit, 12 to 15...
・It is a switching circuit. □t $Z Figure 3

Claims (1)

[Claims] A plurality of lines that divide external input data into a plurality of input lines, receive each input line, and output each input data by being sequentially activated by a plurality of externally generated activation clock signals whose phases are shifted from each other. A semiconductor integrated circuit that includes input buffer circuits.