JPH07295513A - Control circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To control the liquid crystal display device corresponding to a decided picture display mode by providing a circuit which decides the picture display mode of a video source between the video source and a liquid crystal control circuit. CONSTITUTION:The picture display mode decision circuit 11 which decides the picture display mode of the video source 1 is provided between the video source 1 and liquid crystal control circuit 2. This picture display mode decision circuit 11 consists of an oscillation circuit 3, a counter circuit 4, decoder circuits 5-7, and latch circuits 8-10. In this case, the decoder circuits 5-7 and latch circuits 8-10 as many as picture display modes of the video source 1 are required. When the video source or the picture display mode of the video source changes, the picture display mode decion circuit 11 can automatically decide the picture display mode and controls the liquid crystal display device corresponding to the picture display mode. Therefore, a display of a video source having plural picture display modes or a video source different in picture display mode can be made without performing complicated switch operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a liquid crystal display device, and more particularly to a control circuit for a liquid crystal display device capable of automatically discriminating one or more screen display modes of one or more video sources.

[0002]

2. Description of the Related Art Conventional control circuits for liquid crystal display devices do not have a function of automatically discriminating the screen display mode of a video source. When making it correspond, by manually switching the switch, the control corresponding to the specific screen display mode of the video source is performed.

[0003]

However, with this method, it is necessary to manually switch the switch each time the image source changes or the screen display mode of the image source changes, and the method has a specific screen display mode. As the number of types of image sources increases, or as the number of types of screen display modes specific to the image sources increases, the number of switches also increases, which makes the operation complicated.

[0004]

The control circuit for a liquid crystal display device according to the present invention has been invented in view of the above problems, and is characterized in that a single or a plurality of screen display modes are provided. The point is that a screen display mode discriminating circuit for discriminating the screen display mode of the image source is provided between the image source and the liquid crystal control circuit.

[0005]

With the above configuration, if the image source or the screen display mode of the image source changes, the screen display mode discrimination circuit can automatically discriminate the screen display mode, and the liquid crystal display device corresponding to the screen display mode. Can be controlled. Therefore, it is possible to display a video source having a plurality of screen display modes or a plurality of video sources having different screen display modes without a complicated switch operation.

[0006]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing an embodiment of a control circuit for a liquid crystal display device according to the present invention, in which 1 is a video source, 2 is a liquid crystal control circuit, and 11 is a screen display mode discrimination circuit.
The image source 1 is composed of, for example, a main body of a personal computer, and has a single or a plurality of screen display modes. The liquid crystal control circuit 2 is composed of, for example, a circuit for driving a liquid crystal display of a personal computer.

In the liquid crystal display control circuit of the present invention, a screen display mode discrimination circuit 11 for discriminating the screen display mode of the video source 1 is provided between the video source 1 and the liquid crystal control circuit 2. The screen display mode discrimination circuit 11 includes an oscillation circuit 3,
The counter circuit 4, the decoder circuits 5 to 7, and the latch circuits 8 to 10 are used. In this case, the decoder circuits 5 to 7 and the latch circuits 8 to 10 need to be at least as many as the screen display modes of the video source 1, and here the case where the video source 1 has three screen display modes is shown.

The oscillation circuit 3 is provided to generate a reference clock (CLK), and its frequency is the number of reference clocks (CLK) included in the low level period of the horizontal synchronizing signal (HS) of each screen display mode to be discriminated. So that they are different
Set to an appropriate value.

The counter circuit 4 counts the reference clock (CLK) generated by the oscillator circuit 3, and is configured to be reset at the trailing edge (HD) of the horizontal synchronizing signal (HS) sent from the video source 1. To do.

One decoder circuit 5 to 7 is provided for each screen display mode to be discriminated, and the horizontal synchronizing signal (HS) in the screen display mode to be discriminated by the output of the counter circuit 4 respectively.
It is configured such that it is at a high level within a range of several counts including the number of reference clocks (CLK) in the low level period.

The latch circuits 8 to 10 latch the outputs of the decoder circuits 5 to 7 at the rising edge (HU) of the horizontal synchronizing signal (HS) sent from the video source 1.

The operation of the control circuit for the liquid crystal display device is shown in FIG.
A description will be given based on the waveform chart shown in FIG. FIG. 2A shows a horizontal synchronization signal (H
S) and (b) are outputs of the counter circuit 4, (c) are reference clocks (CLK), (d), (e), and (f) are outputs of the decoder circuits 5, 6, and 7, (g), (g). h) and (i) are outputs of the latch circuits 8, 9, and 10.

The video source 1 includes, for example, a horizontal synchronizing signal (H
Since the low level period of S) is different, some screen display modes have the following number of reference clocks (CLK) in the low level period.

Screen display mode Number of low level period (μsec) reference clock (CLK) in low level period of horizontal synchronizing signal (HS) Screen display mode A 3.04 76.5 Screen display mode B 6.36 160.1 screen Display mode C 3.81 95.9 Here, the oscillation circuit 3 outputs 2 as the reference clock (CLK).
A case where a clock of 5.175 MHz is generated will be described. The decoder circuit 5 of FIG. 1 determines the screen display mode A, and when the output of the counter circuit 4 is 74 to 79, it becomes a high level output. The decoder circuit 6 determines the screen display mode B, and when the output of the counter circuit 5 is 158 to 163, it is set to a high level output. Further, the decoder circuit 7 determines the screen display mode C, and the output of the counter circuit 6 is 93
When ~ 98, high level output. However,
The output of the counter circuit 4 in which the decoder circuits 5, 6, and 7 set to high level output here are one example, and the reference clock in the low level period of the horizontal synchronization signal (HS) in each screen display mode is an example. The frequency of the reference clock (CLK) is not particularly limited as long as it includes the (CLK) number and that the high-level output periods of the decoder circuits 5, 6, and 7 do not overlap.

Video source 1 having screen display mode A, for example
, The low level period of the horizontal synchronizing signal (HS) is 3.04 μsec as shown in FIG. The counter circuit 4 uses the horizontal synchronizing signal (H
S) is reset at the falling edge (HD) of the reference clock (C) from 0 when the horizontal synchronizing signal (HS) falls.
LK) starts counting. Decoder circuits 5, 6, 7
As shown in FIGS. 2D, 2E, and 2F, the count values of the counter circuit 4 are 74 to 79 and 158, respectively.
A high level output is provided at 163 and 93 to 98. As shown in FIGS. 2 (g), 2 (h) and 2 (i), the latch circuits 8, 9 and 10 rise the horizontal synchronizing signal (HS) (HU).
Then, the outputs of the decoder circuits 5, 6 and 7 are respectively latched.

In the case of the video source 1 having the screen display mode A, as described above, the low level period of the horizontal synchronizing signal, that is, the period from the falling edge (HD) to the rising edge (HU) is 3.04 μsec, which is 25.175 MHz. Since the number of reference clocks (CLK) is 76.5, the rising edge (HU) of the horizontal synchronizing signal (HS) comes when the output of the decoder circuit 5 is in the high level state. Therefore, of the latch circuits 8, 9 and 10, only the latch circuit 8 latches the high level and the latch circuits 9 and 10 latch the low level.

Similarly, when the video source 1 in the screen display mode B is connected, the low level period of the horizontal synchronizing signal (HS) is 6.36 μsec, and the number of reference clocks (CLK) of 25.175 MHz is 160. Since it is 1, the rising edge (HU) of the horizontal synchronizing signal (HS) is
Of the latch circuit 9 is high when the output of
Latches the high level, and the latch circuits 8 and 10 latch the low level.

Exactly the same, the image source 1 in the screen display mode C
, The low-level period of the horizontal sync signal (HS) is 3.81 μsec and 25.175 MHz.
Since the number of reference clocks (CLK) is 95.9, the rising edge (HU) of the horizontal synchronizing signal (HS) is when the output of the decoder circuit 7 is high level, and therefore only the latch circuit 10 latches the high level. , Latch circuits 8 and 9
Latches low level.

The outputs of the latch circuits 8, 9 and 10 are input to the liquid crystal control circuit 2. For example, if only the latch circuit 8 is at a high level, it can be discriminated as the screen display mode A, and the control can be carried out accordingly. Similarly, if only the latch circuit 9 or the latch circuit 10 is at the high level, it can be discriminated as the screen display mode B or the screen display mode C, respectively.

In the present embodiment, an example of discriminating three screen display modes is shown. However, if the low level period of the horizontal synchronizing signal in each screen display mode is different, the frequency of the reference clock is set appropriately and the decoder circuit is used. By providing a considerable number of latch circuits, it is possible to determine more screen display modes.

[0021]

As described above, according to the control circuit for the liquid crystal display device of the present invention, the screen display of the video source is provided between the video source having one or a plurality of screen display modes and the liquid crystal control circuit. Since the screen display mode discrimination circuit for discriminating the mode is provided, if the screen display mode of the video source or the video source changes, the screen display mode can be automatically discriminated, and the liquid crystal display device compatible with the screen display mode can be discriminated. The liquid crystal display device can be controlled, and the liquid crystal display device can display various image sources without a complicated switch operation.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a control circuit for a liquid crystal display device according to the present invention.

FIG. 2 is a waveform diagram of signals in a liquid crystal display control circuit according to the present invention.

[Explanation of symbols]

1 ... Image source, 2 ... Liquid crystal control circuit, 3 ... Oscillation circuit, 4 ... Counter circuit, 5, 6, 7 ... Decoder circuit, 8, 9, 10 ... Latch circuit , 11 ... Screen display mode discrimination circuit

Claims (3)

[Claims] 1. A control circuit for a liquid crystal display device, comprising a screen display mode discriminating circuit for discriminating a screen display mode of the video source between a liquid crystal control circuit and a video source having one or a plurality of screen display modes. . 2. The screen display mode discrimination circuit, an oscillation circuit for generating a reference clock, a counter circuit for starting the counting of the reference clock from the fall of a horizontal synchronizing signal sent from the video source, and the counter circuit. And a latch circuit for latching the output of the decoder circuit at the rising edge of the horizontal synchronizing signal, and a decoder circuit for setting the data to a high level within the range of several counts including the reference clock number in the low level period of the horizontal synchronizing signal. The control circuit for a liquid crystal display device according to claim 1, wherein the control circuit comprises: 3. The control circuit for a liquid crystal display device according to claim 2, wherein there are a plurality of the latch circuits and the same number as the decoder circuits.