KR0182020B1 - Vertical synchronizing signal decision circuit - Google Patents

Abstract

The present invention relates to a vertical synchronization signal discrimination circuit, which is designed to receive a frequency of a color burst signal as a clock input, receive a vertical synchronization signal, and generate a reset signal at a time point at which the input clock is half-cycled. A synchronization signal for discriminating each video graphic mode according to the vertical synchronization signal by counting a clock for one period of the vertical synchronization signal inputted from that point in time when the reset signal is generated through the reset signal generation means and the reset signal generation means; It is composed of signal discrimination means, and it is possible to discriminate each video graphic mode to be input, and to control the synchronous signal processing circuit according to the discriminated mode to enable automatic adjustment according to each mode, and to use voltage by using digital counter. It operates stably even when the temperature and temperature fluctuate. Chapter is related to a vertical synchronizing signal determination circuit to reduce the overall board size.

Description

Vertical sync signal discrimination circuit

1 is a block diagram to which a conventional vertical synchronization signal discrimination circuit is applied.

2 is a block diagram to which a vertical synchronization signal discrimination circuit according to an embodiment of the present invention is applied.

3 is a detailed circuit diagram of a vertical synchronization signal determination circuit according to an embodiment of the present invention.

4 is a timing diagram of a reset signal generator in a vertical synchronization signal discrimination circuit according to an embodiment of the present invention.

The present invention relates to a vertical synchronizing signal discrimination circuit, and more specifically, it is possible to determine each video graphic mode input using a digital counter and to control the synchronizing signal processing circuit according to the determined mode. The present invention relates to a vertical synchronizing signal discrimination circuit which enables automatic adjustment and operates stably even when the voltage and the temperature fluctuate.

Personal computer monitors, color televisions, etc., are currently used for channel search and white-noise removal depending on the presence or absence of input signals. -It is designed to perform the On-Screen function (the function of displaying a specific color such as Blue or Green on the screen when there is no input signal).

Therefore, monitors, color televisions, and the like of personal computers have used external application circuits for determining the presence or absence of vertical synchronization signals to perform the above functions.

Hereinafter, a conventional vertical synchronization signal determination circuit will be described with reference to the accompanying drawings.

1 is a block diagram to which a conventional vertical synchronization signal discrimination circuit is applied.

As shown in FIG. 1, the conventional vertical synchronization signal discrimination circuit is configured to determine the polarity of the synchronization signal by charging and discharging the signal during a duty cycle of the signal when the vertical synchronization signal is input. A synchronization signal polarity discrimination and positive conversion circuit 1 for converting the polarity of the synchronization signal into positive polarity and outputting it; It consists of a low pass filter (2) for judging the presence or absence of the vertical synchronization signal through the positive signal and the positive signal output from the positive signal conversion circuit 1, and instead of the low pass filter (2) If micom is used, it is configured to perform the same function.

The conventional vertical synchronizing signal determination circuit configured as described above receives a signal synthesized from a synchronizing signal and a fly back signal from the synchronizing signal processing circuit, and sends the input signal to the microcomputer to 'high' or In case of low price without microcomputer, low pass signal can be used to determine whether the synchronization signal is input by using low pass filter to obtain high or low signal. .

However, in the conventional vertical synchronizing signal determination circuit, it is inconvenient to externally adjust the screen adjustment and the synchronizing signal output frequency of the monitor according to each mode.

In addition, since it is configured outside of an integrated circuit, that is, a dedicated board for synchronizing signals is manufactured and used in a chassis application, the cost of manufacturing and productivity are reduced, and the size of the entire board is reduced. There is a problem that becomes large.

In particular, from a technical point of view, as the synchronization signal is determined by an analog method, there is a problem that the determination of the synchronization signal is inaccurate and difficult to control due to changes in the surrounding environment, for example, voltage and temperature variations.

Accordingly, an object of the present invention is to solve the conventional problems as described above, and by using a digital counter, it is possible to determine each video graphic mode input and to control the synchronization signal processing circuit according to the determined mode. It is to provide a vertical synchronization signal discrimination circuit designed to enable automatic adjustment according to modes, to operate stably against voltage and temperature variations, and to be designed inside the integrated circuit to reduce the overall board size.

The configuration of the present invention for achieving the above object, to receive the frequency of the color burst signal (Color Burst Signal) as a clock input and to receive a vertical synchronization signal, to generate a reset signal at a time point of half cycle of the input clock Designed reset signal generating means; When the reset signal is generated through the reset signal generating means, a synchronization signal discrimination means for discriminating each video graphic mode according to the vertical synchronization signal is counted by counting a clock for one period of the vertical synchronization signal inputted from that point in time.

The synchronizing signal discriminating means may include: counting means for receiving a vertical synchronizing signal missing detection signal as a clock input and counting an input clock for discriminating whether there is a synchronizing signal input and a frequency for each video mode; Latch means for latching a value counted by said counting means and outputting it to an output terminal; First delay means for receiving a vertical synchronization signal input delay signal as a clock input and performing a delay function so as to receive a new vertical synchronization signal after delaying a predetermined time when the vertical synchronization signal is not input and newly inputted; And a second delay means for receiving a vertical synchronization signal no input delay signal as a clock input and determining whether or not to input the vertical synchronization signal by delaying a predetermined time when the vertical synchronization signal is not input.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention in detail.

2 is a block diagram to which the vertical synchronizing signal discrimination circuit according to an exemplary embodiment of the present invention is applied, and FIG. 3 is a detailed circuit diagram of the vertical synchronizing signal discriminating circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the configuration of the vertical synchronization signal discrimination circuit according to the embodiment of the present invention receives a frequency (3.58 MHz) of a color burst signal as a clock input and receives a vertical synchronization signal. A reset signal generation circuit 10 designed to receive the input signal and generate the reset signal at a time point of about half an cycle (about 120 nsec) of the input clock; When the reset signal is generated through the reset signal generation circuit 10, the counter circuit 20 for determining each video graphics mode according to the vertical synchronization signal by counting a clock for one period of the vertical synchronization signal inputted from that point in time. Consists of

As shown in FIG. 3, the configuration of the reset signal generation circuit 10 includes an AND gate that logically multiplies the vertical synchronization signal VSYNC and the reset signal RSTB generated at power-on. (AND0); The color burst signal having a frequency of 3.58 MHz and the phase inverted color burst signal through the inverter INV0 are respectively received at the clock input CK, and the 'high' level logic signal VDD is respectively received. A de-flip (DFR_0, DFR_1) which receives an input D, receives an output signal of the AND gate AND0 as a reset input RB, and outputs a data input signal in synchronization with the clock signal; EX-NOR gate (ENOR0) for generating a reset signal (Reset_Pulse1) when the output terminal (QQ) of the flip-flop (DFR_0, DFR_1) is exclusive-negative-OR and generates a half cycle (about 120 nsec) of the input clock Consists of

The counter circuit 20 includes a counter 21 for receiving a vertical synchronization signal loss detection signal Q13 as a clock input and counting a clock input for discriminating the presence or absence of a synchronization signal and a frequency for each video mode. Wow; A latch unit 22 for latching a value counted by the counter unit 21 and inserting it into an output terminal; A first delay that receives the vertical synchronization signal input delay signal Q16 as a clock input and performs a delay function so that a new vertical synchronization signal can be input after delaying a predetermined time when the vertical synchronization signal is not input and newly inputted. Section 23; The second delay unit 24 receives the vertical synchronization signal no input delay signal Q20 as a club input and delays a predetermined time when the vertical synchronization signal is not input to determine whether or not the vertical synchronization signal is input. consist of.

The counter unit 21 includes a NAND gate NAND0 that performs an AND logic on the output signal of the EX-NOR gate ENOR0 and the reset signal RSTB; An inverter INV1 for inverting an output signal of the NAND gate NAND0; A 4-bit counter CNT4R_0 which receives the output signal of the inverter INV1 as a reset terminal RB input and counts a signal input to the clock terminal CLK; An inverter INV2 for inverting the output terminal Q4 signal of the 4-bit counter CNT4R_0; NAND which negatively multiplies the output signal of the inverter INV2 and the vertical synchronization signal missing detection signal (frequency: 3.58Mhz / 8192, period: 2.29ms) to a clock terminal CLK of the 4-bit counter CNT4R_0. A gate NAND1; It is a structure connected in series with the output terminal Q4 of the 4-bit counter CNT4R_0, and receives the output terminal QQ signal of the front end as the data input D and receives the output signal of the inverter INV1, respectively. A de-flop that receives a set input (RB) and performs a counting function according to a clock signal inputted by receiving the vertical synchronization signal missing detection signal (frequency: 3.58Mhz / 8192, period: 2.29ms) as a clock input (CK) DFR_2 to DFR_7).

The first delay unit 23 includes an AND gate AND1 for performing an AND operation on the inverted output terminal QB signal of the de flip-flop DFR_6 and the reset signal RSTB; An OR gate OR0 for ORing the output signal of the AND gate AND1 and the test vector enable terminal TE signal; The output signal of the OR gate OR0 is received as a reset input RB and the frequency signal of 3.58 MHz is received as a test vector clock terminal TCK input, and a test vector enable terminal TE and a test vector data terminal ( TD) and the clock terminal CLK respectively receive the enable signal, the data and the clock signal, and select the clock terminal CLK and the test vector clock terminal TCK according to the input test vector enable terminal TE signal. And a 4-bit counter CNT4_0 for selecting the test vector data terminal TD and counting the signal of the selected clock terminal. A NAND gate (NAND2) that performs negative AND on the output terminals (Q4, Q3) signals of the 4-bit counter (CNT4_0); AND for outputting the output signal of the NAND gate NAND2 and the vertical synchronization signal input delay signal (frequency: 3.58 MHz / 65536, period: 18.3 ms) to the clock terminal CLK of the 4-bit counter CNT4_0. A gate AND2; The AND gate AND3 performs an AND operation on the output signal of the NAND gate NAND2 and the reset signal RSTB.

The latch unit 22 is configured to receive the output terminal QQ signal of the de-flop flop DFR_7 as a clock input CK, and receive a logic signal VDD having a 'high' level as a data input D. The 3.58 MHz frequency signal is received as a test vector clock terminal (TCK) input, and an enable signal and a data signal are input to a test vector enable terminal (TE) and a test vector data terminal (TD), respectively. The clock terminal CK, the test vector clock terminal TCK, the data terminal D, and the test vector data terminal TD are selected according to the enable terminal TE signal, and the data terminal selected by the selected clock terminal signal. A latch (TSN_0) for latching a signal inputted into; An OR gate OR2 for ORing the enable signal input to the test vector enable terminal TE and the output signal of the AND gate AND3; The data output terminal DX and the clock output terminal CKO of the latch TSN_0 are input to the data input terminal D and the clock input terminal CK, respectively, and the output signals of the OR gate OR2 are reset. It is composed of a de-flop (DFR_8) which is input to the input terminal (RB), and outputs the vertical synchronization signal determination signal (VSUS1).

The configuration of the second delay unit 24 includes an inverted signal of the signal input to the test vector data terminal TD of the latch TSN_0 by the inverter INV3 and a vertical synchronization signal no input delay signal (frequency: An AND gate AND4 that ANDs 3.58 MHz / 1048576, period: 293.6 ms); An AND gate AND5 for ANDing the output terminal QQ signal of the de flip-flop DFR_8 and the reset signal RSTB; An OR gate OR1 for ORing the output signal of the AND gate AND5 and the enable signal input to the test vector enable terminal TE; The output signal of the OR gate OR1 is received as a reset terminal RB, the output signal of the AND gate AND4 is received as a clock terminal CK, and the self inverting output terminal QB signal is received as a data terminal D. ) A de-flop (DFR_9) received as an input; The 4-bit counter CNT4_0 receives the output signal of the OR gate OR1 as the reset terminal RB input and receives the inverted output terminal QB signal of the de-flop flop DFR_9 as the clock terminal CLK input. Receives the output terminal Q4 signal from the test vector data terminal (TD) input, receives the 3.58 MHz frequency signal from the test vector clock terminal (TCK) input, and inputs the enable signal to the test vector enable terminal (TE). Selects a clock terminal CLK, a test vector clock terminal TCK and a test vector data terminal TD according to the input test vector enable terminal TE signal, and counts a signal of the selected clock terminal. It consists of a 4-bit counter (CNT4_1).

The operation of the vertical synchronization signal discrimination circuit according to the embodiment of the present invention made as described above is as follows.

The vertical synchronizing signal determination circuit according to an embodiment of the present invention can accurately and stably determine each video graphic mode input by using a clock having a frequency (3.58 MHz) of a color burst signal and a digital counter circuit 20. It was.

The vertical synchronizing signal determination circuit counts a clock for one period of the vertical synchronizing signal and firstly determines whether the vertical synchronizing signal is present. That is, the reset signal generation circuit 10 generates a reset signal Reset_Pulse1 at a time point at which half an interval (about 120 nsec) of the input clock is input, and the counter circuit 20 generates the reset signal until the next vertical synchronization signal is input. Enable counting A timing diagram of the process is shown in FIG.

Next, Table 1 shows the frequencies of the most commonly used video graphics modes.

The vertical synchronizing signal discrimination circuit according to an embodiment of the present invention is designed on the basis of the Display Power Management Signaling (DPMS) proposal of the Video Electronics Standard Association (VESA), and can be used as a synchronizing signal determining circuit in a television or a monitor. . In general, in the VESA DPMS mode, it is determined that there is a synchronization signal input when the frequency of the vertical synchronization signal is 40 Hz or more, and that there is no synchronization signal input when it is less than 10 Hz.

However, in the vertical synchronizing signal discrimination circuit according to the embodiment of the present invention, it is determined that there is a synchronizing signal input when the vertical synchronizing signal is 35.4 Hz or more, and when there is less than 31.4 Hz, it is determined that there is no synchronizing signal input.

In the detailed circuit diagram of the counter circuit 20 shown in FIG. 3, the 4-bit counter CNT4_0 may receive a new vertical sync signal after delaying about 120 msec when a new vertical input signal is not input. It is a counter to perform delay function.

Another counter CNT4_1 is about 4.69 sec (vertical sync signal no input delay time (293.6 msec) x counter output 16 when the vertical sync signal input is less than 31.4 Hz, that is, when the vertical sync signal is not input. Counter to delay by)). When the vertical synchronization signal input during this time (4.69 sec) is less than 31.4 Hz, it is determined that the vertical synchronization signal is not input.

After the above operation, using the comparison means such as a comparator at the output terminal of the counter circuit 20 to determine the frequency of each video graphics mode to determine each video graphics mode input and the synchronization signal according to the determined mode Allows control of the processing circuit.

Therefore, the effect of the vertical synchronizing signal discrimination circuit according to the embodiment of the present invention operating as described above is that each video graphic mode to be input can be discriminated and the synchronizing signal processing circuit can be controlled according to the discriminated mode. It enables automatic adjustment according to the mode, and it uses digital counters to operate stably against voltage and temperature fluctuations, and is integrated inside the integrated circuit to reduce the overall board size.

Claims (6)

A reset signal generating means designed to receive a frequency of a color burst signal as a clock input and to receive a vertical synchronizing signal and to generate a reset signal at a time point that is not half a period synchronized with the input clock; ; Counting means for receiving a vertical synchronization signal defect detection signal as a clock input and counting an input clock to determine whether there is a synchronization signal input and a frequency for each video mode; Latch means for latching a value counted through the counting means and outputting the counted value to an output terminal; First delay means for receiving a vertical synchronization signal input delay signal as a clock input and performing a delay function so as to receive a new vertical synchronization signal after delaying a predetermined time when the vertical synchronization signal is not input and newly inputted; And a second delay means for receiving a vertical synchronization signal no input delay signal as a clock input and delaying a predetermined time when the vertical synchronization signal is not input to determine whether or not the vertical synchronization signal is inputted. Vertical synchronizing signal discrimination circuit. 2. The apparatus of claim 1, wherein the reset signal generating means comprises: an AND gate AND0 for ANDing the vertical synchronizing signal VSYNC and the reset signal RSTB generated at power-on; The color burst signal having a frequency of 3.58 MHz and the phase inverted color burst signal through the inverter INV0 are respectively received at the clock input CK, and the 'high' level logic signal VDD is respectively received. A de-flip (DFR_0, DFR_1) for receiving an input (D) and receiving an output signal of the AND gate (AND0) as a reset input (RB), respectively, and outputting a data input signal in synchronization with the clock signal; EX-NOR gate (ENOR0) for generating a reset signal (Reset_Pulse1) when the output terminal (QQ) of the flip-flop (DFR_0, DFR_1) is exclusive-negative-OR and generates a half cycle (about 120 nsec) of the input clock Vertical synchronizing signal determination circuit comprising a. 3. The apparatus of claim 1 or 2, wherein the counting means comprises: a NAND gate (NAND0) which performs an AND logic on the output signal of the EX-NOR gate (ENOR0) and the reset signal (RSTB); An inverter INV1 for inverting an output signal of the NAND gate NAND0; A 4-bit counter CNT4R_0 which receives the output signal of the inverter INV1 as a reset terminal RB input and counts a signal input to the clock terminal CLK; An inverter INV2 for inverting the output terminal Q4 signal of the 4-bit counter CNT4R_0; NAND which negatively multiplies the output signal of the inverter INV2 and the vertical synchronization signal missing detection signal (frequency: 3.58 MHz / 8192, period: 2.29 ms) and outputs the result to the clock terminal CLK of the 4-bit counter CNT4R_0. A gate NAND1; It is a structure connected in series with the output terminal Q4 of the 4-bit counter CNT4R_0, and receives the output terminal QQ signal of the front end as the data input D and receives the output signal of the inverter INV1, respectively. A de-flop that receives a set input (RB) and receives a count detection signal (frequency: 3.58 MHz / 8192, period: 2.29 ms) as a clock input (CK) and performs a counting function according to an input clock signal ( And DFR_2 to DFR_7). 4. The apparatus of claim 1 or 3, wherein the first delay means comprises: an AND gate AND1 for ANDing the inverted output terminal QB signal of the de flip-flop DFR_6 and the reset signal RSTB; An OR gate OR0 for ORing the output signal of the AND gate AND1 and the test vector enable terminal TE signal; The output signal of the OR gate OR0 is received as a reset input RB and the frequency signal of 3.58 MHz is received as a test vector clock terminal TCK input, and a test vector enable terminal TE and a test vector data terminal ( TD) and the clock terminal CLK respectively receive the enable signal, the data and the clock signal, and select the clock terminal CLK and the test vector clock terminal TCK according to the input test vector enable terminal TE signal. And a 4-bit counter CNT4_0 for selecting the test vector data terminal TD and counting the signal of the selected clock terminal. A NAND gate (NAND2) that performs negative AND on the output terminal (Q4, Q3) signals of the 4-bit counter (CNT4_0); AND for outputting the output signal of the NAND gate NAND2 and the vertical synchronization signal input delay signal (frequency: 3.58 MHz / 65536, period: 18.3 ms) to the clock terminal CLK of the 4-bit counter CNT4_0. A gate AND2; And an AND gate (AND3) for ANDing the output signal of the NAND gate (NAND2) and the reset signal (RSTB). The logic circuit of claim 1, wherein the latch unit receives the output terminal QQ signal of the de-flop flop DFR_7 from a clock input CK, and receives a logic signal VDD having a 'high' level as a data input D. Receiving the 3.58 MHz frequency signal through a test vector clock terminal (TCK) input and receiving an enable signal and a data signal through a test vector enable terminal (TE) and a test vector data terminal (TD), respectively. The clock terminal CK, the test vector clock terminal TCK, the data terminal D, and the test vector data terminal TD are selected according to the enable terminal TE signal, and the data selected by the selected clock terminal signal is selected. A latch TSN_0 for latching a signal input to the terminal; An OR gate OR2 for ORing the enable signal input to the test vector enable terminal TE and the output signal of the AND gate AND3; The data output terminal DX and the clock output terminal CK0 of the latch TSN_0 are input to the data input terminal D and the clock input terminal CK, respectively, and the output signal of the OR gate OR2 is reset. And a flip-flop (DFR_8) which is inputted to an input terminal (RB) and outputs a vertical synchronization signal determination signal (VSUS1). The second delay means is an inverted signal of the signal input to the test vector data terminal TD of the latch TSN_0 by the inverter INV3 and a vertical synchronization signal no input delay signal (frequency). AND gate AND4, which ANDs: 3.58 MHz / 1048576, period: 293.6 ms; An AND gate AND5 for ANDing the output terminal QQ signal of the de flip-flop DFR_8 and the reset signal RSTB; An OR gate OR1 for ORing the output signal of the AND gate AND5 and the enable signal input to the test vector enable terminal TE; The output signal of the OR gate OR1 is received as a reset terminal RB, the output signal of the AND gate AND4 is received as a clock terminal CK, and the self inverting output terminal QB signal is received as a data terminal D. ) A de-flop (DFR_9) received as an input; The 4-bit counter CNT4_0 receives the output signal of the OR gate OR1 as the reset terminal RB input and receives the inverted output terminal QB signal of the de-flop flop DFR_9 as the clock terminal CLK input. Receives the output terminal Q4 signal from the test vector data terminal (TD) input, receives the 3.58 MHz frequency signal from the test vector clock terminal (TCK) input, and inputs the enable signal to the test vector enable terminal (TE). Selects a clock terminal CLK, a test vector clock terminal TCK and a test vector data terminal TD according to the input test vector enable terminal TE signal, and counts a signal of the selected clock terminal. A vertical synchronization signal discrimination circuit comprising a 4-bit counter (CNT4_1).