JPS63121365A - Character display control circuit - Google Patents

Abstract

PURPOSE:To reduce consumption power by providing an oscillation control circuit controlling the operation and stop of an oscillation circuit in correspondance with oscillation control data among instruction data. CONSTITUTION:The oscillation circuit 4 generates a dot clock signal DC which is synchronized with a horizontal synchronizing signal H among video signals, and a timing generation circuit 5 generates a timing signal T from the signal DC, a vertical synchronizing signal V among the video signals, display position designation data among a control register 2 and the like. Dot data which corresponds with the timing of the signal T is read from a ROM6, and a display signal VS which is to be overlapped with the video signals is outputted from a display output control circuit 7. An output signal from an instruction decoder 1 controls the oscillation control circuit 8 which stores oscillation control data among instruction data D, and controls the operation and stop of the circuit 4. Thus, consumption power is reduced and character display can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a character display control circuit, and particularly relates to a character display control circuit used to input characters on the screen of a television set.

[Conventional technology]

Such character display control circuit NI is used to display channel numbers, volume, timer setting data, etc. on the screen of television receivers, and is used in video cameras and video recorders to display date, title, etc. on video signals. Used for overlapping recording.

FIG. 2 is a block diagram showing an example of such a conventional character display control circuit.

The instruction decoder 1 decodes the instruction data D and outputs a signal indicating the type of instruction. The control register 2 is controlled by the output signal of the instruction decoder 1 and stores each deviation control data in the instruction data D. The control data includes display position designation data, character color designation data, background operation designation data, background color designation data, and the like. The video RAM 3 is controlled by the output signal of the instruction decoder 1 and stores the display sentence hand ratio data in the instruction data D. The display character specification data specifies the characters to be displayed in each display frame in a predetermined row/column format.

The oscillation circuit 9 generates a dot clock signal DC synchronized with the horizontal synchronizing signal H in the video signal for character display. The timing generation circuit 5 generates a timing signal T-i from the dot clock signal DC, the vertical synchronization signal V in the video signal, and the display position designation data in the control register 2.

The character ROM 6 stores dot data DD't- for forming each of various characters.

At the timing of the timing signal TO, display character designation data t- is successively read out from the video RAM 3, and dot data Di)i is read out from the character ROM 6 using the read display character designation data as an address. The display output control circuit 7 outputs the read dot data DD″f:.

It is operated based on character color designation data, background operation designation data, background color designation data, etc. in the control register 2 and the timing signal T, and is output as a display signal vS.

The display signal vS is superimposed on the video signal and displays a specified group of characters at a specified position on the screen with a specified color and background.

The conventional example shown in FIG. 2 is usually composed of a CMO 8 and consumes almost no power except for the oscillation circuit 9 during a period when characters are not displayed. However, the oscillation circuit 9 is constantly operating, and its oscillation frequency ranges from several MHz to several MHz.
z, so it constantly consumes a non-negligible amount of power. Even if the power source is turned on, the period during which characters are displayed is very short, and the power consumption of the conventional character display control circuit is mostly due to the power consumption of the oscillation circuit.

[Problem that the invention seeks to solve]

As explained above, the conventional character display control [GL path has the drawback that the oscillation circuit is constantly operating and consumes power even during the period when no characters are displayed, resulting in large power consumption.

This drawback is particularly problematic when used in portable devices such as liquid crystal screen television sets and home video cameras.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above drawbacks and provide a character display control circuit with low power consumption.

[Means for solving problems]

The character light display control circuit of the present invention generates a dot clock signal by an excavation circuit synchronized with a video file number, and uses this dot clock signal, a vertical synchronization signal in the video signal, and display position designation data in the command data. A character display control circuit that generates a timing signal, reads dot data corresponding to display character designation data in the command data from a character ROM at the timing of the timing signal, and outputs it as a display signal to be superimposed on the video signal, The oscillation control circuit is configured to include an oscillation control circuit that controls operation and stop of the oscillation circuit in accordance with oscillation control data in the command data.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a character display control circuit of the present invention.

The embodiment shown in FIG. 1 includes an instruction decoder 1 which inputs instruction data D't manually, a control register 2/oscillation control circuit 8 into which the output signal of the instruction decoder 1 and instruction data D are input,
A video ROM 3 into which the output signal of the instruction decoder 1, instruction data D and timing signal T are input, and an oscillation control circuit 8
The output data of the control register 2, the dot clock signal DC and the vertical synchronization signal V are input, and the timing signal T1 & : Inputs the timing generation circuit 5 to output, the character ROM 6 which inputs the output data of the video RAM 3 and outputs the dot data DD=<, the output data of the control register 2/oscillation control circuit 8, the timing signal T, and the dot data DD. Display signal V
The display output control circuit 7 outputs S6.

The oscillation control circuit 8 is a register and stores the oscillation control data in the instruction data D in response to the output signal of the instruction decoder 1. The oscillation control data includes one operation, one
There are two states: 1 and 1 stop.

The oscillation circuit 4 is controlled by oscillation control data, and when the oscillation control data is in the "@operation" state, it oscillates like the oscillation circuit 9 in FIG. 2, and when the oscillation control data is in the "stop" state, the oscillation is completely stopped.

Since the oscillation control data is set on the output stage flip-flop 'kIJ' of the display output control circuit 7 in the 'stop' state, the display signal vS is not output at this time.

The embodiment shown in FIG. 1 has a configuration in which an oscillation control circuit 8 is added to the conventional example shown in FIG. 2, and the oscillation circuit 9 is replaced with an oscillation circuit 4. - At the beginning of the character display period, excavation control data in the state of "1 action" is input as command data D.

As a result, the oscillation circuit 4 generates the dot clock signal DC, and thereafter the embodiment shown in FIG. m1 outputs the required display signal vS in the same way as the conventional example shown in FIG. At the end of the character display period, oscillation control data in a stopped state is input as command data D, and as a result, the embodiment shown in FIG.
operation also stops.

If the correspondence between the control data stored in the control register 2 and the operation of the display output control circuit 7 guarantees that the display signal VS will not be output during the period in which no characters are displayed, display output control using oscillation control data is performed. It is not necessary to reset the output stage flip-flop of circuit 7.

〔Effect of the invention〕

As explained in detail above, the character display control circuit of the present invention has the effect of reducing power consumption because the oscillation control circuit stops the operation of the oscillation circuit during the period when no characters are displayed. Since the operation of the oscillation circuit is stopped, there is also the effect that the generation of spurious signals is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a character display control circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional character display control circuit. l...Instruction decoder, 2...Control register, 3...Video RAM, 4...Oscillation circuit, 5...Timing generation circuit , 6...
. . . Catactor k<ON, 7 . . . Display output control circuit, 8 . . . Oscillation control circuit. Kaya 2WJ

Claims (1)

[Claims] A dot clock signal is generated by an oscillation circuit synchronized with a horizontal synchronization signal in a video signal, and from this dot clock signal, a vertical synchronization signal in the video signal, and display position designation data in command data. A character display control circuit that generates a timing signal, reads dot data corresponding to display character designation data in the command data from a character ROM at the timing of the timing signal, and outputs it as a display signal to be superimposed on the video signal, A character display control circuit comprising an oscillation control circuit that controls operation and stop of the oscillation circuit in response to oscillation control data in the command data.