JPH0792934A - Storage circuit, address signal generating circuit and flat panel driving circuit - Google Patents

Abstract

PURPOSE:To allow element data read into storage elements to correspond to arbitrary number of lines of a panel even when a conventional external signal is used by converting the address signals of an incorporated storage circuit in a flat panel driving circuit incorporated with a storage circuit having storage elements corresponding to panel display elements. CONSTITUTION:Input clock 102 is divided by a dividing signal generating section 121 and a frequency divider 123. A dividing maximum value decided by an external reset signal 101 is held by a latch 129. A divided output 128 and a latch output 130 are compared by a signal comparator 131, a coincidence signal synthesis section 133 puts the output 128 into a reset condition and an address signal 134 is obtained. The address signal is used in the storage circuit which is incorporated in a flat panel driving circuit. The usage area of the storage circuit is varied or specified by only using the signal changing the address and two signals varying address frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The memory element of the present invention is a memory element for writing / reading data such as SRAM, DRAM, PRO.
Used for M, EPROM and EEPROM. The address signal generating circuit of the present invention is used for the operation of the memory element for reading and writing. The flat panel drive circuit of the present invention is used for a drive circuit connected to a data electrode of a flat panel of a liquid crystal panel.

[0002]

2. Description of the Related Art Hereinafter, a memory element for writing and reading will be abbreviated as a memory element. Below, the high level of the signal is "H",
The low level is indicated by "L". In order to make the logic easier to understand, the signal can be operated at "H" unless otherwise specified, and the switching of the count and the like will be described using the falling edge of the signal.

8 and 9 are a block diagram of a conventional memory circuit and a diagram showing signals around the memory circuit, respectively. The one that counts five input clocks is used as an example.

The input clock 102, which is the first external signal, and the external reset signal 101, which is the second external signal, are input to the storage element operation signal generation unit 103, which is necessary for reading and writing data in the storage element 104. Signal WR105, RD10
6. Create signals such as PC107. The WR105 signal is a signal used for writing data in the memory element 104. RD1
The 06 signal is a signal used for reading data from the storage element 104. The PC107 signal is a precharge signal required for switching between the WR105 signal and the RD106 signal. When the shaded data of the storage element input data 110 synchronized with the input clock 102 is transferred, the storage element input data 110 is transferred to the address including the address changing means and the address cycle changing means by the pulse indicated by the arrow of the WR105 signal. Address first stage signal 162-generated by signal generation circuit 161
1, address second stage signal 162-2, address third stage signal 162-
Both 3 are taken into the storage element 104 in the “L” part.
The address first stage signal 162-1 indicates the lowest address. After that, by the pulse shown by the arrow of the RD106 signal, the address first stage signal 162-1, the address second stage signal 162-2, and the address third stage signal 162-3 are all shown from the storage element 104 in the portion "L" in the shaded area. The data written in the storage element 104 is read. When the shaded portion of the storage element output data 163 is synchronized with the input clock 102 in the synchronizing unit 112, the data is output to the shaded portion of the output data 164. In this way, the output data 164 of the conventional memory circuit is output to the portion delayed by one cycle of the input clock 102 from the input portion. That is, b1, b2, b3, ... Of the storage element input data 110 are read to b1, b2, b3 ,.

10 and 11 are a block diagram of a conventional address signal generating circuit and a diagram showing signals around the address signal generating circuit, respectively. The one that counts five input clocks is used as an example. The input clock 102, which is the first external signal, is input to the synchronous or asynchronous frequency divider 171 which is frequency dividing means to divide the input clock 102. The frequency divider 171 is composed of a flip-flop with reset. By inputting the input clock 102 and the external reset signal 101, which is the second external signal, to the frequency divider reset signal generation unit 172, the frequency divider reset signal 1 necessary for resetting the frequency divider 171
Get 73. The frequency divider reset signal generation unit 172 generates a signal at the falling edge of the input clock 102 and logically synthesizes this signal with the external reset signal 101. The divided cycle reset signal 173 is input to the reset terminal of the frequency divider 171. An address signal 174 is obtained from the address signal generation circuit by these signals.

12 and 13 are a block diagram of a conventional flat panel drive circuit and a diagram showing signals around the flat panel drive circuit, respectively. The VSYNC142 signal is a vertical synchronizing signal of the flat panel 141. HSY
The NC143 signal is a horizontal synchronizing signal of the flat panel 141. Flat panel 1 to drive flat panel 141
It is necessary to apply a signal to the electrodes arranged vertically and horizontally at 41.
It is the flat panel data line drive circuit 181 and the common line drive circuit 145 that give a signal to this electrode. The conventional flat panel drive circuit described here corresponds to the data line drive circuit 181. The input pixel data 146, which is the panel display pixel data, serially includes pixel data for one horizontal period within one cycle of HSYNC143, and VSYNC.
142 Pixel data for one screen is serially transferred within one cycle. This serial pixel data is input to the serial / parallel conversion unit 182 and converted into parallel pixel data 183. The parallel pixel data 183 is converted by the panel drive signal conversion unit 184 into a panel drive signal 185 capable of driving the flat panel 141 and output. Input pixel data 1
The data input to the shaded portion of 46 is sent to the shaded portion of the parallel pixel data 183 and the shaded portion of the panel driving signal 185. Therefore, the panel drive signal 185 is output to a portion which is delayed by one cycle of the HSYNC 143 from the period when the serial input pixel data 146 is input.

[0007]

In order to improve the image quality of the flat panel and reduce the power consumption, it is necessary to incorporate a storage element in the flat panel drive circuit. However, the above-mentioned conventional flat panel drive circuit that simply incorporates the memory circuit that operates in the address signal generation circuit has the following problems. That is, in a flat panel drive circuit that uses a conventional address signal generation circuit and has a built-in memory element, the parallel-converted pixel data is output one horizontal sync signal period after the display serial pixel data is input, and this pixel data is output. When input to the storage element and output, the horizontal synchronization signal is further output with a delay of one cycle, and as a result, the serial pixel data is input, the horizontal synchronization signal is output two cycles, and then the pixel data is output. Normally, in the flat panel drive circuit, the serial pixel data is input, the horizontal synchronization signal is cycled, and then the pixel data is output. Therefore, it is not possible to match the other common line drive circuit that drives the flat panel. The data that should originally be displayed on the second line is displayed on the first line.
It will be displayed line by line. In order to avoid this, it is necessary to change the drive circuit for the common line of the flat panel or change the signal for controlling the flat panel drive circuit, which leads to an increase in cost.

In view of the above problems, therefore, by changing the output timing of the address signal generating circuit necessary for the operation of the memory circuit, a signal for changing the address even when the memory element is built in the network is provided. The use area of the storage circuit can be changed and specified only by two external signals that change the address cycle, and the peripheral circuit can be assembled as in the case where the storage element is not built in the circuit network. Of the control signals sent from the flat panel controller in the flat panel drive circuit that has a built-in storage element corresponding to the panel display pixel, the latch pulse and frame start signal can be used as the external signal without increasing the number of signal lines. The automatic use range of the built-in storage element area can be adjusted according to the display line. This is suitable for the requirement of narrowing the frame area in the flat panel. Further, by incorporating a memory element, various panel driving methods can be performed, so that it is possible to provide a flat panel that can improve image quality and reduce power consumption by using the same signal as an external signal.

[0009]

The memory circuit of the present invention has address signal generating means for generating an address signal from the address changing means and the address cycle varying means, and the same address change is made to the memory circuit by using this address signal generating means. It is characterized in that it has means for generating a data write address which differs by a fixed number of addresses from the data read address of the memory circuit within the period.

The address signal generating circuit of the present invention is used in the above-mentioned memory circuit and comprises means for converting the address changing means into a frequency dividing signal, signal dividing means for dividing the frequency dividing signal, and maximum A signal holding means for holding the frequency division value, a signal creating means for producing a reset signal of the signal holding means and a signal holding timing signal of the signal holding means, a value held in the holding means and an output signal from the frequency dividing means. It is characterized by comprising a signal comparing means for comparing and a signal converting means for converting an output signal from the frequency dividing means with a signal from the comparing means.

The flat panel drive circuit of the present invention incorporates the storage circuit of the present invention having a storage element corresponding to the pixel data of the entire area or a part of the area of the panel and writes / reads the pixel data to / from the storage element of the storage circuit. And then
Further, it is characterized in that it is converted into a signal used for driving the panel and outputted.

[0012]

According to the present invention, even when the memory circuit is incorporated in various circuit networks, the peripheral circuit can be configured in the same manner as when the memory circuit is not provided inside.

Further, in the address signal generating circuit used for the memory circuit, it is possible to cope with any number of memory elements and addresses with the same external signal as in the conventional case.

Further, by incorporating the above-mentioned memory element in the flat panel drive circuit, various panel drive methods are possible, and it is possible to improve the image quality of the panel and reduce the power consumption.

[0015]

EXAMPLES Hereinafter, a memory element for reading and writing will be abbreviated as a memory element. Hereinafter, the high level of the signal is indicated by "H" and the low level thereof is indicated by "L". In order to make the logic easier to understand, the signal can be operated at "H" unless otherwise specified, and the switching of the count and the like will be described using the falling edge of the signal.

1 and 2 are a circuit diagram of a memory circuit of the present invention and a diagram showing signals around the memory circuit, respectively. A signal WR105 necessary for inputting and reading the input clock 102, which is the first external signal, and the external reset signal 101, which is the second external signal, to the storage element operation signal generation unit 103, RD106, PC10
Create a 7th magnitude signal. The WR105 signal is a signal used for writing data in the memory element 104. The RD 106 signal is a signal used for reading data from the memory element 104. The PC107 signal is a precharge signal required for switching between the WR105 signal and the RD106 signal. An address signal generating circuit 108 including an input clock 102 and an external reset signal 101, including address changing means and address cycle changing means.
To enter. The address signal 109 is output from the address signal generation circuit 108 so that the switching of the address signal 109 output from the address signal generation circuit 108 comes immediately after the data writing to the storage element 104 is completed. Storage element input data 110 input in synchronization with the input clock 102
When the portion indicated by the slanted lines is transferred, the storage element input data 110 has the address first stage signal 109-1 and the address second stage signal 109-1 generated by the address signal generation circuit 108 by the pulse indicated by the arrow of the WR105 signal. Both 109-2 and the address third stage signal 109-3 are taken into the memory element in the "L" portion. After that, by the pulse shown by the arrow of the RD106 signal, the address first stage signal 109-1, the address second stage signal 109-2,
The address third-stage signal 109-3 is written in the storage element input data 110 previously input from the storage element selected by "L" in the storage element output data 111 in the hatched portion. Data is read. The storage element output data 111 is synchronized with the input clock 102 by the synchronization unit 112, and the data is output to the hatched portion of the output data 113. In this way, the output data 113 is output from the input portion during one period of the external reset signal 101, that is, during the same address period in the portion delayed by one address period. That is, b1, b2, b3, ... Of the input data 110 to the memory circuit of the present invention are read as b1, b2, b3 ,.

FIGS. 3, 4 and 5 are respectively a block diagram of the address signal generating circuit of the present invention, an address signal generating circuit diagram and a diagram showing signals around the address signal generating circuit. The one that counts five input clocks is used as an example. A frequency-dividing-signal creating unit that is a first converting unit that converts the input clock 102 that is a first external signal into a frequency-dividing signal.
At 121, it is converted into a count clock 122 using a delay or the like.
This count clock 122 is divided by a synchronous or asynchronous frequency divider 123 which is a frequency dividing means. The frequency divider 123 is composed of a flip-flop with reset 124. By inputting the input clock 102 and the external reset signal 101 to the frequency divider reset signal and latch signal generation unit 125 which is a signal generation means, the frequency divider reset signal 126 and the latch described later which are necessary for resetting the frequency divider. Obtain the signal 127. The frequency divider reset signal and latch signal creation unit 125 performs logical synthesis of the input clock 102 and the external reset signal 101.
The logically synthesized signal becomes the latch signal 127, and the signal created by the rising edge of the latch signal 127 becomes the frequency divider reset signal 126. The frequency divider reset signal 126 is input to the reset terminal of the frequency divider 123. With these signals, the frequency divider 123 outputs the frequency division first stage signal 128-1, the frequency division second stage signal 128-2, and the frequency division third stage signal 128-3. These signals 128-1, 128-2, 128-3 are input to the latch section 129 which is a signal holding means by the above-mentioned latch signal 127. As a result, the maximum count value counted by the frequency divider 123 is latched in the latch unit 129. In this case, the latched signals are the latch first stage signal 130-1 "H", the latch second stage signal 130-2 "L", and the latch third stage signal 130-3 "H".
Becomes Latch first stage signal 130-1, Latch second stage signal 130
-2, the latch third stage signal 130-3 is the frequency division first stage signal 1 respectively
28-1, the frequency division second stage signal 128-2, and the frequency division third stage signal 128-3 are latched. Signal comparator 13 which is a signal comparison means
1 is a comparison between the latched signals 130-1, 130-2, 130-3 and the frequency-divided signals 128-1, 128-2, 128-3 of the frequency divider 123, respectively, and the signal comparator output signal 132 is "H" at the portions where the signals match. To work. A signal synthesizing section which is a second signal converting means.
In 133, the signal comparator output signal 132 output from the signal comparator 131 and the frequency divider output signal 128-1, output from the frequency divider 123,
Logic synthesis is performed with each of the signals 128-2 and 128-3 to obtain an address first stage signal 134-1, an address second stage signal 134-2, and an address third stage signal 134-3. This address first stage signal 134
-1 is the frequency division first stage signal 128-1, the latch first stage signal 130-1,
This address second stage signal 134-2 is the frequency division second stage signal 128-2,
This address third stage signal 134 is added to the latch second stage signal 130-2.
-3 is the frequency division third stage signal 128-3, the latch third stage signal 130-3,
Corresponds to each.

FIGS. 6 and 7 are a block diagram of the flat panel drive circuit of the present invention and a diagram showing signals around the flat panel drive circuit, respectively. The VSYNC142 signal is a vertical synchronizing signal of the flat panel 141. The HSYNC143 signal is a horizontal synchronizing signal of the flat panel 141. In order to drive the flat panel 141, it is necessary to apply a signal to the electrodes arranged vertically and horizontally on the flat panel 141. It is the flat panel data line driving circuit 144 and the common line driving circuit 145 that give a signal to this electrode. The flat panel driving circuit of the present invention is a data line driving circuit 144.
Corresponding to. As the input pixel data 146 displayed on the panel, pixel data for one horizontal period is serially transferred within one cycle of HSYNC143, and pixel data for one screen is serially transferred within one cycle of VSYNC142. This input pixel data
Input pixel data 1 that was serial by inputting 146 to the serial / parallel conversion and storage element operation signal generation unit 147
WR105, RD106, PC10 required to convert 46 into parallel pixel data 148 for one horizontal period and to operate the storage element
7 signal and address signal 109 are generated. Address signal 109
Is output from the address signal generating circuit of the present invention. The parallel pixel data 148 is read into the memory circuit of the present invention. The hatched portion of the input pixel data 146 is converted into the hatched portion of the parallel pixel data 148 by serial / parallel conversion, and is written in the storage element by the pulse indicated by the arrow of the WR105 signal and by the pulse indicated by the arrow of the RD106 signal. Data is read from the storage element section 150 to the hatched portion of the storage element section output data 149. The synchronizing section 151 synchronizes the data with the HSYNC143 signal and outputs the data to the shaded portion of the post-synchronizing section data 152. The post-synchronization section data 152 is converted by the panel drive signal conversion section 153 into a panel drive signal 154 that is a signal capable of panel drive, and the data is output to the hatched portion. Therefore, the flat panel data is VS from the period when the serial input pixel data 146 is input.
It is output in a period delayed by one cycle of YNC142 and one cycle of HSYNC143.

[0019]

According to the memory circuit of the present invention, even when the memory circuit is added to various circuit networks, the peripheral circuit can be configured in the same manner as when the memory circuit does not exist inside. Therefore, the number of new peripheral circuits to be changed is small and the cost can be reduced.

The address signal generating circuit of the present invention is used for the operation of the above-mentioned storage element. However, the use area of the storage circuit is changed and specified only by a signal for changing the address and two external signals for changing the address cycle. Can be
An arbitrary number of storage elements and addresses can be handled with the same external signals as in the conventional case, and the circuit can be simplified.

Since the flat panel drive circuit of the present invention has a built-in memory element, it is possible to variously convert the signal output to the flat panel, which is the signal output from the flat panel drive circuit. For example, the image quality of a flat panel is improved by a driving method that selects several lines of the panel at the same time, and when a still image is displayed on the panel screen, the panel is driven by a signal from an internal storage circuit without using an external image signal. By the driving method for performing the above, the effect of reducing the power consumption of the flat panel can be obtained. Of the control signals sent from the flat panel controller, the latch pulse and frame start signal can be used as the external signal, and the automatic use range adjustment of the built-in storage element area according to the display line can be performed without increasing the number of signal lines. it can. This is suitable for the demand for narrowing the frame area of the flat panel.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory circuit of the present invention.

FIG. 2 is a diagram showing signals around a memory circuit of the present invention.

FIG. 3 is a configuration diagram of an address signal generation circuit of the present invention.

FIG. 4 is a circuit diagram of an address signal generation circuit of the present invention.

FIG. 5 is a diagram showing signals around an address signal generating circuit of the present invention.

FIG. 6 is a configuration diagram of a flat panel drive circuit of the present invention.

FIG. 7 is a diagram showing signals around a flat panel drive circuit of the present invention.

FIG. 8 is a configuration diagram of a conventional memory circuit.

FIG. 9 is a diagram showing signals around a conventional memory circuit.

FIG. 10 is a configuration diagram of a conventional address signal generation circuit.

FIG. 11 is a diagram showing signals around a conventional address signal generation circuit.

FIG. 12 is a configuration diagram of a conventional flat panel drive circuit.

FIG. 13 is a diagram showing signals around a conventional flat panel drive circuit.

[Explanation of symbols]

101-External reset signal 102-Input clock 103-Memory element operation signal creation unit 104-Memory element 105-WR 106・ RD 107 ・ ・ ・ PC 108 ・ ・ ・ Address signal generation circuit 109 ・ ・ ・ ・ ・ Address signal 110 ・ ・ ・ Memory element input data 111 ・ ・ ・ Memory element output data 112 ・ ・・ ・ ・ Synchronous unit 113 ・ ・ ・ ・ ・ Output data 121 ・ ・ ・ ・ ・ Dividing signal creation unit 122 ・ ・ ・ ・ ・ Count clock 123 ・ ・ ・ Divider 124 ・ ・ ・ With reset Flip-flop 125 ・ ・ ・ ・ ・ Divider reset signal and latch signal creation unit 126 ・ ・ ・ ・ ・ Divider reset signal 127 ・ ・ ・ Latch signal 128-1 ・ ・ ・ Dividing first stage signal 128- 2 ・ ・ ・ Divided second stage signal 128-3 ・ ・ ・ Divided third stage signal 129 ・ ・ ・ Latch section 130-1 ・ ・ ・ Latch first stage signal 130-2 ・・ Latch second stage signal 130-3 ・ ・ ・ Latch third stage signal 131 ・ ・ ・ ・ ・ Signal comparator 132 ・ ・ ・ ・ ・ Signal comparator output signal 133 ・ ・ ・ ・ ・ Signal combiner 134-1 ・..Address first stage signal 134-2 ... Address second stage signal 134-3 ... Address third stage signal 141 ・ ・ ・ ・ ・ Flat panel 142 ・ ・ ・ ・ ・ VSYNC 143 ・ ・ ・ ・ ・ HSYNC 144-Data line drive circuit 145-Common line drive circuit 146-Input pixel data 147-Serial / parallel conversion and memory element operation signal generator 148 ...・ ・ ・ Parallel pixel data 149 ・ ・ ・ ・ ・ Memory element output data 150 ・ ・ ・ ・ ・ Memory element section 151 ・ ・ ・ ・ ・ Synchronization section 152 ・ ・ ・ Synchronization section post-data 153 ・ ・ ・ ・ ・Panel drive signal conversion unit 154 ・ ・ ・ ・ ・ Panel drive signal 161 ・ ・ ・ ・ ・ Address signal generation circuit 162-1 ・・ Address first stage signal 162-2 ・ ・ ・ Address second stage signal 162-3 ・ ・ ・ Address third stage signal 163 ・ ・ ・ Memory element output data 164 ・ ・ ・ ・ ・ Output data 171 ・ ・ ・ ・・ Frequency divider 172 ・ ・ ・ ・ ・ Frequency divider reset signal creation unit 173 ・ ・ ・ ・ ・ Frequency divider reset signal 174 ・ ・ ・ Address signal 182 ・ ・ ・ Serial / parallel conversion unit 183 ・ ・・ ・ ・ Parallel pixel data 184 ・ ・ ・ ・ ・ Panel drive signal converter 185 ・ ・ ・ ・ ・ Panel drive signal

Claims (3)

[Claims] 1. A memory circuit for writing and reading data by an address signal generating circuit according to a first and a second external signal, wherein the address signal generating circuit includes an address changing means for changing an address by the first external signal. , An address cycle changing means for changing an address cycle by the second external signal, and a signal from the address changing means and the address cycle changing means, which is constant with respect to a read address of the memory circuit within the same address changing period. A memory circuit comprising: means for generating write addresses having different numbers of addresses. 2. A first signal converting means for converting the first external signal, which is the address changing means, into a frequency dividing signal by delaying or the like in the address signal generating circuit used in the memory circuit according to claim 1. A signal frequency dividing means for frequency dividing the frequency dividing signal synchronously or asynchronously, and a signal generating means for generating a reset signal of the frequency dividing means and a timing signal to be held in the signal holding means from the first and second external signals. A signal holding means for holding the maximum frequency division value output from the signal frequency dividing means and determined by the signal holding timing signal; and a signal for comparing the value held in the signal holding means with the output signal from the frequency dividing means. An address signal generating circuit comprising: a comparing means; and a second signal converting means for logically converting an output signal from the frequency dividing means with a signal from the signal comparing means. 3. A drive circuit for a flat panel, comprising the memory circuit according to claim 1 having a memory element corresponding to pixel data in the entire area or a part of the area of the panel, the pixel data being stored in the memory element of the memory circuit. A flat panel drive circuit, which performs writing and reading, and further converts the voltage into a signal used for driving the panel and outputs the signal.