JPS6123907B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a synchronization signal generating device for generating synchronization signals necessary for forming television signals. To generate a decoded synchronization signal for a television signal, the oscillation output frequency of the oscillator, which serves as the time reference, is sequentially stepped down by a group of counting circuits, and the signals corresponding to the various timings generated in the counting process are Of these, those needed to form a composite synchronization signal were extracted and led to a matrix circuit, and these various timing signals were combined to form a synchronization signal. In addition, in order to synchronously couple a conventional synchronizing signal generator with such a configuration to an external synchronizing signal, an appropriate counting circuit in the above-mentioned counting process is made to perform erroneous counting in accordance with the phase of the external synchronizing signal. In the past, the phase of the synchronization signal it generated was aligned with the external synchronization signal. Therefore, the conventional synchronization signal generator has an extremely complicated structure, and it is difficult to maintain the frequency interleaving relationship in the color television signal when synchronously combining with an external synchronization signal. . An object of the present invention is to provide a composite synchronization system that eliminates the above-mentioned conventional drawbacks, has a simple configuration, and maintains accurate frequency interleaving relationships of color television signals even when synchronously combined with an external synchronization signal. An object of the present invention is to provide a television signal synchronization signal generating device which enables a television signal to be obtained. That is, in the synchronization signal generating device of the present invention, the signal level and duration of each signal part in the composite synchronization signal waveform of a television signal are stored in advance in a programmable read-only memory, and the reference clock pulse, which is the reference for the time length, is stored in advance. A clock pulse having a frequency that is an integral multiple of the color subcarrier frequency of the television signal is designed to generate a synchronization signal having a predetermined signal waveform by sequentially reading out the signal levels of the stored contents at a timing corresponding to the counting. a clock pulse generator that generates a synchronizing signal of a television signal, and data representing the count values of the clock pulses corresponding to the signal levels and durations of successive signal parts in the synchronization signal of the television signal to addresses corresponding to the successive signal parts, respectively. a memory means for storing each,
an address counter for setting an address corresponding to the successive signal part after the duration of the successive signal part; and an address counter that sequentially increments the address by the address counter to determine the successive address represented by the data read from the memory means. a latch circuit that holds the signal level of the signal portion; and a clock counter that counts the clock pulses in relation to the duration of the sequential signal portions represented by the read data; The synchronization signal of the television signal is generated by extracting the signal level from the latch circuit for a time length corresponding to the count value of and forming a signal waveform of the signal portion in sequence. . The present invention will be described in detail below with reference to the drawings. The synchronization signal generator of the present invention not only generates the above-mentioned composite synchronization signal SYNC for television signals, but also generates various synchronization signals necessary for driving various devices used for forming television signals, that is, retrace lines. Blanking signal for erasing
BL, horizontal synchronization signal HD, vertical synchronization signal VD, horizontal reference number HR necessary to synchronously combine these synchronization signals with an external synchronization signal, and an odd field start point that is in phase with the horizontal synchronization signal. It also generates an indicating vertical reference number VR. Note that in even fields of standard television signals, scanning starts from the top center of the screen and ends at the bottom right corner of the screen, whereas in odd fields, scanning starts from the top left corner of the screen and ends at the bottom right corner of the screen. The scanning ends at the center of the bottom edge, so the starting point of the odd field is in phase with the horizontal synchronizing signal. Next, FIG. 1 shows an example of the configuration of the synchronization signal generator of the present invention. In the configuration example shown in Figure 1, reference clock pulses from a reference clock pulse generation source CPS (not shown) are counted sequentially according to a preset program corresponding to a predetermined signal waveform of a synchronization signal to be formed. By doing this, each signal part of the synchronization signal waveform having a predetermined duration is sequentially formed, and the repetition frequency of the reference clock pulse is equal to the color subcarrier frequency.
By choosing 4 times 3.579545MHz and using 14.318180MHz, the clock period will be 69.84127 nanoseconds. In the synchronization signal generator of the present invention, for example, for the composite synchronization signal SYNC, as shown in FIG.
At time 1, 23 clock periods after the start of the odd field 0, the equalization pulse rises, the high signal level H continues for the next 34 clock periods, and then at time 2 the equalization pulse falls;
The next equalization pulse rises at time point 4 after the low signal level L continues for the next 34+387 clock periods. Similarly, other signals, such as the blanking signal
BL rises at the start point 0 of the odd field, and the horizontal drive signal HD also rises at the start point 0 of the odd field, and then becomes 23+34+34.
The high signal level lasts for =91 clock periods and then falls at time point 3. The counting of reference clock pulses for waveform formation as described above is performed using a programmable read-only memory (P-ROM) that can be repeatedly read non-destructively after writing a desired program.
6 according to the program written in advance. The programmable read-only memory 6 has 20 parallel data output terminals 0 to 19, and is controlled by an 8-bit address code signal.
It is configured so that 256 addresses can be designated and their data can be read. 20 parallel data output bits 0 to 1 in the programmable read-only memory 6 described above
The allocation of 9 is as shown in Table 1.

[Table] In Table 1, the assigned data for bits 0 and 1 are branch flags to be described later, and the assigned data for bits 2 to 7 are various synchronization signals, and at the rising edge of each signal, the assigned data is "1", At the falling edge, it becomes "0". The assigned data of bits 8 and 9 is a count value correction permission flag for synchronous combination with an external synchronization signal, which will be described later.
The assigned data No. 19 is the count value of the reference clock pulse representing the signal duration width between the bending points of each signal waveform in various synchronization signals, that is, the rising or falling points of the signal waveform,
The output data of each of these bits is applied to the clock counter 2 to designate the count value of the reference clock pulse when forming a signal waveform, which will be described later.
Also, as will be described later, when the conditional branch flag of output bit 1 becomes "1" and it is necessary to branch from a certain point to another specified point, that is,
When it is necessary to jump from a specific address to another specific address, output bits 12-19 provide data indicating the address to which the branch is to be made. Next, aspects of generation of various synchronization signals in the apparatus of the present invention will be explained with respect to the configuration example shown in the first diagram. First, Table 2 shows the bit pattern of output data for each address set in the programmable read-only memory 6. The two left columns of Table 2 show addresses in an 8-bit configuration, the third column shows sequential points in time, and the right five columns show the 20 output data bits of the programmable read-only memory P-ROM. show.

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[Table] Address counter 7 in the configuration shown in Figure 1
specifies the read address of the programmable read-only memory 6, but now,
The output 1 of the address counter 7 is always “0” due to the action of the unconditional branch flag, which will be described later.
(00000000), at the start point of each field, the output 1 is "0", so the address input of the programmable read-only memory 6 is set to "0", as shown in Table 2. As mentioned above, various synchronization signals SYNC,
The output data of bit numbers 2 to 7 to which BL, HD, VD, HR, and VR are respectively assigned are "0", "1", "1", "1", "0", and "0", respectively.
Output data representing the rising edges of these signals are applied to input terminals D ₁ -D ₆ of latches 5, each consisting of a rising edge triggered D-flip-flop. On the other hand, the output of the clock counter 2 is the complement of "0" at the beginning of each field, that is, "1, 1, 1, 1, 1, 1, 1,
1, 1, 1”, so we added the output
The output of NAND circuit 1 becomes “0”, and the NAND
AND circuit with the output “1” inverted by inverter INV ₁ and the reference clock pulse
The output of AND ₁ also becomes "1" and is supplied to the AND output latch 5, and the output terminals Q ₁ to Q ₆ of the latch 5 are output at the timing of the rising edge of the reference clock pulse.
The bit pattern "0", "1", 1", "1", at the beginning of the field of each synchronization signal described above
“0” and “0” appear. As is clear from the timing charts shown in FIGS. 2 and 3, the state at the start point of the odd field is the same up to the time when the composite synchronization signal SYNC reaches the high level H.
Since it lasts for 23 clock periods, the count value "22" of the reference clock pulse during that period is applied to each terminal of the parallel data output bits 10 to 19 of the programmable read-only memory 6 as shown in the first row of Table 2. Bit number 1 at the time (000)
It appears in the form of "0000010110" as data from 0 to 19. Output data indicating the duration width of these signal waveforms is output from exclusive OR circuit group 3-2,
Full adder 4 and other exclusive OR circuit group 3-
1 in sequence, and is inverted and supplied to the input terminal 2 of the clock counter 2 in the form of a 22's complement. Note that the full adder 4 and the exclusive OR circuits 3-1 and 3-2 of the second group are necessary circuits when performing synchronous coupling with an external synchronization circuit, and the details will be described later, but the above-mentioned As described above, it also functions to invert the output data from the programmable read-only memory 6. As shown in the timing chart of FIG. 3, the output of the NAND gate circuit 1 is "0" at the starting point of the odd field.
The load input of clock counter 2, that is, the load input LD, is also “0”, and the clock input
Since the inverted reference clock pulse is supplied to CK via the inverter INV ₁ , the clock counter 2 receives the output data "22" from the programmable read-only memory 6 at the falling timing of the reference clock pulse. Data “22” with the polarity reversed is loaded. At this load timing, the latch 5 has already been supplied with and stored the output data of each synchronizing signal waveform from the programmable read-only memory 6 as described above, so it responds to the falling edge of the reference clock pulse. At the above-mentioned load timing with a 1/2 clock period delay, the output of clock counter 2 is output from NAND circuit 1,
AND gate circuit through inverter INV ₂
The latch 5 is controlled by the clock pulse passed through _the AND gate circuit _AND1 , and each signal waveform stored therein is sent out as an output signal waveform. Furthermore, if we take into account the time required to load the clock counter 2 mentioned above, each signal waveform at the start of the field actually lasts for 23 clock periods, so the clock pulses at the clock counter 2 The count will be "22". On the other hand, the output data “22” of programmable read-only memory 6 is output from clock counter 2.
When loaded, its output data “22” complement,
That is, (1, 1, 1, 1, 1, 0, 1, 0,
0, 1) appears at the output of the clock counter 2, the output of the NAND circuit 1 becomes "1", and the "1" output is inverted by the inverter INV ₂ and then sent to the master slave via the OR gate circuit OR ₁ . Joins the J terminal of flip-flop 9,
The rising edge of the reference clock pulse applied to the clock terminal CK drives the flip-flop 9, and the falling edge determines the output, and the output is delayed by one clock period and has the same pulse width as the reference clock pulse. Corresponding to the output "1", it is applied to the clock terminal CK of the address counter 7, and at the timing of the rising edge of the pulse, the address output of the address counter 7 is
Steps are made from address "0" corresponding to the odd field start point to address "1" corresponding to the next point in time. Note that the rises of the pulses applied to the load input LD of the clock counter 2 and the clock input CK of the address counter 7 are simultaneous, but after the rise of the pulse applied to the clock input CK of the address counter 7, the address output is " Since the step is performed from the address "0" to the address "1", the output data of the programmable read-only memory 6 changes from the contents of the address "0" to the contents of the address "1". Therefore, there is a time delay of at least about 60 nanoseconds in the access time of the programmable read-only memory 6 until the address changes, so the clock counter 2
is loaded with the contents of address “0” as the output data before the address change, and then about 60
After a nanosecond has elapsed, the output data of the programmable read-only memory 6 changes to the contents of address "1". At that time, the output of the NAND circuit 1 has already changed to "1" according to the load of the clock counter 2 mentioned above, so the output data at the address "1" mentioned above is changed to the clock counter 2.
It will not be loaded again. It should be noted that among the contents of the address "1", the data relating to the signal waveforms of bit numbers 2 to 7 are supplied to the inputs _D1 to _D6 of the latch 5, respectively, as described above. On the other hand, if, for example, the complement of the clock count value "22" is loaded as the input 2 of the clock counter 2, the output 2 will be the complement of "22", that is,
It becomes a binary number representing “22”, and therefore,
The output of the NAND circuit 1 becomes "1", and from then on, when the reference clock pulse arrives at the clock input CK via the inverter INV ₁ , at the timing of its falling edge, as shown in FIG.
After counting “-21”, “-20”, etc., and finishing counting for 22 clock cycles, the count output is finally converted into “-0”, that is, in binary form, and “1,”
1, 1, 1, 1, 1, 1, 1, 1, 1”,
The output of NAND circuit 1 becomes "0". However,
Since its NAND output is inverted by the inverter INV ₂ , the input of the subsequent AND gate circuit AND ₁ becomes "1" and supplies the reference clock to the clock input CK of the latch 5, which has already connected the parallel inputs D ₁ to
The signal waveform data of the contents of address “1” from the programmable read-only memory 6 supplied to D ₆ , that is, the output data “1” of bit numbers 2 to 7 at the time (001) in Table 2,
"1", "1", "1", and "0" are taken into the latch 5, and signal waveforms as shown in FIG. 3 are taken out as parallel outputs _Q1 to _Q6 . At the same time, since the output of the NAND circuit 1 is "0", a "0" signal is applied to the load input LD of the clock counter 2, and the clock counter 2 receives the "0" signal from the programmable read-only memory 6. Among the contents of address 1'', parallel output data ``33'' of bit numbers 10 to 19 is written, and counting of 33 clock cycles is started. Further, the address counter 7 is triggered by the reference clock pulse via the master-slave flip-flop 9.
The address output increments from address "1" to address "2", and programmable read-only memory 6 is set to read the contents of address "2". As described above, the composite synchronization signal shown in FIG.
The signal waveform that is at a high level for a period of 34 clock cycles corresponding to the pulse width of the equalization pulse between time points 1 and 2 in SYNO is taken out as the output signal of latch 5, but other signals BL, HD,
Regarding VD, HR, and VR, as shown in Figure 2,
The high level H continues as it is. By repeating the process described above, complex composite synchronization signal waveforms and other synchronization signal waveforms within the vertical blanking period for each field are sequentially formed. To form a signal waveform, use addresses up to address "89" in the programmable read-only memory 6 to indicate sequential bending points of the composite vertical synchronization signal waveform of odd fields in the composite synchronization signal waveform, and then For the image period, specify the waveform of the first horizontal scanning period as the data content at each address “90”, “91”, “92”, “93”, and “94”, and then The signal waveform of one horizontal scanning period is repeatedly read out and used 241 times up to the composite vertical synchronizing signal at the beginning of the succeeding even field. Therefore, as the stored contents of the programmable read-only memory 6, the data at addresses "90" to "94" is written only once and read out repeatedly 241 times. Therefore,
For the data at address “94”, set the conditional branch flag of bit number 1 in the parallel output data of programmable read-only memory 6 to “1” as shown at time (094) in Table 2. and when the conditional branch flag is "1", bit numbers 12 to 1 are set as the data content of the address at that time.
9, the branch destination address is written as shown in Table 1. That is, at the time of Table 2 (094)
In this case, the binary number "01011010" representing the branch destination address "90" is written into bit numbers 12-19. Next, repeated reading of the data contents of the above-mentioned addresses "90" to "94" in the programmable read-only memory 6 is performed by repeat counter 1.
The timing chart shown in FIG. 4 is performed under the control of step 4. That is, the initial output of the repeat counter 14 is the complement of "0", that is, 2 representing "-0".
The base number is "1, 1, 1, 1, 1, 1, 1, 1", and the output of the NAND circuit 13 that led to the output is also "0". Now, when the address counter 7 increments from address "0" to address "93" and address "94" is read out, bit number 1 of programmable read-only memory 6 is read.
The conditional branch flag "1" rises after the access time of the memory 6 has elapsed and is supplied to the D terminal of the edge trigger D-flip-flop 12.
It forms an output pulse that rises in synchronization with the fall of the reference clock pulse applied to the clock terminal CK.
The output pulses are followed by a master-slave flip-flop 11, an AND gate circuit 10 and 1.
6, and a flip-flop 11 and an AND gate circuit 10 form a pulse that rises in synchronization with the rise of the output pulse and lasts for one clock period. When the pulse from the AND gate circuit 10 is supplied to the clock input CK of the repeat counter 14, the load input LD is initially "0", so the number of repeated readouts "241" is "1" less than the "241" mentioned above. Complement of “−
240". Meanwhile, the clock input of repeat counter 14
The same pulse applied to CK is the OR gate circuit.
The output pulse is supplied to the J terminal of the master-slave flip-flop 9 via OR ₁ and OR ₂ , and the corresponding output pulse is applied to the clock input CK of the address counter 7. Therefore, the load input LD of the address counter 7 is "0", and the programmable read-only memory 6 has already been loaded.
Since the branch destination address "90" written in bit numbers 12 to 19 of address "94" is supplied, the data of the branch destination address "90" is written to the address counter 7. That is,
This means that address “94” has branched to address “90”. In this way, in the programmable read-only memory 6, the output data at address "90" is read out again as parallel output data, and thereafter, this process is repeated, and every time address "94" is reached, "90" Return to the address and AND gate circuit 1
The output pulse of 0 is supplied to the clock input CK of the repeat counter 14 every time it reaches address "94", and the memory contents of the repeat counter 14, which were initially set to "-240", are shown in the time chart in FIG. “−239” and “−238” in sequence as shown.
When the address reaches "94" after being repeated 241 times, that is, when the image period of the odd field ends, the repeat counter 14 completes its counting and becomes "-0", and the NAND The output of the circuit 13 becomes "0", the output of the NOR circuit 8 becomes "1", and the address counter 7
When the load input LD of the address counter 7 becomes "1", the signal load of the address counter 7, that is, loading is prohibited, and the output of the address counter 7 becomes as follows by the clock input applied one clock cycle later.
It advances to the next address "95" for the first time, and as shown in the time chart of FIG. 4, the process of repeated readout in the image period of the odd numbered field is exited and the transition is made to the composite vertical synchronization signal period of the even numbered field. During the above transition, repeat counter 1
Since the output of the NAND circuit 13 on the output side of the programmable read-only memory 6 is in the "0" state, the condition of bit number 1 in the output data at address "196" of the programmable read-only memory 6 is set at the start point of the even field. When the branch flag "1" arrives again, "-240" is loaded onto the repeat counter 14 again in the same manner as described above, and this process is repeated thereafter. The data of various synchronization signal waveforms for one frame written to the programmable read-only memory 6 in the above manner ends at address "196" including the conditional branch flag, and after that, it becomes "0" again. It returns to the address, but the programmable
If you use a read-only memory 6 that has a storage capacity beyond address “197”,
The unconditional branch flag of bit number 0 after address "197" is set to "1", the branch destination address of bit numbers 10 to 19 are all set to "0", and the D-flip-flop flag is set to "0" in the same way as the conditional branch. The address counter 7 is loaded to "0" via DFF ₂ and master-slave flip-flop MFF ₃ . The difference between such an unconditional branch and a conditional branch is that the branch is executed without passing through the repeat counter 14, and regardless of the output of the repeat counter 14, the address counter 7 is always set to "0". and no clock pulses are supplied to the repeat counter 14. Next, a mode of horizontal synchronization phase correction for synchronously combining with other external synchronization signals will be described. A full adder 4 is used for this horizontal synchronization phase correction. In the synchronization signal generator of the present invention, one horizontal scanning period consists of 910 clock cycles, and the full adder 4 increases or decreases the count value of the reference clock pulse in the output data of the programmable read-only memory 6, and the clock counter 2 By changing the clock pulse count value set in , the time length of the horizontal scanning period is made to match the phase of the external synchronization signal. The phase correction signal for the external synchronization signal is generated by guiding the horizontal reference number, HR, and the external synchronization signal to a synchronization phase difference detection section (not shown) to detect the phase difference between these signals, and outputting the detection output. ^The phase difference signal of 4 ^bits , ^that is, ²
It is converted into a base number and applied to input B of the full adder 4 via the horizontal synchronization phase correction request circuit. The maximum count value of this phase difference signal is 8 clocks. Further, the positive load sign C acting on the input A and the output A+B of the full adder 4 indicates the direction of increase/decrease of the phase difference signal described above, that is, the positive/negative polarity, and indicates the output data from the programmable read-only memory 6. When the count is decreased, it is "1" and when it is increased, it is "0".
The exclusive OR circuit 3-2 is supplied to the exclusive OR circuit 3-1 via an inverter, and controls these OR circuits. As mentioned above, the maximum count value for phase correction is 8 clocks, and to perform phase correction beyond that, the same count value of 8 clocks is repeated, but for phase correction below that, each bit 2 ⁰ , The phase correction amount is given by either 2 ¹ or 2 ² or a combination thereof. In order to correct the synchronization phase using such a phase difference signal, it is preferable to perform the phase correction during the image period in which the signal waveform retention period is the longest within one horizontal scanning period. As an address corresponding to the period, the correction permission flag of bit number 8 shown in Table 1 is set to "1", and the clock count value is adjusted at that point. Note that during the period of the vertical synchronization signal and the period in which equalization pulses are added before and after it, the composite synchronization signal waveform is repeated with a 1/2 horizontal scanning period, and the odd field is At the start of an even field, one horizontal scanning period is divided into two periods, one in which the blanking signal is "on" and the other in which it is "off." To increase or decrease the count value, divide one horizontal scanning period into two, divide the required correction amount into two times, and perform the correction twice.The timing control of the correction is shown in Table 1. The phase correction is performed using the 1/2 correction permission flag of bit number 9 shown above.
Increase/decrease only the count value up to ⁰ , 2 ¹ , 2 ² . In order to correct the clock count value for phase correction as described above in the full adder 4, when the above-mentioned plus/minus sign C is "0" and the clock count value is increased, the clock count value is read from the programmable read-only memory 6. After adding the data input A and correction request count value input B, the polarity of the above-mentioned addition output from the full adder 4 is determined by the exclusive OR circuit 3-1 to which a plus/minus sign C whose polarity is inverted by an inverter is applied. It is inverted and then supplied to the clock counter 2, and the plus/minus sign C
is "1" and the clock count value is to be decreased, the output data from the programmable read-only memory 6 is inverted by the exclusive OR circuit 3-2 to which a plus/minus sign C is applied, and then the full adder 4 It is supplied as input A to the clock counter 2, and after being added to the correction request count input B, it is supplied to the clock counter 2. That is, let the output data of the programmable read-only memory 6 be n,
If the correction required count value is r, when it increases -
(n+r), and when decreasing -n+r=-
Let (n-r) be the clock count value after correction. In addition, programmable read-only memory 6
The output data of is configured from the beginning so that the reciprocal of the clock count value, that is, when the clock count value is n, the reciprocal number - n is supplied to the clock counter 2. Therefore, the correction request input B of the full adder 4 The corrected clock count value after increasing or decreasing is also supplied to the clock counter 2 in the form of a complement of -(n+r) or -(n-r). Next, in order to correct the phase of the vertical synchronization signal with respect to the external synchronization signal, the count value of the horizontal scanning period in the repeat counter 14 is gradually increased or decreased by a maximum of one horizontal scanning period per field. . Detecting the phase difference between the vertical reference number VR of bit number 7 in Table 1 generated by the generator of the present invention and the vertical synchronization signal in the external synchronization signal,
When the phase difference of the detection output is 2 horizontal scanning periods or more, the data of 2 ¹ = 2 horizontal scanning periods is supplied as input 3 of the repeat counter 14 via the scanning line correction request circuit, and when the phase difference is 1 When the horizontal scanning period is 2 ⁰ = 1 horizontal scanning period data,
Similarly, it is supplied as input 3 of the repeat counter 14 via the scanning line correction request circuit. Further, the plus/minus sign _C2 indicates the direction of increase/decrease in the correction, and is set to "0" when the correction is increased and "1" when the correction is decreased. Furthermore, flip-flop 15 is used to discriminate between odd and even fields. The above-mentioned phase correction of the vertical synchronization signal is performed based on the following operating principle. That is, the repeat counter 14 is set to count, for example, 240 horizontal scanning periods, but the complement of "240", "-240", is expressed in binary as "0, 0, 0, 0,"
1, 1, 1, 1", and the complement of "241" that follows "-241" is "0, 0, 0, 0, 1, 1, 1,
0”, the complement of the preceding “239” “-239” is “0,”
0, 0, 1, 0, 0, 0, 0'', therefore, to increase or decrease the count value by one horizontal scanning period per field, that is, two horizontal scanning periods per frame, as shown in Fig. 5. The correction input of the repeat counter 14 is set as shown in the timing chart.At this time, in order to set the direction of increase/decrease of the correction amount by the plus/minus sign _C2 , the plus/minus sign _C2 must be "0", That is, when increasing, the NAND ₂ circuit is driven via an inverter to set only the ²⁰ bits at the input 3 of the repeat counter 14 to "0", and the other bits 2 ¹ , 2 ² , 2
³ are set to "1", and when the plus/minus sign _C2 is "1", that is, a decrease, the AND ₂ circuit is driven to set only the ²⁴ bits at input 3 of the repeat counter 14 to "1", and the other bits are set to "1". Set all bits to “0”. When one horizontal scanning period is to be corrected per frame, the count value is corrected in the same manner as described above for only either the odd field or the even field using the output of the flip-flop 15.
Note that if it is necessary to perform phase correction for two or more horizontal scanning periods per frame, the required amount of phase correction can be performed using a full adder similar to that used for horizontal synchronization phase correction. Clock counter 2 in the configuration shown in the first diagram
And the count output value of the repeat counter 14 is
Although it is unstable immediately after the device is powered on,
Once counting is started, a series of counting is performed, and after counting out to the "-0" state, a stable and normal operating state is achieved. Furthermore, for reading from address "198" onward, the programmable read-only memory 6 sets the bit number (0) to "1" which instructs a forced return to address "0" using the unconditional branch flag, and the clock signal. “1” of bit number (19) indicates a counting command that makes counting meaningless.
Since these are written alternately, the structure is such that the address immediately returns to "0". In the above explanation, there is no particular mention of the insertion of a color burst signal into a composite synchronization signal by the synchronization signal generator of the present invention, but the clock frequency of the basic clock pulse generation source is set to four times the color subcarrier frequency. Therefore, if this reference clock pulse generation source is also used for color subcarrier generation, it is possible to easily generate a color burst signal.Moreover, once the composite synchronization signal has been generated as described above, The color burst signal can be easily inserted. Further, in addition to the high level "1" and the low level "0", the signal level of the signal formed by the generator of the present invention may also be set to the signal level of the color burst signal to form a multi-level signal. If you set the read-only memory program so that addresses “90” to “94” and “192” to “196”
By writing the program to the address, color burst signals can be sequentially inserted when composite synchronizing signal waveforms are sequentially formed. In addition, as the memory data of the programmable read-only memory in the configuration example shown in the first figure, the data of the signal waveform of the vertical synchronization signal of the odd field and the vertical synchronization signal of the even field in the compound signal waveform is written, Although the data of each composite vertical synchronizing signal waveform that differs between odd and even fields due to a phase shift of 1/2 horizontal scanning period with respect to the horizontal synchronizing signal of the composite vertical synchronizing signal in odd and even fields is written as is. Since the difference in signal waveforms is only due to the difference in relative phase between the vertical synchronization signal and the horizontal synchronization signal, if the clock count value within the vertical retrace period is corrected to correspond to the difference in relative phase, , most of the data of the composite vertical synchronization signal waveform of the odd-even fields can be shared by the odd-even fields, for example by adding an appropriate conditional branch flag, and furthermore, the data of the composite vertical synchronization signal waveform of one field Even when considering only the waveform, for example, for a signal portion in which equalized pulse waveforms are repeatedly arranged, repetitive readout similar to the repetitive readout of horizontal synchronizing pulses in the image period can be performed. Therefore, such changes in the data read operations on the composite vertical sync signal waveform result in a programmable
The storage capacity of read-only memory can be significantly reduced. As is clear from the above description, according to the present invention, a programmable read-only memory is provided with a reference clock pulse having a repetition frequency that has a certain relationship, for example, a fourfold relationship, with the color subcarrier frequency of a television signal. By counting the reference clock pulses and setting the duration of each signal part, it is possible to form the signal waveforms of various synchronization signals, including composite synchronization signals, using a memory device with extremely small storage capacity. It is possible to generate various synchronization signals with a simple configuration, and also allows synchronization with external synchronization signals.
This can be done very easily by correcting the clock pulse counts and the horizontal scan period counts, and once the phase of the color burst signal in the external signal and the reference clock pulse are combined, the frequency interleaving of the color subcarriers can be adjusted. Since the relationship can be maintained at all times, the synchronous signal waveform will not be adversely affected even when synchronous coupling is performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of the synchronization signal generating device of the present invention, FIG. 2 is a signal waveform diagram showing required timing charts of various synchronization signals of the television standard system, and FIG. 3 is the configuration shown in FIG. 1. A signal waveform diagram showing a timing chart of various synchronization signals according to read data of the programmable read-only memory in the example shown in FIG. FIG. 5 is a signal waveform diagram showing a timing chart of vertical synchronization phase correction in the configuration example shown in FIG. 1, 13...NAND circuit, 2...Clock counter, 3-1, 3-2...Exclusive OR circuit,
4... Full adder, 5... Latch, 6... Programmable read-only memory, 7... Address counter, 8... NOR circuit, 9, 11,
15...Master-slave flip-flop, 1
0, 16...AND circuit, 12...Rising edge trigger gate-D flip-flop, 14...Repeat counter.

Claims (1)

[Scope of Claims] 1. A clock pulse generator that generates a clock pulse having a frequency that is an integral multiple of the color subcarrier frequency of a television signal, and corresponds to the signal level and duration of sequential signal parts in the synchronization signal of the television signal. memory means for storing data representing the counted values of the clock pulses in respective addresses corresponding to the successive signal parts; an address counter to be set; a latch circuit that sequentially increments addresses by the address counter and holds the signal levels of the sequential signal portions represented by the data read from the memory means; a clock counter for counting the clock pulses in relation to the duration of the signal portion of the latch circuit, and extracting the signal level from the latch circuit for a length of time corresponding to the count of the clock pulses by the clock counter. A synchronization signal generating device characterized in that a synchronization signal of a television signal is generated by forming a signal waveform of the signal portions sequentially. 2. The phase of the generated synchronization signal is controlled by increasing or decreasing the count value of the clock pulse corresponding to the duration of the sequential signal portions represented by the data read from the memory means. A synchronizing signal generator according to claim 1. 3. A clock pulse generator for generating clock pulses having a frequency that is an integer multiple of the color subcarrier frequency of the television signal, and counts of said clock pulses corresponding to the signal levels and durations of successive signal portions of the synchronization signal of the television signal. and an address counter for setting the address corresponding to the successive signal portion after the duration of the successive signal portion; a latch circuit that sequentially increments the address by the address counter and holds the signal level of the sequential signal portions represented by the data read from the memory means; and a continuation of the sequential signal portions represented by the read data. a clock counter for counting the clock pulses in relation to time; and a clock counter configured to repeatedly set the same address corresponding to a signal portion having the same signal waveform in the synchronization signal when the signal portion having the same signal waveform repeats a plurality of times. a repeat counter for controlling the address counter, and when a signal portion having the same signal waveform in the synchronization signal is repeated a plurality of times, the same signal waveform is controlled by the repeat counter and stored in the memory means. The data representing the clock signal is read out from the same address of the memory means by repeating the data a plurality of times, and the signal level is extracted from the latch circuit for a time period corresponding to the count value of the clock pulse by the clock counter, and the signal level is sequentially read out from the latch circuit. 1. A synchronization signal generating device characterized in that a synchronization signal for a television signal is generated by forming a signal waveform of a portion. 4. The synchronization signal generating device according to claim 3, wherein the phase of the synchronization signal to be generated is controlled by increasing or decreasing the number of times the repeat control is performed by the repeat counter.