CN100356418C - Universal panel display controller and control method thereof - Google Patents
Universal panel display controller and control method thereof Download PDFInfo
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- CN100356418C CN100356418C CNB2004100938672A CN200410093867A CN100356418C CN 100356418 C CN100356418 C CN 100356418C CN B2004100938672 A CNB2004100938672 A CN B2004100938672A CN 200410093867 A CN200410093867 A CN 200410093867A CN 100356418 C CN100356418 C CN 100356418C
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Abstract
The present invention relates to a structure and a controller of a panel display, particularly to a controller which is provided with a PWM waveform generator and a configurable register, can be used for various displays such as LCD, FED, PDP, etc., and belongs to the panel display technical field. The peripheral control circuits of the existing panel displays are all designed through programmable logic devices or special circuits ASIC; even though the scanning control principle is the same, the displays can not be universal or standardized. The controller of the present invention comprises seven parts such as a digit transducer, an I<2>C interface controller, the PWM wave generator, etc. which are integrated, wherein the configurable register is adopted to output various display control signals and clock signals with different display resolutions, different field frequencies and different data writing modes. The PWM wave generator is adopted to generate pulse-wide modulation drive signals to provide high-voltage excitation signals required by FED, PDP, etc. Reverse control signals meeting LCD display are generated through a column scanning controller. The present invention can optimize display system circuits, reduce cost and realize standardization.
Description
Technical field
The present invention relates to the driving and the control technology of flat-panel monitor, particularly have PWM waveform generator and configurable register, can be used for the display controller of various flat-panel monitors such as LCD, FED, PDP, belong to technical field of flat panel display.
Background technology
Flat-panel monitor has become the main flow of information display technology development now, and various dissimilar flat-panel display devices such as LCD, PDP, FED, OLED etc. competitively develop, and image displaying quality is become better and better, and application is more and more wider.Say that from system aspects any flat panel display systems all is made up of three parts: video processing circuit, display module and interface control circuit.Wherein video processing circuit all is identical to any flat-panel monitor, and existing many universal circuits can be selected for the deviser; And display module is made up of display matrix and driving circuit, dissimilar display devices, and its display mechanism, display screen structure and driving circuit have very big difference, but all realize by driving circuit separately; For interface control circuit, respectively the unit of research and development and manufacturer all are basis situations separately at present, adopt programming device or exploitation special circuit ASIC such as FPGA.Dissimilar its interface control circuit of product of the product of different manufacturers or same producer is all different.Make that not only the cost of display system is high, and the formation of the product that is difficult to realize to standardize.By analysis, various types of flat-panel monitors have a common characteristic, promptly all are to adopt matrix structure, and its drive principle is consistent, and picture element scan method for addressing and process all are by row, show by row point by point scanning.Therefore invent a kind of universal panel display controller; can realize control, not only have very big design flexibility, and realize the standardization of flat panel display easily different flat-panel display devices; be convenient to large-scale production, improve interchangeability, maintainability, reduction system cost.But still there is not this general flat-panel monitor control method at present both at home and abroad.
Summary of the invention
The objective of the invention is to develop a kind of for the various active-addressed general display controllers of flat-panel monitor, built-in scan controller and PDM keyer (PWM) can provide needed pixel clock signal and row, field scan control timing signal for flat-panel monitor.
Technical scheme of the present invention:
Adopt fully integrated method for designing, element circuits such as digital frequency converter, column scan controller, line scanning controller, PWM waveform generator, Memory Controller are integrated, be designed to IP kernel.
1, adopts three groups of configurable data registers, characterize type, resolution and the scan mode of flat-panel monitor.
2, digital frequency converter is used for producing the clock frequency signal of appointment according to display resolution that sets and scan mode.
3, column scan controller and line scanning controller are used for producing the control signal of reading data from storer
4, the PWM waveform generator is used for producing and the output pulse width modulation signal.Can be used to encourage the high-voltage generator in the flat panel display.
The concrete technical scheme of the present invention is as follows:
This universal panel display controller, it comprises digital frequency converter, I
2C interface controller, status register, PWM waveform generator, column scan controller, line scanning controller, Memory Controller are characterized in they are integrated;
Digital frequency converter 1: form by data latches 12, delay circuit 11 and logical operation circuit 10 3 parts; The data input pin of data latches 12 links to each other with configuration register 13, receive and latch the data of configuration register 13, the input end of clock of delay circuit and logical operation circuit is directly linked external clock input, exports the DCLK signal at output terminal behind the signal process XOR of logical operation circuit the clock signal of outside input and after delaying time; External timing signal CLK inputs to logical operation circuit and delay circuit, delay circuit is according to the control code D0-D7 of data latches, frequency signal f1-f8 through time-delay is delivered to logical operation circuit, again by the clock signal DCLK of logical operation circuit output through frequency-conversion processing;
I
2C interface controller 2:I
2C interface controller inside is made up of deserializer, time schedule controller, address generator circuit; I
2The C interface controller links to each other with the outer CPU interface by universal serial bus, links to each other with configuration register 13, configuration register 14, configuration register 15, PWM waveform generator 4, status register 3 respectively with 8 position datawires by 3 bit address lines; I
2The C interface controller receives the I of outer CPU
2The C protocol signal, inwardly under the control of location generator, order write each configuration register, the relation of address and internal register is: 000 is configuration register 13; 001 and 010 is the PWM register; 011 and 100 is configuration register 14; 101 and 110 is configuration register 15; 111 is status register;
Status register 3: form by one 8 bit data register; 8 bit data incoming line and I
2C interface controller data bus links to each other, and 8 bit data output lines are linked I
2The data output buffer of C interface controller; By I
2C interface controller 8 bit data of packing into;
PWM waveform generator 4: can preset presetting of initial value by a frequency divider 8 and one and seal in/incorporate into and go here and there out shift register 9 and form; The input end of clock of frequency divider is linked external clock CLK, and the parallel data input end of internal displacement register is linked I
2The data bus of C interface controller, the direct output pwm signal of PWM output terminal; Receive outside clock signal, according to the initial value that presets of internal register, output turnable pulse width signal;
Column scan controller 5: form by presetting cycle counter 16, MUX 17, frequency divider 18; The data initialization end of cycle counter links to each other with configuration register 14, and the clock input of counter links to each other with the output of digital frequency converter, and the input of MUX links to each other with row synchronous Hs, field synchronization Vs, pixel clock DCLK; Cycle counter is put initial value by configuration register 14, then clock DCLK is subtracted counting, output VCK and OE signal when counter is zero entirely.MUX selects one of Hs, Vs and DCLK to carry out exporting the POL signal behind the two divided-frequency;
Line scanning controller 6: by can preset cycle counter 19, delay counter 20, delay counter 21, delay counter 22 and or door 23 form; The data initialization end of cycle counter links to each other with configuration register 15, and counting clock links to each other with the column scan controller, and delay counter links to each other with column scan controller, input signal Vsy, input signal Hsy respectively; Cycle counter is put initial value by configuration register 15, and the output signal VCK to the column scan controller subtracts counting then, counter complete zero the time through or door output Vs signal, or another input of door is from the delay counter of Vsy; The VCK signal of column scan controller output is exported the Hs signal after delaying time, the Hsy signal outputs to Memory Controller and is used for producing the HF signal after time-delay;
Memory Controller 7: form by pulse shaping circuit and monopulse generator; Input end is received Vsy and the Hsy signal that the line scanning controller receives, and CS, VF and HF signal be externally output directly; Pulse shaping circuit carries out exporting the CS signal through frequency division after the shaping to the Vsy signal.The Vsy signal lag is after monopulse generator is exported the VF signal, and the Hsy signal lag is after monopulse generator output HF signal;
Beneficial effect of the present invention: universal panel display controller can dispose display resolution and scan mode flexibly according to user's needs; Have versatility, can control the flat-panel monitor of multiple dot matrix addressing such as LCD, PDP, FED, OLED.Can realize the standardized designs of flat panel display systems, reduce the display system cost.
Description of drawings:
Fig. 1: flat-panel monitor general purpose controller structured flowchart
Fig. 2: PWM waveform generator structured flowchart
Fig. 3: digital frequency converter structured flowchart
Fig. 4: column scan controller architecture block diagram
Fig. 5: line scanning controller architecture block diagram
Among the figure
1. digital frequency converter 2.I
2 C interface controller 3. status register 4.PWM waveform generators 5. column scan controllers 6. line scanning controllers 7. Memory Controllers 8. frequency dividers 9. seal in/incorporate/go here and there out 15.16 configuration registers of shift register 10. logical operation circuit 14.16 configuration registers of 13.8 configuration registers of 11. delay circuits, 12. data latches, 17. Port Multipliers, 18. frequency dividers 19. into can preset cycle counter 20. delay counter 21. delay counters, 22. delay counters 23. or door
Embodiment
This universal panel display controller, it comprises digital frequency converter, I
2C interface controller, status register, PWM waveform generator, column scan controller, line scanning controller, Memory Controller is characterized in that: they are integrated:
Digital frequency converter 1: form by data latches 12, delay circuit 11 and logical operation circuit 10 3 parts; The data input pin of data latches 12 links to each other with configuration register 13, receive and latch the data of configuration register 13, the input end of clock of delay circuit and logical operation circuit is directly linked external clock input, exports the DCLK signal at output terminal behind the signal process XOR of logical operation circuit the clock signal of outside input and after delaying time; External timing signal CLK inputs to logical operation circuit and delay circuit, delay circuit is according to the control code D0-D7 of data latches, frequency signal f1-f8 through time-delay is delivered to logical operation circuit, again by the clock signal DCLK of logical operation circuit output through frequency-conversion processing;
I
2C interface controller 2:I
2C interface controller inside is made up of deserializer, time schedule controller, address generator circuit; I
2The C interface controller links to each other with the outer CPU interface by universal serial bus, links to each other with configuration register 13, configuration register 14, configuration register 15, PWM waveform generator 4, status register 3 respectively with 8 position datawires by 3 bit address lines; I
2The C interface controller receives the I of outer CPU
2The C protocol signal, inwardly under the control of location generator, order write each configuration register, the relation of address and internal register is: 000 is configuration register 13; 001 and 010 is the PWM register; 011 and 100 is configuration register 14; 101 and 110 is configuration register 15; 111 is status register;
Status register 3: form by one 8 bit data register; 8 bit data incoming line and I
2C interface controller data bus links to each other, and 8 bit data output lines are linked I
2The data output buffer of C interface controller; By I
2C interface controller 8 bit data of packing into;
PWM waveform generator 4: can preset presetting of initial value by a frequency divider 8 and one and seal in/incorporate into and go here and there out shift register 9 and form; The input end of clock of frequency divider is linked external clock CLK, and the parallel data input end of internal displacement register is linked I
2The data bus of C interface controller, the direct output pwm signal of PWM output terminal; Receive outside clock signal, according to the initial value that presets of internal register, output turnable pulse width signal;
Column scan controller 5: form by presetting cycle counter 16, MUX 17, frequency divider 18; The data initialization end of cycle counter links to each other with configuration register 14, and the clock input of counter links to each other with the output of digital frequency converter, and the input of MUX links to each other with row synchronous Hs, field synchronization Vs, pixel clock DCLK; Cycle counter is put initial value by configuration register 14, then clock DCLK is subtracted counting, output VCK and OE signal when counter is zero entirely.MUX selects one of Hs, Vs and DCLK to carry out exporting the POL signal behind the two divided-frequency;
Line scanning controller 6: by can preset cycle counter 19, delay counter 20, delay counter 21, delay counter 22 and or door 23 form; The data initialization end of cycle counter links to each other with configuration register 15, and counting clock links to each other with the column scan controller, and delay counter links to each other with column scan controller, input signal Vsy, input signal Hsy respectively; Cycle counter is put initial value by configuration register 15, and the output signal VCK to the column scan controller subtracts counting then, counter complete zero the time through or door output Vs signal, or another input of door is from the delay counter of Vsy; The VCK signal of column scan controller output is exported the Hs signal after delaying time, the Hsy signal outputs to Memory Controller and is used for producing the HF signal after time-delay;
Memory Controller 7: form by pulse shaping circuit and monopulse generator; Input end is received Vsy and the Hsy signal that the line scanning controller receives, and CS, VF and HF signal be externally output directly; Pulse shaping circuit carries out exporting the CS signal through frequency division after the shaping to the Vsy signal.The Vsy signal lag is after monopulse generator is exported the VF signal, and the Hsy signal lag is after monopulse generator output HF signal;
PWM waveform generator, its frequency divider 8 are made up of d type flip flop; The outside input clock of clock termination, inverse output terminal is received D data input pin own, and the forward output terminal is received the clock end of shift register; External clock is connected on the clock of d type flip flop, and the clock signal behind forward data output terminal output two divided-frequency is as the shift clock of shift register; Parallel data input termination I
2C interface controller data bus, serial input terminal connect last bit serial output terminal, constitute shift counter 9; Under the control of shift clock, by serial data output terminal output square-wave signal;
But being made of 16 d type flip flops, shift register 9 can preset parallel input data, serializable input data, and the circulating register of serial output.
Digital frequency converter, its logical operation circuit 10. is made up of XOR circuit and basic gate circuit, and input end of clock connects outer clock circuit and delay circuit, the outer output terminal of output termination clock signal; After the frequency signal f1-f8 of clock signal clk and time-delay carries out logical operation such as XOR, the clock signal after the output frequency conversion;
Whether its delay circuit 11 is made of 8 basic delay units that are cascaded, and each delay unit is made up of the two-stage reverser, and control this delay unit by an electronic switch and work; The control termination data latches 12 of 8 delay units, input end of clock connect the external clock input, and output terminal is received logical operation circuit; After the control code of latch 12 was determined, input clock signal f0 one or several among the output frequency signal f1-f8 after delaying time given logical operation circuit;
Its data latches 12 is formed data latches by 8 D flip-flops; Data input pin is received the data line of configuration register 13, and data output end connects delay circuit; Produce the control code of delay circuit according to the prevalue of data latches.
The control method of this universal panel display controller, pass through following step successively:
(1) duty is set: pass through I before the system works
2The C interface controller reads in user's configuration data Data, comprise exploration on display resolution ratio, the field refreshing frequency, the DDC highway width, information such as pwm signal dutycycle and LCD inversion mode, configuration register 13, configuration register 14 and configuration register 15 are set, thus the duty of initialization system.
(2) generation of pixel clock signal: configuration register 13 is according to the resolution of the flat-panel monitor that will control, field refreshing frequency and DDC highway width are set the frequency conversion ratio of digital frequency converter, external clock signal clk is become needed pixel clock frequency DCLK output, as the pixel clock signal of flat-panel monitor.Simultaneously DCLK is also as the work counting clock of column scan controller.
The generation of (3) line scanning control signal: the line scanning control signal comprises field sync signal Vs and line synchronizing signal Hs.
Vs determines the beginning of the synchronous and first line scanning process of each field picture signal and signal source image information.Export the Vs signal in both cases, when the field sync signal Vsy of image source arrives, after the time-delay of determining, output Vs signal; The line scanning controller subtracts counting to the VCK signal all the time, and the count cycle is determined according to the content of configuration register 15, when counter is zero entirely, exports the Vs signal.Line synchronizing signal Hs determines the beginning of column scan process in each row, after the scan shift signal VCK that is expert at arrives, is high level through Hs after the time-delay of determining, becomes low level at the rising edge of VCK.
The generation of (4) column scan control signal: the column scan control signal comprises line scanning shift signal VCK and writes screen enable signal OE.The VCK signal is produced by the pixel clock counter, and counter writes initial value after the Vs signal arrives, and subtracts counting then, its count cycle is by the set condition decision of configuration register 14, when counter arrives zero, produce a VCK signal output, show the data line end of scan.The OE signal be flat-panel monitor such as LCD need write the enable signal of data to screen, can be as required set and select pointwise write, write line by line or by writing by configuration register (14).
(5) generation of pwm signal: pwm signal is produced by the PWM waveform generator, passes through I
2The C controller initialize data is packed into seal in/incorporate/go here and there out shift register into, its output terminal and serial input terminal connect together, under the driving of Clock dividers, the pulse duty factor of shift register output is determined by initialize data.
(6) generation of storer control signal: the storer control signal comprises a switching signal CS and two synchronous reference signal VF, HF.Most flat-panel monitor controllers all are provided with two groups of storeies, and one group is in the state of writing, and another group is in read states.The storer that is in the state of writing will produce address signal according to signal source field synchronization reference signal VF and row synchronous reference signal HF, through to the suitable coding of video data with writing data into memory.The address signal that is in the storer of read states is produced by Vs, Hs and DCLK, and the sense data of order is delivered to the screen data bus.The read-write state of two storeies is switched by the CS signal controlling.
(7) generation of LCD video reversal of poles control signal POL: the POL signal is produced by the column scan controller, be used to control the AC driving of LCD vision signal, the column scan controller obtains the POL signal to the drive signal two divided-frequency, when being driven by pixel clock, is the row inversion mode; When driving, be the row inversion mode by line synchronizing signal; When driving, be the field reversal mode by field sync signal; When driving jointly, be an inversion mode by pixel clock and line synchronizing signal.
(8) control method of universal panel display controller comprises: work schedule: after controller powers on or resets, and I
2The C interface controller at first writes each configuration register to data by outside MCU; Digital frequency converter is gone out the frequency output DCLK signal of pixel clock according to the value of configuration register 13 by display resolution, a refreshing frequency and three calculation of parameter of data-bus width; The column scan controller reads the data of configuration register 14, the calculating pixel clock count cycle, and give the counter initialize, counter begins counting, output VCK, OE, POL signal; The line scanning controller reads the data of configuration register 15, calculates the VCK count cycle, and gives the counter initialize, counter begins counting, and counter arrives to zero or Vsy signal, all can export Vs, in any moment, Vs all counters that arrive are put initial value, VCK time-delay back output Hs; The Vsy in Memory Controller waiting signal source and Hsy signal through output VF and HF signal after the shaping, can be used as the addressing marking signal to memory write operation, and the two divided-frequency of VF signal is exported as the CS signal; The PWM waveform generator is exported the square-wave signal of adjustable dutycycle under the driving of system reference clock.
Status register (3): be one 8 bit data register, can be read the state of a control of display controller by the user, the status information of reading is used as the foundation of other circuit modules of design.
The state of D0-D2 shows the display resolution of flat-panel monitor, have 8 kinds of situations, 000 shows that current output resolution ratio is 640*480,001 represents 800*600,010 represents 1024*768, and 011 represents 1280*1024, and 100 represent 1600*1200,101 represent 1024*720, and 111 represent 1920*1080.
The state of D3-D5 shows the field refreshing frequency of flat-panel monitor, has 8 kinds of situations, and 000 shows that current output field refreshing frequency is 60Hz, and 001 represents 70Hz, 010 represents 75Hz, and 011 represents 85Hz, and 100 represent 90Hz, 101 represent 100Hz, and 110 represent 120Hz, and 111 represent 125Hz.
The state of D6-D7 shows the data channel highway width of flat-panel monitor, have 4 kinds of situations, 00 shows that current employing single channel (8) data write display screen, on behalf of 2 passages (16) data, 01 write display screen, on behalf of 4 passages (32) data, 10 write display screen, and on behalf of 8 passages (64) data, 11 write display screen.
Technique scheme by software emulation, can be gone into IP kernel with the design of VIIDL hardware description language, utilizes programmable logic device (PLD) (FPGA) to verify; Utilize Cadence software, adopt 0.35u and following multiple layer metal CMOS integrated circuit technology condition to come the design circuit domain, finish Front-end Design and rear end emulation, form the IP kernel of this invention product with standard domain (GDSII) file.
Claims (8)
1. universal panel display controller, it comprises digital frequency converter, I
2C interface controller, status register, PWM waveform generator, column scan controller, line scanning controller, Memory Controller is characterized in that: they are integrated:
Digital frequency converter (1): form by data latches (12), delay circuit (11) and logical operation circuit (10) three parts; The data input pin of data latches (12) links to each other with configuration register (13), receive and latch the data of configuration register (13), the input end of clock of delay circuit and logical operation circuit is directly linked external clock input, exports the DCLK signal at output terminal behind the signal process XOR of logical operation circuit the clock signal of outside input and after delaying time; External timing signal CLK inputs to logical operation circuit and delay circuit, delay circuit is according to the control code D0-D7 of data latches, frequency signal f1-f8 through time-delay is delivered to logical operation circuit, again by the clock signal DCLK of logical operation circuit output through frequency-conversion processing;
I
2C interface controller (2): I
2C interface controller inside is made up of deserializer, time schedule controller, address generator circuit; I
2The C interface controller links to each other with the outer CPU interface by universal serial bus, links to each other with configuration register (13), configuration register (14), configuration register (15), PWM waveform generator (4), status register (3) respectively with 8 position datawires by 3 bit address lines; I
2The C interface controller receives the I of outer CPU
2The C protocol signal, inwardly under the control of location generator, order write each configuration register, the relation of address and internal register is: 000 is configuration register 13; 001 and 010 is the PWM register; 011 and 100 is configuration register 14; 101 and 110 is configuration register 15; 111 is status register;
Status register (3): form by one 8 bit data register; 8 bit data incoming line and I
2C interface controller data bus links to each other, and 8 bit data output lines are linked I
2The data output buffer of C interface controller; By I
2C interface controller 8 bit data of packing into;
PWM waveform generator (4): can preset presetting of initial value by a frequency divider (8) and one and seal in/incorporate into and go here and there out shift register (9) and form; The input end of clock of frequency divider is linked external clock CLK, and the parallel data input end of internal displacement register is linked I
2The data bus of C interface controller, the direct output pwm signal of PWM output terminal; Receive outside clock signal, according to the initial value that presets of internal register, output turnable pulse width signal;
Column scan controller (5): form by presetting cycle counter (16), MUX (17), frequency divider (18); The data initialization end of cycle counter links to each other with configuration register (14), and the clock input of counter links to each other with the output of digital frequency converter, and the input of MUX links to each other with row synchronous Hs, field synchronization Vs, pixel clock DCLK; Cycle counter is put initial value by configuration register (14), then clock DCLK is subtracted counting, output VCK and OE signal when counter is zero entirely.MUX selects one of Hs, Vs and DCLK to carry out exporting the POL signal behind the two divided-frequency;
Line scanning controller (6): by can preset cycle counter (19), delay counter (20), delay counter (21), delay counter (22) and or door (23) form; The data initialization end of cycle counter links to each other with configuration register (15), and counting clock links to each other with the column scan controller, and delay counter links to each other with column scan controller, input signal Vsy, input signal Hsy respectively; Cycle counter is put initial value by configuration register (15), and the output signal VCK to the column scan controller subtracts counting then, counter complete zero the time through or door output Vs signal, or another input of door is from the delay counter of Vsy; The VCK signal of column scan controller output is exported the Hs signal after delaying time, the Hsy signal outputs to Memory Controller and is used for producing the HF signal after time-delay;
Memory Controller (7): form by pulse shaping circuit and monopulse generator; Input end is received Vsy and the Hsy signal that the line scanning controller receives, and CS, VF and HF signal be externally output directly; Pulse shaping circuit carries out exporting the CS signal through frequency division after the shaping to the Vsy signal.The Vsy signal lag is after monopulse generator is exported the VF signal, and the Hsy signal lag is after monopulse generator output HF signal;
2. universal panel display controller according to claim 1 is characterized in that: the PWM waveform generator, and its frequency divider (8) is made up of d type flip flop; The outside input clock of clock termination, inverse output terminal is received D data input pin own, and the forward output terminal is received the clock end of shift register; External clock is connected on the clock of d type flip flop, and the clock signal behind forward data output terminal output two divided-frequency is as the shift clock of shift register; Parallel data input termination I
2C interface controller data bus, serial input terminal connect last bit serial output terminal, constitute shift counter (9); Under the control of shift clock, by serial data output terminal output square-wave signal;
Shift register (9) but constitute by 16 d type flip flops and can preset parallel input data, serializable input data, and the circulating register of serial output.
3. universal panel display controller according to claim 1, it is characterized in that: digital frequency converter, its logical operation circuit (10): be made up of XOR circuit and basic gate circuit, input end of clock connects outer clock circuit and delay circuit, the outer output terminal of output termination clock signal; After the frequency signal f1-f8 of clock signal clk and time-delay carries out logical operation such as XOR, the clock signal after the output frequency conversion;
Whether its delay circuit (11) is made of 8 basic delay units that are cascaded, and each delay unit is made up of the two-stage reverser, and control this delay unit by an electronic switch and work; The control termination data latches (12) of 8 delay units, input end of clock connect the external clock input, and output terminal is received logical operation circuit; After the control code of latch (12) was determined, input clock signal f0 one or several among the output frequency signal f1-f8 after delaying time given logical operation circuit;
Its data latches (12) is formed data latches by 8 D flip-flops; Data input pin is received the data line of configuration register (13), and data output end connects delay circuit; Produce the control code of delay circuit according to the prevalue of data latches.
4. universal panel display controller according to claim 1 is characterized in that: configuration register (13) is made of the unit 8 data register, and data input pin meets I
2C interface controller data bus, the data latches (12) of output termination digital frequency converter is from I
2The C interface controller writes configuration data the data latches (12) of digital frequency converter.
5. universal panel display controller according to claim 1 is characterized in that: configuration register (14) is made of 16 cell data registers; Data input pin meets I
2C interface controller data bus, output termination column scan controller configuration data input end; From I
2The C interface controller writes column scan controller configuration data input end to configuration data.
6. universal panel display controller according to claim 1 is characterized in that: configuration register (15) is made of 16 cell data registers; Data input pin meets I
2C interface controller data bus, output termination line scanning controller configuration data input end; From I
2The C interface controller is configuration data writing line scanning monitor configuration data input end.
7. the control method of a universal panel display controller is characterized in that passing through following step successively:
(1) duty is set: pass through I before the system works
2The C interface controller is by user's configuration data Data, comprise exploration on display resolution ratio, the field refreshing frequency, the DDC highway width, pwm signal dutycycle and LCD inversion mode information, configuration register (13), configuration register (14) and configuration register (15) are set, thus the duty of initialization system.
(2) generation of pixel clock signal: configuration register (13) is according to the resolution of the flat-panel monitor that will control, field refreshing frequency and DDC highway width are set the frequency conversion ratio of digital frequency converter, external clock signal clk is become needed pixel clock frequency DCLK output, as the pixel clock signal of flat-panel monitor.Simultaneously DCLK is also as the work counting clock of column scan controller.
The generation of (3) line scanning control signal: the line scanning control signal comprises field sync signal Vs and line synchronizing signal Hs.Vs determines the beginning of the synchronous and first line scanning process of each field picture signal and signal source image information.Export the Vs signal in both cases, when the field sync signal Vsy of image source arrives, after the time-delay of determining, output Vs signal; The line scanning controller subtracts counting to the VCK signal all the time, and the count cycle is determined according to the content of configuration register (15), when counter is zero entirely, exports the Vs signal.Line synchronizing signal Hs determines the beginning of column scan process in each row, after the scan shift signal VCK that is expert at arrives, is high level through Hs after the time-delay of determining, becomes low level at the rising edge of VCK.
The generation of (4) column scan control signal: the column scan control signal comprises line scanning shift signal VCK and writes screen enable signal OE.The VCK signal is produced by the pixel clock counter, and counter writes initial value after the Vs signal arrives, and subtracts counting then, its count cycle is by the set condition decision of configuration register (14), when counter arrives zero, produce a VCK signal output, show the data line end of scan.The OE signal be flat-panel monitor such as LCD need write the enable signal of data to screen, can be as required set and select pointwise write, write line by line or by writing by configuration register (14).
(5) generation of pwm signal: pwm signal is produced by the PWM waveform generator, passes through I
2The C controller initialize data is packed into seal in/incorporate/go here and there out shift register into, its output terminal and serial input terminal connect together, under the driving of Clock dividers, the pulse duty factor of shift register output is determined by initialize data.
(6) generation of storer control signal: the storer control signal comprises a switching signal CS and two synchronous reference signal VF, HF.Most flat-panel monitor controllers all are provided with two groups of storeies, and one group is in the state of writing, and another group is in read states.The storer that is in the state of writing will produce address signal according to signal source field synchronization reference signal VF and row synchronous reference signal HF, through to the suitable coding of video data with writing data into memory.The address signal that is in the storer of read states is produced by Vs, Hs and DCLK, and the sense data of order is delivered to the screen data bus.The read-write state of two storeies is switched by the CS signal controlling.
(7) generation of LCD video reversal of poles control signal POL: the POL signal is produced by the column scan controller, be used to control the AC driving of LCD vision signal, the column scan controller obtains the POL signal to the drive signal two divided-frequency, when being driven by pixel clock, is the row inversion mode; When driving, be the row inversion mode by line synchronizing signal; When driving, be the field reversal mode by field sync signal; When driving jointly, be an inversion mode by pixel clock and line synchronizing signal.
8. the control method of universal panel display controller according to claim 7 is characterized in that: work schedule: after controller powers on or resets, and I
2The C interface controller at first writes each configuration register to data by outside MCU; Digital frequency converter is gone out the frequency output DCLK signal of pixel clock according to the value of configuration register (13) by display resolution, a refreshing frequency and three calculation of parameter of data-bus width; The column scan controller reads the data of configuration register (14), the calculating pixel clock count cycle, and give the counter initialize, counter begins counting, output VCK, OE, POL signal; The line scanning controller reads the data of configuration register (15), calculates the VCK count cycle, and gives the counter initialize, counter begins counting, and counter arrives to zero or Vsy signal, all can export Vs, in any moment, Vs all counters that arrive are put initial value, VCK time-delay back output Hs; The Vsy in Memory Controller waiting signal source and Hsy signal through output VF and HF signal after the shaping, can be used as the addressing marking signal to memory write operation, and the two divided-frequency of VF signal is exported as the CS signal; The PWM waveform generator is exported the square-wave signal of adjustable dutycycle under the driving of system reference clock.
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