CN100351894C

CN100351894C - Driving circuit of planar display device with adjustable size

Info

Publication number: CN100351894C
Application number: CNB2005100218799A
Authority: CN
Inventors: 杨传仁; 李益全
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2005-10-18
Filing date: 2005-10-18
Publication date: 2007-11-28
Anticipated expiration: 2025-10-18
Also published as: CN1746958A

Abstract

The present invention relates to a drive circuit of a planar display device with an adjustable size, which belongs to the electronic technical field, particularly to a drive circuit of a planar display device. The present invention comprises a clock generator, a column shift register, a column latch, a column signal drive circuit, a row shift register, a row scan drive circuit and a row and column number control module which is used for adjusting the size, wherein a cascade enabling end 16 can be added to the clock generator 1 to realize the cascade. The present invention is a drive circuit which is suitable for planar display devices in different sizes, has excellent portability, and can adjust the size of an FPD circuit according to sizes of panels of planar display devices to drive planar display devices in different sizes; simultaneously, the present invention has a cascade function to drive planar display device in larger sizes. Because the entire drive circuit mainly uses fundamental digital unit circuits, the entire circuit has the advantages of simple structure and convenient integration.

Description

The driving circuit of planar display device of adjustable scale

Technical field

The driving circuit of planar display device of adjustable scale belongs to electronic technology field, particularly the driving circuit of flat-panel display device.

Background technology

Flat-panel monitor (FPD) has thin type, lightweight, low-voltage driving, low-power consumption, does not have outstanding advantages such as X ray and flicker compared with traditional cathode ray tube (CRT).Make it attract people's attention, made aspects such as high speed information circuit, HDTV, multimedia adopt the problem of FPD to become hot issue in the application of aspects such as portable computer, mobile television, wall-hanging TV, computing machine, household electrical appliance.

Flat-panel monitor mainly comprises LCD (LCD), light emitting diode indicator (LED), plasma scope (PDP), electroluminescent display (ELD) and field-emitter display (FED) etc.Particularly LCD have that operating voltage is low, power consumption is little, the display message amount is big, the life-span long, easy of integration, be convenient for carrying and advantage such as electromagnetic radiation pollution is little, in display technique, be a dark horse, have bright development prospect, be widely used in electronic products such as mobile phone, PDA product, handheld instrument instrument and household electrical appliance and the equipment.Developing rapidly of flat-panel monitor be unable to do without the driving circuit supporting with it, and it is another big branch of flat panel display industry, occupies and consequence.In the flat-panel monitor complete machine, therefore its display driver circuit we can say that the development of driving circuit is restricting the progress of flat-panel monitor to a great extent no matter be that technology content or price ratio are all very big.

Driving circuit is the flat panel display systems important component part, be the interface circuit that is specifically designed between computing machine or MCU and the panel display screen, its major function is to carry out phase place, peak value, the isoparametric modulation of frequency and set up driving electric field by it being outputed on the electrodes of flat panel display parts electric potential signal.With reference to existing patent (CN1052565A and United States Patent (USP) 6,275,204 etc.), present existing flat pannel display driving circuit mainly is made up of clock generator 1, column shift register 2, row latch 3, column signal driving circuit 4, line shift register 5 and line-scanning drive circuit 6, and its basic structure substantially as shown in Figure 1.

The external clock end 11 of clock generator 1 receives the clock signal clk that adds; It holds 12 reception horizontal-drive signal HD and vertical synchronizing signal VD to come as reference timing signal synchronously, and horizontal-drive signal HD and vertical synchronizing signal VD are synchronous with DI video input signals hereinafter.

The data input pin 21 external video input signals DI from PC or MCU of column shift register 2, its clock end 22 connects the output pulse ends 13 of clock generator 1, receives row shift pulse CLK1.The working method of most flat-panel monitors (particularly LCD) is to line by line scan, and soon each column signal is added on the display row electrode simultaneously in the delegation, and the time of keeping a line scanning.By the time this row end of holding time, when transferring to next line (be next line add select voltage), voltage should be transformed into the voltage that next line should apply on the time simultaneously on each row electrode of display.The function of column shift register 2 is under shift pulse CLK1 effect, be provided with the n row, by n CLK1 PRT, n column signal all deposited in the column shift register 2 successively, and can be by the n bit parallel output terminal 23 of column shift register 2 simultaneously to row latch 3 and line output.

The n bit parallel data input pin 31 of row latch 3 docks with the n bit parallel output terminal 23 of column shift register 2; Its clock signal terminal 32 connects the output pulse ends 14 of clock generator 1, receives latch pulse signal LP; The n position output terminal 33 of row latch connects the n bit parallel input end 41 of column signal driving circuit 4.Row latch 3 can rank the n of input end 31 signal and transfer to output terminal 41 simultaneously under latch pulse LP effect, after LP uses up, is in high-impedance state between input port and the delivery outlet.

The n position input end 41 of column signal driving circuit 4 connects the n position output terminal 33 of row latch 3, and its n position output terminal 42 directly connects n row contact conductor of flat-panel display device 7.Column signal driving circuit 4 plays a level transferance, V here ₀-V _xAs the bias voltage input of column signal driving circuit, can select for use for the row electrode, its output level need elect according to the characteristics of flat-panel display device.

The clock end 52 of line shift register 5 connects the output pulse ends 14 of clock generator 1, receives shift pulse signal CLK2; Its serial input terminal 51 connects the output pulse signal end 15 of clock generator 1, and received frame signal FLM is as asserts signal; Line shift register 5 has only 1 bit serial input mode, and when the FLM signal was effective, data were frame signal FLM, and pulsewidth accounts for a line time, only deposits a pulse signal in line shift register 5 in, moves forward by turn under shift pulse signal CLK2 effect then.The cycle of row shift pulse signal CLK2 is the n doubly (n is a columns) of row shift pulse signal CLK1, and the shift pulse of line shift register 5 is spaced apart a line period, and row shift pulse CLK2 and row latch pulse LP are synchronous.

The principle of work of driving circuit is as follows:

As shown in Figure 2, (1) video data DI (be made as the 1st row) under row shift pulse CLK1 effect, deposits column shift register 2 in successively.All column data in being filled with a line period, frame signal FLM puts high level, and the FLM signal is moved into line shift register 5; Row latch 3 is under latch pulse LP effect, video data with this row is latched in the row latch 3 simultaneously, and outputs to column signal driving circuit 4, and column signal driving circuit 4 produces the driving voltage of each row electrode of display device, at this moment the 1st the row gating, thereby realize the 1st the row display operation; (2) when showing the 1st row, the video data DI of the 2nd row is transferred to column shift register 2 under the effect of data shift pulse signal CLK1, after the transmission of second line data is finished, frame signal FLM is changed to low level, under latch pulse signal LP effect, video data DI is latched in the row latch 3, simultaneously the FLM signal is moved into line shift register 5, and the data in the line shift register 5 are shifted once simultaneously, and output on line-scanning drive circuit 6, thereby realized the 2nd display operation of going.Circulation step (2) is finished all display operations of going of a frame; The display operation of next frame is finished in circulation step (1), (2).

But foregoing driving circuit ranks shift register all is the fixing register of figure place, and a driving circuit all can only drive the FPD of a certain specific scale (scale is meant the ranks pixel of display device), does not have versatility.Because the specification of FPD differs bigger, and all will develop the special driving circuit for it at the FPD of each size scale, has wasted lot of manpower and material resources and time like this.

Summary of the invention

The purpose of this invention is to provide a kind of display driver circuit that can be used for the FPD panel of different scales, can adjust FPD driving circuit scale according to the concrete size of different FPD panels.

Driving circuit of the present invention is a FPD driving circuit that function is comparatively complete.In order to satisfy the actual needs of current most FPD display application on a small scale, our designed FPD driving circuit has m COM (OK) and n SEG (row) output, and it mainly contains following several major functions:

(1) driving FPD shows;

(2) support with bus form directly and MCU link;

(3) (n is value continuously for m * n), m can to drive the FPD of different scales;

(4) cascade by a plurality of driving circuits is to drive fairly large FPD.

The driving circuit of planar display device of adjustable scale of the present invention, as shown in Figure 3, comprise clock generator 1, column shift register 2, row latch 3, column signal driving circuit 4, line shift register 5 and line-scanning drive circuit 6, it is characterized in that, it also comprises a ranks numerical control molding piece 8, can insert line number NH and the columns NL that needs the flat-panel display device that drives respectively by two

input ends

81 and 82 of ranks numerical control molding piece 8, to realize adjustable scale; And on clock generator 1, can increase a cascade Enable Pin 16, to realize cascade; In addition, two impact dampers have also newly been added, impact damper A is between the clock end 52 of the output pulse ends 14 of clock generator 1 and line shift register 5, and impact damper B controls the shift pulse of row and column respectively between the clock end 22 of the output pulse ends 13 of clock generator 1 and column shift register 2.

Ranks numerical control molding piece 8 is to constitute (see figure 4) by

columns controlling sub

9 and 10 two submodules of line number controlling sub.Columns controlling sub 9 and line number controlling sub 10 are all formed by putting counter, and the maximum count of its counter is respectively the figure place of the register of column shift register 2 and line shift register 5.

The line number input end 81 and the columns input end 82 of ranks numerical control molding piece 8 connect outer row columns control input end, can import the ranks number (NH, NL) of the FPD that needs driving by it; Its column count clock end 83 connects the output pulse ends 13 of clock generator 1, the counting clock of row shift pulse CP1 as row; Row counting clock end 84 connects the output pulse ends 14 of clock generator 1, the counting clock of row shift pulse CP2 as row; The capable shift pulse control end 85 of ranks numerical control molding piece 8 connects the Enable Pin of impact damper A, to control capable shift pulse; Row shift pulse control end 86 connects the Enable Pin of impact damper B, with the shift pulse of control row; Its horizontal reset end 87 connects the reset terminal 54 of line shift register 5, and row reset terminal 88 connects the reset terminal 24 of column shift register 2.

The course of work of entire circuit can be described as: establishing column shift register is the n position, under shift pulse CLK1 effect, column shift register 2 every displacements once, counter in the columns controlling sub 9 is once counted (adding 1) with regard to accounting, up to equaling the columns NL that columns input end 82 presets, its row shift pulse control end 86 will produce a high level, impact damper B is a high-impedance state, the output terminal of clock 13 of clock generator 1 and the clock end 22 of column shift register 2 are disconnected, column shift register 2 will stop displacement and make it stop transmission signals to the full signal of register of peripheral control unit output, produce row latch pulse LP up to clock generator 1 and make 3 work of row latch, the video data of this delegation is deposited in the row latch 3, gone to drive the signal demonstration that FPD finishes this row by column signal driver 4 then.And the counter in the columns controlling sub 9 continues counting under the output pulse CP1 of the output terminal of clock 13 of clock generator 1 effect, up to the maximum count value n that equals counter (being the figure place of column shift register), it can be in pulse of row reset terminal 88 outputs, column shift register 2 is resetted, row shift pulse control end 86 output low levels simultaneously, column shift register 2 under row shift pulse CLK1 effect, begin again the to be shifted column signal of storage next line.If line shift register is the m position, be expert under the shift pulse CLK2 effect, line shift register 5 every displacements once, the counter of line number controlling sub 10 is once counted (adding 1) with regard to accounting, up to equaling the line number NH that line number input end 81 ends preset, its capable shift pulse control end 85 will produce a high level, and impact damper B is a high-impedance state, and line shift register 5 is quit work.And the counter in the line number controlling sub 10 continues counting under the output pulse CP2 of the output terminal of clock 14 of clock generator 1 effect, up to the maximum count value m that equals counter (being the figure place of line shift register), its reset pulse HR of reset terminal 87 output that can be expert at, line shift register 5 is resetted, capable simultaneously shift pulse control end 85 output low levels, clock generator 1 produces frame signal FLM then, has so just finished the display operation of a frame.Move in circles, so continue.

Because shift register is serial input and line output, if the register figure place is too many, and very few in requisition for the columns that shows, can cause time delay to increase, may cause the scintillation of flat-panel monitor, so the preferable scope of application of the present invention is that the pixel of ranks is less than 640.In order to be suitable for driving more massive FPD screen, the present invention provides a cascade Enable Pin 16 on clock generator 1.When to cascade Enable Pin 16 input selected signals, this drive circuit module operate as normal; When not choosing, clock generator 1 can be to other module output drive pulse signal, and then driving circuit is not just worked.The input signal of this port is by row cascade signal (high position) and is that two parts of row cascade signal (low level) constitute, expands by capable cascade and row cascade that the capable cascade signal and the row cascade signal of this port input can be realized this drive circuit module respectively.

The present invention is a kind of driving circuit applicable to the different scales flat-panel display device, has excellent transplantability, and can adjust the FPD circuit scale according to the size of flat-panel display device panel, to drive the flat-panel display device of different scales; Has cascade function simultaneously, to drive more massive flat-panel display device.Because what whole driving circuit mainly utilized is basic digital units circuit, make entire circuit simple in structure, be convenient to integrated.

Description of drawings

Fig. 1 has the main structured flowchart of driving circuit now.1 expression clock generator, 11,12,13,14,15 represent the external clock end of clock generator 1, synchronous end, output pulse signal end a, output pulse signal end b and output pulse signal end c respectively; 2 expression column shift registers, 21,22,23 represent video data input end, shift clock end and the parallel output terminal of column shift register 2 respectively; 3 expression row latchs, 31,32,33 represent parallel input end, latch clock end and the parallel output terminal of row latch 3 respectively; 4 expression column signal driving circuits, 41,42 represent the input end and the output terminal of column signal driving circuit 4 respectively; 5 expression line shift registers, 51,52,53 represent the serial input terminal of shift register 5 respectively, shift clock end and parallel output terminal; 6 expression line-scanning drive circuits, 61,62 represent the parallel input end and the parallel output terminal of line-scanning drive circuit 6 respectively; 7 expression flat-panel display devices, 71,72 is respectively its row electrode and column electrode.

The working timing figure of the existing driving circuit of Fig. 2.

The primary structure block diagram of Fig. 3 driving circuit of the present invention.Among the figure with Fig. 1 in the same meaning of identical symbolic representation, only introduce the symbol that newly adds here.8 expression ranks numerical control molding pieces, 81～88 represent line number input end, columns input end, column count clock end, row counting clock end, row shift pulse control end, row shift pulse control end, horizontal reset end and row reset terminal respectively; The 16th, the Enable Pin of

clock generator

1,24 and 54 is respectively the reset terminal of column shift register 2 and line shift register 5.

The structured flowchart of Fig. 4 ranks numerical control molding piece inside.

The line number control function sequential chart of Fig. 5 embodiment.

The columns control function sequential chart of Fig. 6 embodiment.

The cascade layout viewing of the driver module of Fig. 7 embodiment.

Embodiment

According to a preferred embodiment of the present invention, this driving circuit has 64 row and 64 row outputs.Have many control ends, its controller can easily be controlled neatly, can carry out cascade expansion satisfying fairly large FPD (cascade is maximum respectively between the cascade in the ranks of this module and row supports 4) by cascade Enable Pin 16, columns input end 82 and line number input end 81 can be adjusted the line scanning electrode of driving circuit output and the number of column signal electrode according to the scale of the FPD of the required driving of reality respectively in not exceeding 64 scope.Column shift register 2, line shift register 5 and row latch 3 all are 64; The line number input end 81 of ranks numerical control molding piece 8 and columns input end 82 are 6 inputs; Cascade Enable Pin 16 is 4 inputs, and row cascade signal and row cascade signal are respectively 2, and ranks can be supported 4 these circuit module cascades (supporting 16 cascades altogether) respectively.Illustrate, suppose to have FPD screen (128 * 172), we can drive with six modules of the present invention, make respectively when being provided with that CS is 0000,0001,0010,0100,0101,0110, just can constitute this module array of driving of 2 * 3, it arranges synoptic diagram as shown in Figure 5.

The simple circuit system architecture of a preferable embodiment of the present invention as shown in Figure 3.The main modular that contains in the driving circuit among the embodiment: clock generator 1, column shift register 2, row latch 3, column signal driving circuit 4, line shift register 5, line-scanning drive circuit 6 and ranks numerical control molding piece 8.The course of work of this driving circuit is as follows:

(1) video data DI (be made as the 1st row) under row shift pulse CLK1 effect, deposits column shift register 2 in successively, and is connected to row latch 3 input ends 31.Frame signal FLM puts high level, and is expert under the shift pulse CLK2 effect, the FLM signal is moved in the line shift register 5 of drive system.Column shift register 2 every displacements once, counter in the columns controlling sub 9 is once counted (adding 1) with regard to accounting, will produce a high level up to equaling its row shift pulse control end 86 of columns NL that columns input end 82 presets, impact damper B is a high-impedance state, column shift register will stop displacement and make it stop transmission signals to the full signal of register of controller output, produce row latch pulse LP up to clock generator 1 and make 3 work of row latch, the video data of this delegation is deposited in the row latch 3, gone to drive the signal demonstration that FPD finishes this row by column signal driver 4 then.And the counter in the columns controlling sub 9 continues counting under the output pulse CP1 of the output terminal of clock 13 of clock generator 1 effect, up to equaling 64, it can be in pulse of row reset terminal 88 outputs, column shift register 2 is resetted, row shift pulse control end 86 output low levels simultaneously, column shift register 2 under row shift pulse CLK1 effect, begin again the to be shifted column signal of storage next line.At this moment the 1st the row gating, thereby realize the 1st the row display operation.The operation (see figure 6) of columns control.

(2) when showing the 1st row, the video data of the 2nd row is transferred to column shift register 2 under the effect of data shift pulse signal CLK1, similar with said process, after the display data transmissions of second row is finished, frame signal FLM is changed to low level, under latch pulse signal LP effect, video data is latched in the row latch 3, simultaneously the FLM signal is moved in the line shift register 5, and the data in the line shift register 5 are shifted simultaneously once by 6 outputs of line scanning driver, also have the rolling counters forward of while line number controlling sub 10 once (to add 1), thereby realized the display operation of the 2nd row.Circulation step (2) equals the line number NH that line number control end 81 presets up to the numerical value of the counter of line number controlling sub 10, thereby finishes display operations of all row of a frame; The operation (see figure 7) of line number control.The display operation of next frame is finished in circulation step (1), (2).

Though the present invention with a preferred embodiment explanation as above; yet be not to be used for limiting the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the present invention; should do some improvement and retouching, so protection scope of the present invention is when looking being as the criterion that the accompanying Claim book defined.

Claims

1, the driving circuit of planar display device of adjustable scale, comprise clock generator (1), column shift register (2), row latch (3), column signal driving circuit (4), line shift register (5) and line-scanning drive circuit (6), it is characterized in that, it also comprises a ranks numerical control molding piece (8), two input ends (81) by ranks numerical control molding piece (8) and (82) can be inserted line number NH and the columns NL that needs the flat-panel display device that drives respectively, to realize adjustable scale; In addition, also comprise two impact dampers, impact damper A is between the clock end (52) of the output pulse ends (14) of clock generator (1) and line shift register (5), impact damper B controls the shift pulse of row and column respectively between the clock end (22) of the output pulse ends (13) of clock generator (1) and column shift register (2).

2, the driving circuit of planar display device of adjustable scale according to claim 1 is characterized in that, described ranks numerical control molding piece (8) is made of columns controlling sub (9) and (10) two submodules of line number controlling sub; Columns controlling sub (9) and line number controlling sub (10) are all formed by putting counter, and the maximum count of its counter is respectively the figure place of the register of column shift register (2) and line shift register (5).

3, the driving circuit of planar display device of adjustable scale according to claim 1, it is characterized in that, the line number input end (81) and the columns input end (82) of ranks numerical control molding piece (8) connect outer row columns control input end, can import ranks number N H, the NL of the FPD that needs driving by it; Its column count clock end (83) connects the output pulse ends (13) of clock generator (1), the counting clock of row shift pulse CP1 as row; Row counting clock end (84) connects the output pulse ends (14) of clock generator (1), the counting clock of row shift pulse CP2 as row; The capable shift pulse control end (85) of ranks numerical control molding piece (8) connects the Enable Pin of impact damper A, to control capable shift pulse; Row shift pulse control end (86) connects the Enable Pin of impact damper B, with the shift pulse of control row; Its horizontal reset end (87) connects the reset terminal (54) of line shift register (5), and row reset terminal (88) connects the reset terminal (24) of column shift register (2).

4, the driving circuit of planar display device of adjustable scale according to claim 1, it is characterized in that, increased a cascade Enable Pin (16) on the clock generator (1), to realize cascade: when to cascade Enable Pin (16) input selected signal, this driving circuit operate as normal; When not choosing, this driving circuit is not just worked; The input signal of cascade Enable Pin (16) is to be made of row cascade signal and two parts of row cascade signal, expands by capable cascade and row cascade that the capable cascade signal and the row cascade signal of cascade Enable Pin (16) input can be realized this driving circuit respectively.

5, the driving circuit of planar display device of adjustable scale according to claim 1 is characterized in that, described driving circuit has 64 row and 64 row outputs; The columns input end (82) of ranks numerical control molding piece (8) and line number input end (81) are 6 inputs, can adjust the line scanning electrode of driving circuit output and the number of column signal electrode in not exceeding 64 scope according to the scale of the FPD of the required driving of reality respectively; Column shift register (2), line shift register (5) and row latch (3) all are 64; Cascade Enable Pin (16) is 4 inputs, and row cascade signal and row cascade signal are respectively 2, and ranks can be supported 4 these driving circuit cascades respectively.