JP2005538397A - Control unit and method for reducing interference patterns in image display on a screen - Google Patents

Abstract

A control unit and method are provided for reducing interference patterns in displaying an image on a screen having a pixel frequency. The image is represented by pixel data and supplied to the screen by the control unit. When generating pixel data, a clock signal used for generating pixel data is changed, or a pixel frequency is changed.

Description

  The present invention relates to a control unit and method for controlling a screen, and more particularly to a control unit and method for reducing interference patterns in displaying an image on a screen. In particular, the present invention relates to a method and control device for use with a TFT / LCD screen.

  In complex systems that use multiple signals, the interference between the digital and analog components increases while the pattern size decreases. This fact is acute in systems that have multiple clock signals (clock domains) on one chip and use approximate frequencies for digital data processing and analog data acquisition.

  Particularly in graphic applications, such interference effects present an aspect of the interference pattern in the output image, which will be described in more detail below with respect to TFT / LCD screens (TFT = Thin Film Transistor; LCD = Liquid Crystal Display). .

  To connect the TFT / LCD screen to common image sources (PC graphics card etc: VGA, DVI and parallel port (PC = personal computer; VGA = video graphics adapter; DVI = digital video input)) There is a need for an LCD control unit that takes input data, converts them into digital RGB data (RGB = red, green, blue) and outputs them in waveforms (pixel frequencies) required by various screens.

  FIG. 8 is a simplified block diagram of a conventional LCD control chip 800. Control chip 800 receives input signals from various input sources 802, 804, and 806. A signal source 802, shown schematically, provides an analog video input signal (AVI = analog video input). The signal source 804 supplies a digital video input signal (DVI = digital video input). The signal source 806 supplies a parallel video input signal (PVI = parallel video input). The input signals supplied to the control chip 800 by the input sources 802-806 are input to the input selection unit 808, which selects the input signals to be processed and supplies them to the input 810 of the control chip 800. To do. The signal supplied to input 810 is supplied to a processing unit 812 having a FIFO memory (FIFO = first in first out) and memory elements. This memory combined with the processing means 812 is connected to a memory interface 814 (MI = memory interface). The processing unit 812 outputs the pixel data to be displayed on the screen via the output 814 and the output interface 816 to the screen at the pixel frequency ppll_clk. Furthermore, the control chip 800 has a configuration block 818 that is driven by the system clock sys_clk.

  In the processing unit 812, the signal is input with a clock fclk corresponding to the clocks (DVI_clk, AVI_clk, PVI_clk) of the input signals obtained from the input sources 802-806.

  As shown in FIG. 8, various clocks (clock domains) of the input source (AVI_clk, DVI_clk, PVI_clk), as well as additional clocks (domains) for the memory interface 814 (mpll_clk) and the screen interface 818 (ppll_clk) Are supplied on the control chip 800 according to the type of the control unit. Furthermore, a system clock sys_clk is also supplied.

  The control chip 800 shown in FIG. 8, for example, is disposed on a printed circuit board and receives video or graphic signals supplied by a computer for drawing and display on a screen, for example.

  In such a control unit, the problem arises that the clock signal is combined with one or several of the inputs of the control chip via the substrate of the control chip 800 and superimposed on the input signal. As a result, a troublesome interference pattern is generated in displaying data on the screen. This problem is described below with respect to the signal received at the analog input.

  It should be noted here that, theoretically, for the various inputs of the control chip 800, the DVI input 804 may be subject to interference by other clock signals (clock domains) through the substrate of the chip, However, to simplify the explanation here, the analog input 802 (AVI) is limited to interference, and the memory clock signal mpll_clk and the screen clock signal ppll_clk are used as interference sources, and these signals usually have low impedance. The case of coupling to the analog input AVI through the substrate of the control chip 800 is described below.

  In the simplest case of interference that frequently occurs in the LCD control unit, an interference signal having the frequency (pixel frequency) of the screen clock ppll_clk and an interference signal having a harmonic of this clock are present on the analog video input 802 (AVI). It is a case where it couple | bonds with each. There are several possibilities as to how the interference signal is generated and how it enters the low impedance substrate of chip 800. In addition to the digital logic in the core, the input / output driver of the output interface 818 can be viewed as the main source of substrate voltage.

  FIG. 9 shows an equivalent circuit of the screen interface, that is, the output interface 818 of FIG. The elements of the memory chip are shown in the left part of FIG. 9 (left side of the broken line), and the elements of the circuit board are shown on the right side of the broken line.

The illustrated interface receives at its driver stage 822 from output 816 a pixel signal to be displayed on the screen at the screen pixel frequency ppll_clk. In the illustrated example, the driver stage 822 includes a first field effect transistor 822a and a second field effect transistor 822b. The output of the driver stage 822 is connected to a pad of the control chip 800, the pad, the impedance comprising resistors part and parts by volume has with respect to ground of the substrate, which resistance R ₁ and capacitor C in FIG. 9 Shown in ₁ . The control chip 800 is connected to the housing via a bonding wire in order to connect the pad of the control chip to the pad of the chip housing. FIG. 9 shows an inductance part L ₁ and a resistance part R ₂ of the impedance of the bonding wire.

In addition, the capacitive part of the impedance of the pad and the housing to which the control chip is connected via the bonding wire, the inductance part, and the resistance part are shown as a resistor R ₃ , an inductance L ₂ and capacitors C ₂ and C _3. Yes.

The circuit board is provided with a transmission line TL for outputting a signal output from the control chip to another driver stage, and this driver stage transmits the signal to the screen. Similar to the driver stage 822, the driver stage 824 includes a first field effect transistor 824a and a second field effect transistor 824b. Further, the capacity of the housing of the driver stage 824 is indicated by a capacity C ₄ .

Further, in FIG. 9, the voltage drops through the inductance _{L 1} u L (t) is shown in relation to the inductance L _1. As already mentioned, one of the main sources of substrate voltage is the output signal of the input / output driver stage 822 of the screen interface. This interface generates a very steep signal (large di / dt) that passes through the bonding wire and pad inductances L ₁ , L ₂ and resistors R ₁ , R ₂ , R ₃ . This can cause voltage drops of up to several hundred mV (u _L (t)) through the bonding wire, which can be coupled directly or indirectly to the substrate of the control chip 800 depending on the driver layout. To do.

  Other sources of interference at the analog input of the control chip 800 are also considered mass or supply voltage interference (bounce), which can be caused by inadequate or lack of control chip separation at the digital core, or supply voltage It can be caused by inadequate guidance (power route allocation) of the supply line.

In both cases, the visible effects are very similar and if the precautions (removal of power supply ripple, separation of ground and board noise) are insufficient in analog circuits, these are the forms of high-frequency pseudo-noise signals. (When high interference frequency f _interf ≒ avi_clk), thin diagonal stripe and line format (when 1/2 avi_clk ≥ f _interf ≥ f _horizontal ), or whether the luminance appearing horizontally at low frequency is lower than the surroundings Or it is visually _{recognized in} the form of a high stripe (f _horizontal ≧ f _interf ≧ f _vertical ).

  The appearance of visible interference on the screen (panel) depends on the frequency set in the control chip 800 in relation to the input clock, where each input format (active area, blanking, etc.) plays an important role. Fulfill.

  FIG. 10A shows an example of such an interference pattern, which simulates an LCD control unit having a screen interface based on the C model. The waveform of the interference pattern shown in FIG. 10A almost coincides with the waveform observed by the actual LCD control unit.

  Up to this point, only the LCD control unit with only one screen interface has been considered. However, there is also an LCD control unit that further includes a memory interface 814, as described with respect to FIG. In principle, the same considerations apply as above, but in an LCD control unit with external memory, in addition to the screen interface, there is a fairly powerful driver input / output on the control chip 800 for the memory interface. . The powerful drivers provided for these memory interfaces are of considerable importance for consideration because of their impact on the board. Usually, the clock of data passing through the memory interface is different from the clock at the screen interface and is usually higher than the clock at the screen interface. As in the screen interface, a very steep signal (large di / dt) can cause an induced voltage to pass through the bonding wire, couple to the substrate, and affect analog circuitry therefrom. Thus, in reality, there is a frequency mix of at least two frequencies on the board, which are in the same range as the input frequency avi_clk of the signal of the input source 802 under consideration.

Although both frequencies are considered independently, as seen in FIG. 10B, superposition of two interference patterns can also occur. Here, only the fundamental frequency is considered, and the harmonic part that itself causes another interference pattern is not considered.

Hereinafter, the formation of the interference pattern will be discussed in more detail with reference to FIGS. 10A and 10B. The formation of the interference pattern is based on the following simplified mechanism. Starting from the real XGA input mode (XGA = extended graphics adapter), the resulting interference pattern is derived numerically by examining the set pixel frequency (only the fundamental frequency) and illustrated graphically. The following conditions are assumed for the following examination.
Input mode:
XGA 1024 × 768 system clock 78.75 MHz, sweep speed 75 Hz
Horizontal back porch: 176 pixels Horizontal front porch: 112 pixels Vertical back porch: 28 lines Vertical front porch: 4 lines Screen settings:
XGA 1024 × 768
Pixel frequency: 66 MHz

From here, the interference frequency f _interf is
f _interf = 78.75MHz-66MHz = 12.75MHz
Is calculated.

From there, the number of interferences per analog video input line (active area + blanking) can be calculated,
Interference / line = (78.75 / 12.75) ⁻¹ * 1312 = 212.4190
Is brought about.

Therefore, the maximum / minimum of interference is
l _interf = 1313 / 212.4190. . . = 6.1764. . . Pixels and
t _interf = (78.75 MHz) ⁻¹ * 6.1764. . . = 78.4313. . . ns
It occurs periodically at intervals.

If the start point t = 0s is selected for the first frame (frame; f = 1) and the first line (n = 1), the maximum / minimum of the first interference is the sixth and seventh. Visible between pixels and after 78.4313 ns, respectively, and periodically from there to the end of the line (at _tinterf ). Usually, the interference period does not match the input line as an integer, so there is a remainder at the end of each line. Therefore, the difference between the next integer and (interference / line) * n is the starting value for the next line n + 1. An oblique linear pattern is formed by the deviation of the start value of each line, and the following relationship applies.
(Interference / line) remainder <0.5-> diagonal stripes \\\\\
(Interference / line) remainder>0.5-> diagonal stripes /////

The value after the decimal point of (interference / line) * n _max accumulated in the last line determines the starting value of interference in the following frame (f + 1), often above or below the diagonal line. Shift occurs. The result is a moving diagonal line that moves across the original image in one direction, depending on the vertical frequency of the screen. At a fixed frequency ratio, the apparent speed in this direction of movement is constant and depends only on the interference frequency at the analog video input and the waveform of the input signal.

  The above description regarding the interference pattern is summarized again with reference to FIG. In particular, the determination of starting values for subsequent lines and subsequent frames is shown.

In reality, in addition to the above, in addition to all the harmonic parts, all the components of the control chip, as well as the dynamic behavior of external elements such as phase locked loops and input signal sources on the control chip The mechanism of interference formation is even more complex because plays an important role. However, in principle, the generated interference can be calculated in the same way as described above.

The correlated interference pattern generated on the screen by the above mechanism is visible to the user / viewer and is therefore interference.

  It is an object of the present invention to provide a method and a control unit that can prevent visible interference on the screen.

  This object is achieved by a method according to claim 1 and an apparatus according to claim 9.

  The present invention is a method for reducing an interference pattern in displaying an image on a screen having a pixel frequency, wherein the image can be represented by pixel data supplied to the screen by a control unit, and the generation of the pixel data A method comprising changing one or several of the clock signals used in generating the pixel data.

  According to one embodiment, the present invention is a method for reducing interference patterns in the display of an image on a screen having a pixel frequency, the image being supplied to the screen by a control unit. And a method of changing the pixel frequency when the pixel data is generated.

  Furthermore, the present invention provides a control unit for controlling a screen operating at a pixel frequency and displaying an image with reduced interference patterns on the screen. The control unit is an input for receiving image data and processing means for processing the received image data to generate pixel data, which is used to generate the pixel data when generating the pixel data. Processing means for changing one or several of the clock signals to be output and an output for supplying the pixel data for display.

  According to one embodiment, the present invention further provides a control unit for controlling a screen operating at a pixel frequency and displaying an image with reduced interference patterns on the screen. The control unit includes an input for receiving image data, and processing means for processing the received image data to generate pixel data, wherein the pixel frequency is changed when the pixel data is generated. Means and an output for supplying the pixel data for display.

  The method of the present invention and the control unit of the present invention manipulate the clock ratio on the control chip, which eliminates typical interference patterns and is therefore almost invisible.

  The present invention is based on the finding that a fixed frequency ratio and a fixed input signal waveform are responsible for the formation of interference patterns and interference images, respectively. Where the proper design of analog components alone can no longer avoid visible interference, the frequency ratio on the chip is the starting point for solving problems with interference images.

  In general, the inventive approach is characterized by eliminating the correlation and fixed ratio between the frequencies used, respectively, resulting in a regular interference pattern in one frame or in subsequent frames. It becomes impossible. According to a preferred embodiment, the correlation between frequencies and the elimination of fixed ratios are each performed by time-dependent frequency modulation.

  This typically causes interference between 1-5 LSB (LSB = Least Significant Bit), but is only visible to the human eye as a slight random noise in the image, Therefore, it is much less troublesome.

  According to the first embodiment, time-dependent frequency modulation (FM) is realized by frequency modulation executed in a time-continuous manner. According to another embodiment, time-dependent frequency modulation is realized by frequency modulation performed in a time-discrete manner.

  According to a second preferred embodiment, the frequency modulation for the control chip is performed by an external frequency source, or according to a further embodiment, performed by an internal frequency source implemented on the chip. Is done.

  According to a third preferred embodiment, the frequency modulation is performed by spread spectrum phase locked loops.

  Preferred developments of the invention are defined in the dependent claims.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
(A)-(C) are figures which show the example of the time-continuous modulation function g (t). (A)-(C) are figures which show the example of the time discrete modulation function g (k). It is the block diagram which showed the clock generation in the control chip for screens. 1 is a block diagram of a control unit according to a first embodiment of the invention with external frequency modulation. FIG. 2 is a control unit according to a second embodiment of the invention with internal frequency modulation. FIG. 6 is a diagram showing a frequency response in a spread spectrum phase locked loop. It is a figure which shows the example of the interference pattern in an LCD control unit provided with a memory interface and a screen interface. It is a block diagram of a well-known LCD control unit. FIG. 9 is an equivalent diagram of a screen interface of the LCD control unit of FIG. 8. (A) is a figure which shows the interference pattern of an LCD control unit provided with a screen interface, (B) is a figure which shows the interference pattern of an LCD control unit provided with a screen interface and a memory interface. It is a figure for demonstrating formation of an interference pattern.

  In the following description of the preferred embodiment, identical or apparently identical or similar elements are provided with the same reference numerals in the drawings.

  Based on the simplified model of interference formation, the method, method and apparatus of the present invention that can avoid or suppress the formation of visible interference will be described below.

  Here, the methods, techniques and apparatus described below should be taken to reduce the sensitivity to noise and undesirable substrate and mass voltages in the analog circuit portion and the entire system (printed circuit board, chip, application). It should be noted that it is considered as an additional measure to the countermeasure. Therefore, the present invention is preferably applied to a system that has already been fully developed and whose behavior of analog operation is relatively insensitive to interference.

  As already mentioned, according to a preferred embodiment of the present invention, the change in pixel frequency to avoid the interference pattern is achieved by implementing time-dependent frequency modulation (FM), which is time-dependent. The type of frequency modulation eliminates the correlation between the frequencies and the fixed ratio, respectively, so that the interference pattern when combined with the interference frequency is reduced or suppressed.

According to the first embodiment, the time-dependent frequency modulation passes through the frequency range Δf at an appropriate speed, and the modulation function g around the fundamental frequency (f ₀ ) required by the screen and the memory, respectively. Realized by time-continuous frequency modulation, such as the function of a frequency wobbler fixed by (t).

Assuming that the required clock signal is generated on the control chip by a phase locked loop (PLL), for the input frequency f _{xpllin (t)} of the phase locked loop, the following holds: f _{xpllin (t)} = f ₀ + Δf * g (t)
Here, f ₀ is the fundamental frequency (pixel frequency) of the screen or the fundamental frequency of the memory, Δf is a frequency range around the fundamental frequency, and g (t) is a modulation function.

  The modulation function g (t) may be any continuous function, such as the functions shown in FIGS. 1A to 1C, for example, and is generally not limited with respect to the formation and implementation of the function used.

  When the frequency modulation described here is time continuous, the resulting interference pattern varies continuously within each line and thus within each frame, and the function g (t) and the parameter Δf are appropriately defined. Sometimes, it is possible to generate a wide (pseudo) noise having no apparent correlation from the initial correlated interference pattern.

  In another preferred embodiment of the invention, a simpler, time discrete frequency modulation is used instead of the above technique for time continuous frequency modulation, which is generally quite expensive. Although this method yields similar results, it is believed that there are significant advantages in terms of realization.

In this embodiment, the frequency f _{xpllin (k)} to be modulated does not change continuously, but changes in units of frames or lines depending on the implementation. Furthermore, any decision in time can be selected. Similar to time-continuous frequency modulation, a suitable random generator can change the frequency continuously or arbitrarily and irregularly, making “white” (pseudo) noise more effective It is possible to generate.

In this embodiment, the following holds for the input frequency of the phase-locked loop mechanism.
f _{xpllin (t)} = f ₀ + Δf * g (k)
here,
f ₀ is the fundamental frequency of the screen (pixel frequency) or the fundamental frequency of the memory;
Δf is the frequency range around the fundamental frequency,
g (k) is a time discrete modulation function;
k is a run index.

  The run index k is 1 every time a line or frame change, meaning that a new line or new frame has been reached, or a similar phenomenon occurs, and a predetermined condition for frequency change is met. Increase by increments. 2A to 2C show examples of the time discrete modulation frequency g (k), but it should be noted that there is generally no restriction on the discrete function used. Is a point.

  Similar to the first embodiment, by appropriately selecting the function g (k), the modulation condition and the parameter Δf, “white” (pseudo) noise is produced, which is not visible in the best case, Or it is only faintly visible.

  It should be noted that in general with respect to the above embodiments, both of the above methods for producing time-dependent frequency modulation can be used very flexibly by appropriate determination of the modulation conditions, The method can be adapted to the various environmental conditions required by the multiple possible input modes and input frequencies.

  In the following, the generation and distribution of the clock signal at the control chip as described with respect to FIG. 8 will be described in more detail, and then, based on this discussion, an implementation for implementing the method of the present invention on the control chip of the LCD screen. A form is demonstrated.

FIG. 3 shows a block diagram of units required for clock generation on the control chip. As can be seen from the schematic diagram of FIG. 3, the illustrated switching elements are used to generate the memory clock mpll_clk as well as the pixel clock ppll_clk. The circuit has a multiplexer 100 that receives a horizontal synchronization signal HS (H-Sync) at a first input. Multiplexer 100 receives an external oscillator clock sys_clk at a second input. The multiplexer selects one of the two inputs as an input signal for generating the pixel clock ppll_clk based on the drive signal. The output signal selected by the multiplexer 100 is supplied to the pre-divider 104 (n _prediv ) via the wiring 102, and the output signal generated by the pre-divider 104 is separated. Is supplied to the input of the phase-locked loop 108 through the wiring 106, and the phase-locked loop 108 outputs the pixel clock ppll_clk under the control of the internal divider 110 (n _div ). Further, the external oscillator clock sys_clk is supplied to another pre-frequency divider 112 (n _prediv ), and this frequency divider 112 outputs an output signal to the phase-locked loop 116 via the wiring 114. The phase lock loop 116 is driven by the internal control 118 (n _div ), and outputs a memory clock mpll_clk at its output.

  Further, FIG. 3 shows that the clock rclk for operating the configuration register shown in FIG. 8 is the same as the system clock, that is, the external oscillator clock sys_clk.

  The input clock avi_clk is also generated from the horizontal synchronization signal HS via a further phase lock loop 120 and a downstream phase delay loop 122, which is also supplied to the sampler 124 for AVI signal acquisition and digital conversion. It is shown.

  The schematic circuit diagram shown in FIG. 3 is a control unit for clock generation in an LCD control chip with an external memory, which typically has at least four different clocks (clock domains) that are mutually connected. It has a relationship with a predetermined temporal deviation. Further, FIG. 3 shows a configuration for clock generation, which is also shown in the configuration and application described later.

  In FIG. 3, the four clocks and their generation are outlined and all other phase locked loops except the phase locked loop 108 (llpll) which can use the horizontal sync signal HS of the analog video input AVI as the input signal. Is driven by an external oscillator clock sys_clk.

  The clock rclk used for the control chip 800 registers is not critical. This is because this clock is usually the same as the external clock (rclk = sys_clk), and the register is static in normal operation, so it has no visible or measurable effect on the analog circuitry of the chip.

  On the other hand, the situation of the memory clock mpll_clk and the screen clock (pixel clock) ppll_clk generated from the related phase lock loops 108 and 116 (ppll, mpll) is different from the above. Not only are these clock signals driving the very large digital blocks of the LCD control chip, but each input / output interface, ie the memory interface and the screen interface, is also driven by these clock signals. An external oscillator clock can be used as an input signal in both phase-locked loops, and the clock signal is set to the desired frequency at the output by programming pre-dividers 104, 112 and inner loop dividers 110, 118 it can. In the phase lock loop for the screen, the H-Sync signal of the selected input, ie the analog video input signal HS in the illustrated embodiment, can be used as the input signal instead of the external clock sys_clk. .

  Starting from the system configuration shown in FIG. 3, two preferred embodiments for realizing the above method of pseudo-eliminating clock correlation will be described below. Those skilled in the art will appreciate that other configurations are possible in addition to those described below.

  With reference to FIG. 3, a first embodiment in which a frequency-modulated system clock is supplied from an external source will be described. FIG. 4 shows a part for generating the pixel clock ppll_clk and the memory clock mpll_clk among the circuit elements shown in FIG. 3, and the system clock sys_clk supplied from the outside in order to realize the method of the present invention. Is selected as the input signal to the phase locked loop 108 that generates the pixel clock, and for simplicity, the multiplexer 100 shown in FIG. 3 is omitted in FIG.

As can be seen from FIG. 4, instead of the external crystal or crystal oscillator 126 used in conventional LCD control chips, a sweep generator (Wobbel Generator) 128 is used here to supply the system clock sys_clk. ing. This is indicated by the _{disconnection} between the crystal oscillator 126 and the pre-dividers 104, 112 (n _prediv ) at 130. The embodiment shown in FIG. 4 is a simple implementation of the present invention in which an external frequency generator 128, such as the Stanford DG245 model, is used instead of the commonly used crystal oscillator 126. Instead of a crystal oscillator, it is arranged on a printed circuit board which is used and on which a control chip for driving the screen is arranged. If the frequency generator 128 is set to generate a frequency modulated signal such that it corresponds to the method embodiment of the invention described above, this frequency modulated output signal of the generator 128. Can be used as the input signal and system clock sys_clk for each of the phase locked loops 108 and 116. By carefully selecting the parameters, the correlation of the analog input signal to the sample clock (avi_clk) can be pseudo-excluded for the clock signals ppl_clk and mpl_clk generated by the phase-locked loops 108 and 116 (ppll, mpl). realizable.

  The system boundaries of the parameters to be selected depend on the one hand on the dynamic phase characteristics of the phase-locked loops 108 and 116 and on the other hand on the frequency tolerance of the connected unit, ie the connected screen and memory. doing. This means that even if the frequency is shifted to the maximum by frequency modulation, a safe data transmission to the connected unit must be ensured. Moreover, in strong frequency modulation, limit control applied to the synthesis of digital blocks must be considered to avoid timing problems at the interface within the block and especially between clocks (clock domains).

  The determination of parameters to be selected for frequency modulation is theoretically very expensive. This is because, in reality, not only the fundamental frequency, but also the harmonic characteristics of all the harmonic parts and all the components are overlapped, resulting in complicated behavior in terms of time and frequency. They can be determined theoretically, but the parameters for frequency modulation are preferably determined experimentally for all input mode / application combinations. Based on the value determined in this way, the setting is executed according to the required mode.

  The embodiment just described above gives good results with an external frequency generator, but the disadvantage of this embodiment is that the cost and labor for connecting the external frequency generator is too great. Recent applications do not require the use of an external frequency generator, and in practice a simplified programmable / initializable generator can be used on a printed circuit board. But this is a possible but uneconomical solution.

  Thus, according to a second embodiment of the invention for carrying out the method of the invention, a frequency-modulated system clock is generated internally, i.e. in the control unit, i.e. on a chip. FIG. 5 shows a circuit for generating the frequency modulation internally. As can be seen, a conventional external crystal oscillator 126 located on the circuit board is used to supply the system clock sys_clk to the control chip. In addition to the elements already described, a frequency divider controller 132 is provided which is connected to the first pre-frequency divider 104 via the first control bus 134 and to the second pre-range via the second control bus 136. It is connected to the frequency divider 112, connected to the first feedback frequency divider 110 via the third control bus 138, and further connected to the second feedback frequency divider 118 via the fourth control bus 140.

  The embodiment shown in FIG. 5 is an embodiment of correlation elimination by “on-chip” frequency modulation, which is more sophisticated and technically easier to implement than the embodiment described with respect to FIG. . The starting points for frequency modulation according to this embodiment are pre-dividers 104 and 112 and feedback dividers 110 and 118 used in phase-locked loops 108 and 116, respectively. The respective divider values of the pre-dividers 104 and 112 and the feedback divider are under the control of the divider control 132 to obtain the above-described temporal and frequency behavior using an appropriate algorithm or Varies with a programmable pseudo-random number generator. In the embodiment shown in FIG. 5, divider control 132 includes sample control, a programmable counter / divider, and a random number generator.

In order to obtain good results of frequency modulation, the accuracy of the _prescalers 104, 112 (n _prediv ) is important, so that the minimum frequency step Δf _step to be set is the phase lock loop 108, Note that it is converted upward by 116 feedback dividers 110, 118 (n _div ). With respect to the amount of frequency steps that can be effectively obtained in each of the pixel clock ppll_clk and the memory clock mpll_clk, the following holds true for the same circuit structure.
Δf _step = Δf _n * n _div / n _prediv
Here, for example,
n _div = 2 ⁰
n _prediv = 2 ¹⁶
From which the minimum Δf _step results.

One problem with changing frequency dividers is in principle that they are programmed to some predetermined termination value and provide an output pulse when this termination value (threshold) is reached. It is a point that it is a counter. Therefore, reprogramming and accompanying modulation of the input frequency of the phase-locked loop can only be performed when the counter overflows. Due to the dynamic behavior of the phase-locked loop, the time-continuous changes of the output clock signal and the output frequencies mpll_clk and ppll_clk occur somewhat. For this reason, it is not necessary to realize a high resolution in the step width Δf _step . This is because the phase locked loop continuously sweeps these intermediate ranges.

  The second embodiment for implementing the method of the invention is much easier to implement than with an externally generated frequency modulation signal, but the temporal behavior of the phase-locked loop is again determined. It becomes a factor. Since the pre-divider already exists in existing circuits and designs, the method of the present invention can be implemented and verified with little effort (divider logic and control).

  A third preferred embodiment for realizing the frequency modulation required for correlation elimination is to use another phase locked loop concept. So-called spread spectrum phase-locked loops are used in similar applications to improve EMC / EMI (EMC = electromagnetic compatibility, EMI-minimization, EMI = electromagnetic interference). Appropriate adjustment of the phase-locked loops and their control parameters (linear, function or random) eliminates the correlation between clocks to avoid visible interference and has a positive impact on EMC / EMI behavior Can bring.

  FIG. 6 shows the difference between a normal phase locked loop (normal PLL) and a spread spectrum phase locked loop (spread spectrum PLL). As can be seen, the spread spectrum PLL, in contrast to a normal PLL, produces an output signal that spans a predetermined frequency range, while a normal PLL only produces a single output frequency depending on the input frequency. Supply. Thus, the inventive method for eliminating the correlation between the clock signals already described in detail can be implemented here as well.

  Hereinafter, the experimental result of correlation elimination of the clock signal executed based on the first embodiment for implementing the method by supplying the frequency-modulated signal from the outside will be described in more detail.

  For the analysis of the occurrence of interference in the LCD control unit, in particular a control unit such as, for example, SAA 6714, which can store data in a memory and statistically evaluate them is suitable. Accordingly, in the following, each test facility will be described first, followed by the results of correlation elimination obtained by external supply of a frequency-modulated system clock.

The test equipment used the following equipment and parts.
As a system clock generator, Stanford Research Systems' DS345 type synthesis function generator As an AVI signal source, Quantum Data's 801GD type video test generator SAA6714 evaluation board “Early Dragon”, version 1.2, using SAA6714A • LG Philips 18-inch panel, LM181E1, SXGA resolution • Deutronic power supply, 12V / 5A DTP60 type The following settings and parameters were selected.
input:
Quantum Data Test Generator Format: 83 = DMT1260
Image: 43 = 45Flat27
Resolution: 1280x1024
Clock generation:
Stanford Research Systems Synthetic Function Generator Fundamental Frequency: 25,000,005.000Hz (25.000005MHz)

  In the Stanford Research generator, the frequency can be set in units of Hz, so that a special case where the interference pattern does not move can be created, and statistical evaluation can be made without caching in the memory. When a system clock is generated by a crystal oscillator during normal operation, the generation and type of interference lines are highly dependent on the temperature and aging of the crystal oscillator, manufacturing tolerances, and the like.

  The LCD control behavior described with respect to FIG. 8 was tested. Here, the output of the external frequency generator functions as a reference signal of the memory clock and the screen clock (pixel clock) as described above. Frequency modulation in the external generator results in respective frequency modulation of the memory clock and stream clock determined by the dynamic behavior of each phase-locked loop.

  FIG. 7 shows a part of a screen printout obtained by freezing an image in the external memory of the LCD scaler and reading this memory area. Since the interference lines are hardly visible in the printout of the document, three of them were highlighted with white lines for purposes of illustration.

  In contrast to the discrete model already described, in fact, a strong dependence of the interference pattern was seen even within small frequency changes. Different interference patterns can be seen with only a few hertz changes in input frequency.

The following table shows some settings as well as corresponding interference line configurations.

  By using correlation elimination with a frequency-modulated system clock instead of a crystal oscillator on a printed circuit board, the interference pattern shown in FIG. 7 can be “invisible” to the human eye. is there. Thus, the determinant for the desired effect is a combination of interference frequency, interference line diversion due to frequency modulation, and vertical refresh rate.

  As an example, consider an interference pattern generated with a system clock of 25,000,004 Hz. When the sweep speed is 25 Hz, the swept frequency range is 7777 Hz, and the sine function is selected as the modulation frequency g (t), the interference line is no longer visible to the human eye due to such a function generator setting. Very good results have been achieved.

  The method of the present invention is preferably performed using random modulation because the frequency modulation itself can generate new and complex interference patterns. Since this behavior is expected mainly in a continuous modulation function, random modulation is a more preferred variant of frequency modulation from the results of simulations with discrete models.

  According to the present invention, it is possible to effectively reduce the occurrence of interference in the LCD control unit and to make it invisible by pseudo-excluding the correlation of clock signals as described above. Is shown.

  Technical implementation is possible with relatively little effort, but the effective use of this method ensures that this method works reliably and that there are no problems with external components (memory and screen). In order to do so, the appropriate parameters must be established in various ways.

  The preferred embodiment of the present invention has been described in detail above, in which visible interference is avoided by changing the pixel frequency when generating pixel data. However, the present invention is not limited to this.

  In general, all interfering signals on the second board chip can be manipulated in the same way as the signals ppll and mpl, so the present invention is not limited to these clock signals and is widely applicable to all clock signals Is possible.

Claims (15)

A method for reducing interference patterns in the display of an image on a screen having a pixel frequency (ppll_clk), wherein the image can be represented by pixel data supplied to the screen by a control unit (800). ,
Changing the one or more of the clock signals used to generate the pixel data during the generation of the pixel data.   The method according to claim 1, further comprising changing the pixel frequency (ppll_clk) when generating the pixel data.   The method according to claim 1 or 2, wherein the step of changing the pixel frequency (ppll_clk) includes time-dependent frequency modulation (FM).   The method of claim 3, wherein the pixel data comprises a plurality of portions, and the time-dependent frequency modulation (FM) is performed time-continuously over the portions of the pixel data.   The pixel data is composed of a plurality of portions, and the time-dependent frequency modulation (FM) is performed in a time-discrete manner over the portions of the pixel data, and a change in the frequency (ppll_clk) is performed for each change in the portions. 4. The method of claim 3, wherein: The control unit includes means (108) for generating the pixel frequency (ppll_clk) in response to an input frequency (sys_clk) input;
6. The method according to claim 1, wherein the step of changing the pixel frequency (ppll_clk) includes the step of changing the input frequency (sys_clk).   Method according to claim 6, characterized in that the input frequency (sys_clk) is supplied by an external frequency source (128) or a frequency source (132) internal to the control unit (800). The control unit comprises a memory interface (814) driven by a drive signal having a memory frequency (mpll_clk), and means (116) for generating a memory frequency (mpll_clk),
The input frequency (sys_clk) of the means (108) for generating the pixel frequency (ppll_clk) is further input to the means (116) for generating the memory frequency (mpll_clk). Item 8. The method according to Item 6 or 7.   9. A method according to any one of claims 6 to 8, wherein the means for generating the pixel frequency (ppll_clk) comprises a spread spectrum phase locked loop. A control unit for controlling a screen operating at a pixel frequency (ppll_clk) and displaying an image with a reduced interference pattern on the screen,
Inputs (802, 804, 806) for receiving image data;
Processing means (812) for processing the received image data to generate pixel data, wherein one or several clock signals used to generate the pixel data are generated when generating the pixel data; Processing means (812) to change;
An output (818) for supplying the pixel data for display;
A control unit comprising:   11. The control unit according to claim 10, wherein the processing means (812) changes the pixel frequency (ppll_clk) when generating the pixel data.   12. The processing means (812) according to claim 10 or 11, comprising a pixel frequency generator (108) for generating the pixel frequency (ppll_clk) in response to a changing input frequency signal (sys_clk). Controller unit.   The changing input frequency signal is supplied by an external signal source (128) or by an internal frequency control means (134) based on a constant frequency signal from the outside. Item 13. The control unit according to Item 12.   The processing unit includes a memory frequency generator (116) for generating a memory frequency (mpll_clk) for a drive signal for a memory interface (814) based on the input frequency signal (sys_clk). The control unit according to 12 or 13.   15. A control unit according to any one of claims 12 to 14, wherein the pixel frequency generator comprises a spread spectrum phase locked loop.

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