KR102290414B1 - Driving Unit And Display Device Including The Same - Google Patents

Abstract

The present invention includes: a timing control unit for generating a completion signal corresponding to completion of reading and application of a set value for FPGA, and generating a data control signal and image data by using an image signal and a plurality of timing signals; a data driver for generating a data voltage by using the data control signal and the image data; There is provided a driving unit for a display device including a power supply unit for supplying analog power to the data driving unit after the generation of the completion signal. By supplying an analog voltage to the data driving unit after a normal signal is output, defects in the data driving unit are prevented and reliability This is improved.

Description

Driving Unit And Display Device Including The Same

The present invention relates to a driving unit, and more particularly, to a driving unit supplying analog power after a normal operation of a timing control unit by digital power and a display device including the same.

Recently, as society enters the information age in earnest, the field of display that processes and displays a large amount of information has developed rapidly. , Examples of the flat panel display device include a liquid crystal display device (LCD device), an organic light emitting diode display device (OLED device), a plasma display panel device (PDP device), and the like. can be heard

The display device includes a display panel for displaying an image, and a driver for supplying signals and power to the display panel, and the driver includes a gate driver and a data driver for supplying a gate voltage and a data voltage to each pixel region of the display panel, respectively. and a timing controller for transmitting a plurality of control signals and image data to the gate driver and data driver, and a power supply for supplying power to the gate driver, data driver, and timing controller.

Here, the power supply unit supplies digital power to the timing controller using the supplied external power, and supplies analog power to the gate driver and the data driver.

In general, the timing controller is configured in the form of an application specific integrated circuit (ASIC), which is an application specific integrated circuit (ASIC), which has an advantage of relatively low cost, but has a disadvantage in that a completed design cannot be changed. Accordingly, the timing control unit is configured with a field programmable gate array (FPGA) in the development stage or the initial stage of mass production of a display device, where design changes often occur.

FPGA is a kind of programmable logic device (PLD). It is an integrated circuit that can reset the internal logic circuit structure. It includes a logic element and a programmable connection line connecting the logic element.

Developers can configure the timing control unit by setting complex circuits with various functions by connecting logic elements of the FPGA as desired through programming, and can configure the timing control unit with a design change by resetting the circuit by software through programming.

The timing control unit composed of ASIC has all logic elements and connection lines fixed, so it takes several hundred milliseconds (msec) to output a normal signal after power is applied, but the timing control unit composed of FPGA sets the logic element and connection line Since the value must be read and applied from the storage unit, it takes several seconds (sec) to output a normal signal after power is applied, and an abnormal signal in hi_z state is output from the timing controller until the normal signal is output.

This abnormal signal is input to the data controller to which the analog power is supplied and causes burnt or malfunction of the data controller, which will be described with reference to the drawings.

1 is a waveform diagram illustrating a power sequence of a display device including a timing controller of a conventional FPGA.

As shown in FIG. 1 , in a conventional display device, a digital high potential voltage VCC is supplied to the timing controller at a first time point t1 by a power supply unit, and an analog high potential voltage VCC at a second time point t2 is supplied. (VDD) and gamma voltage Gamma are supplied to the data driver, and at a third time point t3 , the analog half-high potential voltage HVDD is supplied to the data driver.

Then, the timing controller outputs a normal source output enable (SOE) after the fourth time point t4.

For example, the interval between the first and second time points t1 and t2 may be in the range of about 0 seconds to about 2 seconds, and the interval between the second and third time points t2 and t3 is about 0.1 second to about 1 second, and the interval between the first and fourth time points t1 and t4 may be within the range of about 2 seconds to about 6 seconds.

Although not shown, when the timing control unit is configured as an ASIC, the normal SOE is output from the timing control unit within several hundred milliseconds (msec) after the first time point t1 when the digital high potential voltage (VCC) is supplied to the data driver. Since it is input, the normal SOE is input to the data driver before or immediately after the second time t2 when the analog high potential voltage VDD and the gamma voltage Gamma are supplied, so that combustion or malfunction of the data driver does not occur.

However, when the timing control unit is configured as an FPGA, the time for reading and applying the FPGA set value from the timing control unit to the normal SOE output after the first time point (t1) when the digital high potential voltage (VCC) is supplied, e.g. For example, it takes a time within the range of about 2 seconds to about 6 seconds, and before the fourth time point t4, an abnormal SOE of the hi_z state is output.

Accordingly, an abnormal SOE is input to the data driver from the second time point t2 when the analog high potential voltage VDD and the gamma voltage Gmma are supplied to the fourth time point t4, and the data driver receives the abnormal SOE. There is a problem in that the combustion or malfunction occurs.

In FIG. 1, SOE is mentioned as an example of the data control signal output from the timing controller. However, in the case of other data control signals and image data, the analog high potential voltage (VDD) and the gamma voltage (Gmma) are supplied at the second time point ( After t2) until the fourth time point (t4), there is a problem that an abnormal signal is output from the timing controller and input to the data driver. includes a control bit.

In addition, such a problem may occur at any time in a development model using an FPGA or an initial mass production model, and there is a problem of causing an increase in manufacturing cost and a decrease in reliability due to replacement of a driving integrated circuit that is a data driving unit.

The present invention has been proposed to solve this problem, and by supplying analog power to the data driver after the normal operation of the timing controller of the FPGA by digital power supply, damage to the data driver by the abnormal signal of the timing controller is prevented and reliability is improved. An object of the present invention is to provide an improved driving unit and a display device including the same.

In addition, the present invention provides an analog power supply to the data driving unit using a completion signal corresponding to the completion of the setting of the timing control unit of the FPGA, thereby preventing damage to the data driving unit and improving reliability without adding or changing components, and a driving unit and the same It is another object to provide a display device comprising.

In order to solve the above problems, the present invention generates a completion signal corresponding to the completion of reading and application of a set value for FPGA, and a timing for generating a data control signal and image data using an image signal and a plurality of timing signals a control unit; a data driver for generating a data voltage by using the data control signal and the image data; A driving unit for a display device including a power supply unit for supplying analog power to the data driving unit after the generation of the completion signal is provided.

And, at a first time point, the power supply unit supplies digital power to the timing control unit, and at a second time point after the first time point, the timing control unit generates the completion signal and supplies it to the power supply unit, At a third time point after the second time point, the power supply unit may supply the analog power to the data driver.

In addition, the timing control unit outputs the abnormal data control signal and the image data in a section between the first and second time points, and outputs the data control signal and the image data that are normal in a section after the second time point. can be printed out.

And, the digital power supply includes a digital high potential voltage, the analog power supply includes an analog high potential voltage, a gamma voltage, an analog semi-high potential voltage, and a first common voltage, and the data control signal is a source output enable; It may include a source start pulse and a source sampling clock.

On the other hand, the present invention generates a completion signal corresponding to the completion of reading and application of a set value for FPGA, and a timing control unit for generating a gate control signal, a data control signal and image data by using an image signal and a plurality of timing signals; ; a data driver for generating a data voltage by using the data control signal and the image data; a gate driver for generating a gate voltage by using the gate control signal; a power supply unit for supplying a first analog power to the data driver and a second analog power to the gate driver after the completion signal is generated; and a display panel that displays an image using the gate voltage and the data voltage.

And, at a first time point, the power supply unit supplies digital power to the timing control unit, and at a second time point after the first time point, the timing control unit generates the completion signal and supplies it to the power supply unit, At a third time point after the second time point, the power supply unit may supply the first analog power to the data driver.

In addition, the timing control unit outputs the abnormal data control signal and the image data in a section between the first and second time points, and outputs the data control signal and the image data that are normal in a section after the second time point. can be printed out.

The digital power supply includes a digital high potential voltage, the first analog power supply includes an analog high potential voltage, a gamma voltage, an analog semi-high potential voltage, and a first common voltage, and the second analog power supply includes a gate high voltage , a gate low voltage, and a second common voltage, and the data control signal may include a source output enable, a source start pulse, and a source sampling clock.

According to the present invention, by supplying analog power to the data driver after the normal operation of the timing controller of the FPGA by digital power supply, damage to the data driver due to an abnormal signal of the timing controller is prevented and reliability is improved.

In addition, the present invention supplies analog power to the data driver using the completion signal corresponding to the completion of the setting of the timing control unit of the FPGA, thereby preventing damage to the data driver without adding or changing components, improving reliability, and providing large, high-resolution It has the effect that it is easy to apply to the model.

1 is a waveform diagram illustrating a power sequence of a display device including a timing controller of a conventional FPGA.
2 is a view showing a display device according to an embodiment of the present invention.
3 is a waveform diagram illustrating a power sequence of a display device according to an embodiment of the present invention;

A driving unit and a display device including the same according to the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a display device according to an embodiment of the present invention.

As shown in FIG. 2 , the display device 110 according to the first embodiment of the present invention includes a timing controller 120 , a data driver 130 , a gate driver 140 , a power supply unit 150 , and a display panel. (160).

The timing control unit 120 operates by receiving digital power (DPW) from the power supply unit 150, and includes an image signal (IS) and a data enable signal (DE) transmitted from an external system such as a graphic card or a TV system; A gate control signal (GCS), a data control signal (DCS) and image data (RGB) are generated using a plurality of timing signals such as a horizontal synchronization signal (HSY), a vertical synchronization signal (VSY), and a clock (CLK). , the generated data control signal DCS and image data RGB are supplied to the data driver 130 , and the generated gate control signal GCS is supplied to the gate driver 140 .

For example, the gate control signal GCS includes a gate output enable (GOE), a gate start pulse (GSP), a gate shift clock (GSC), and the like, and includes data The control signal DCS may include a source output enable (SOE), a source start pulse (SSP), a source sampling clock (SSC), and the like.

The timing control unit 120 is configured in the form of a programmable logic device (PLD) such as a field programmable gate array (FPGA). Although not shown, the FPGA is a gate array logic unit including thousands of programmable resettable logic elements; It may include a phase locked loop (PLL) for multiplying an input clock frequency, a data receiving unit, a data transmitting unit, and the like, and the PLL may be initialized according to a reset signal.

After the timing control unit 120 of the FPGA receives the digital power (DPW) from the power supply unit 150, it takes several seconds (sec) to read and apply the set values for the logic element and the connection line from the storage unit. When the reading and application of the set value is completed, the timing control unit 120 of the FPGA generates a completion signal (DONE) corresponding to the completion of reading and applying the set value, and transmits the generated completion signal (DONE) to the power supply unit 150 ) is supplied.

Accordingly, the timing control unit 120 of the FPGA outputs an abnormal data control signal DCS and image data RGB from the supply of the digital power DPW until the completion signal DONE is generated, and the completion signal DONE. ), the normal data control signal DCS and image data RGB are output.

The data driving unit 130 operates by receiving the first analog power APW1 from the power supply unit 150 , and uses the data control signal DCS and the image data RGB supplied from the timing control unit 120 to obtain data. A voltage is generated and the generated data voltage is supplied to the data line DL of the display panel 150 .

The gate driving unit 140 operates by receiving the second analog power APW2 from the power supply unit 150 , and generates and generates a gate voltage using the gate control signal GCS supplied from the timing control unit 120 . The applied gate voltage is supplied to the gate line GL of the display panel 150 .

Each of the data driver 130 and the gate driver 140 is configured in the form of an integrated circuit (IC).

The power supply unit 150 receives external power (EPW) from an external system, and uses the external power (EPW) to generate digital power (DPW), first and second analog power (APW1, APW2), and the generated The digital power supply DPW is supplied to the timing controller 120 , and the generated first and second analog power supplies APW1 and APW2 are supplied to the data driver 130 and the gate driver 140 , respectively.

To this end, the power supply unit 150 includes a digital power supply unit 152 for generating a digital power supply (DPW), and an analog power supply unit 154 for generating first and second analog power sources (APW1, APW2).

Although not shown, the digital power supply unit 152 may include a plurality of buck converters, and the analog power supply unit 154 may include a plurality of boost converters.

The digital power supply DPW includes a digital high potential voltage (or logic power supply) VCC, and the like, and the first analog power supply APW1 is an analog high potential voltage VDD, a gamma voltage Gamma, and an analog semi-high potential voltage ( HVDD), a first common voltage Vcom1, and the like, and the second analog power supply APW2 may include a gate high voltage VGH, a gate low voltage VGL, a second common voltage Vcom2, and the like. For example, the external power supply (EPW) is about 12V, the digital high potential voltage (VCC) is about 3.3V, the analog high potential voltage (VDD) and the gamma voltage (Gamma) are about 16V, and the analog semi-high potential voltage (HVDD) may be about 8V.

At this time, the power supply unit 150 supplies the digital power (DPW) to the timing control unit 120 of the FPGA immediately after supplying the external power (EPW), and based on the completion signal (DONE) supplied from the timing control unit 120 The first analog power supply APW1 is supplied to the data driver 130 .

The display panel 160 displays an image using the data voltage supplied from the data driver 130 and the gate voltage supplied from the gate driver 140 .

To this end, the display panel 160 includes a gate line GL and a data line DL that intersect each other to define the pixel region P, and a thin film transistor ( T) is connected.

Although not shown, a liquid crystal capacitor may be connected to the thin film transistor T when the display device is a liquid crystal display device, and a light emitting diode may be connected to the thin film transistor T when the display device is an organic light emitting diode display device.

In the display panel 160 , the thin film transistor T is turned on according to the high level of the gate voltage of the gate line GL, and the data voltage of the data line DL is the thin film transistor T ) is applied to the liquid crystal capacitor or light emitting diode to display grayscale.

As described above, in the display device 110 according to the embodiment of the present invention, the data driver 130 supplies the first analog power APW1 from the power supply unit 150 after the completion signal DONE of the timing controller 120 is generated. Since the normal data control signal DCS and the image data RGB are output from the timing controller 120 after the completion signal DONE is generated, the abnormal data control signal DCS and the image data RGB are output. ), such as combustion or malfunction of the data driving unit 130, is prevented, the reliability of the driving unit and the display device is improved, and the manufacturing cost is reduced.

The operation of the driving unit for the display device will be described with reference to the drawings.

3 is a waveform diagram illustrating a power sequence of a display device according to an embodiment of the present invention, which will be described with reference to FIG. 3 .

As shown in FIG. 3 , in the display device 110 according to the embodiment of the present invention, the power supply unit 150 timings the digital high potential voltage VCC, which is the digital power source DPW, at a first time point t1 . It is supplied to the control unit 120, and the timing control unit 120 starts the operation.

Thereafter, at the second time point t2 , the timing control unit 120 completes reading and applying the set value of the FPGA to generate a completion signal DONE, and supplies the generated completion signal DONE to the power supply unit 150 . .

Thereafter, at a third time point t3, the power supply unit 150 converts the analog high potential voltage VDD and the gamma voltage Gamma, which are the first analog power sources APW1, to the data driving unit after a predetermined time based on the completion signal DONE. (130).

Thereafter, at the fourth time point t4 , the power supply unit 150 supplies the analog semi-high potential voltage HVDD, which is the first analog power source APW1 , to the data driver 130 after a predetermined time based on the completion signal DONE. .

For example, the interval between the first and second time points t1 and t2 may be in the range of about 2 seconds to about 6 seconds, and the interval between the second and third time points t2 and t3 is about 0 seconds. to about 2 seconds, and the interval between the third and fourth time points t3 and t4 may be within the range of about 0.1 second to about 1 second.

Then, the point at which the digital high potential voltage VCC becomes 70% of the maximum value is set as the first time point t1, and the point at which the completion signal DONE changes from the low level to the high level is set at the second time point t2 ), the point at which the analog high potential voltage (VDD) and the gamma voltage (Gamma) becomes 50% of the maximum value is set as the third time point (t3), and the analog high potential voltage (HVDD) is 50% of the maximum value % may be set as the fourth time point t4.

Here, the timing control unit 120, before the completion of reading and applying the set value of the FPGA, that is, the second time point at which the completion signal DONE is generated from the first time point t1 to which the digital high potential voltage VCC is supplied. Until t2, the abnormal data control signal DCS, that is, the abnormal SOE is output, and after the second time t2 when the completion signal DONE is generated, the normal data control signal DCS, that is, the normal SOE is generated. to output

Accordingly, the data driver 130 receives the analog high potential voltage VDD and gamma from the power supply unit 150 at a third time point t3 after the second time point t2 at which a normal SOE is output from the timing controller 120 . The voltage Gamma is supplied to start operation, and as a result, defects such as combustion or malfunction of the data driver 130 due to abnormal SOE can be prevented, and the reliability of the driver and the display device 110 is improved and displayed. The manufacturing cost of the device 110 is reduced.

In particular, in the case of a new display device having a large size and high resolution, the timing control unit is highly likely to be configured with an FPGA for easy design change. It effectively prevents the failure of the data driving unit due to the abnormal signal of the control unit, and the timing control unit of the FPGA can be easily applied to a large, high-resolution display device.

In FIG. 3 , SOE is mentioned as an example of the data control signal DCS output from the timing controller 120 , but in the case of other data control signals and image data, the second time point t2 at which the completion signal DONE is generated. Although it is output in an abnormal state before, it is output in a normal state after the second time point t2 when the completion signal DONE is generated, so that the failure of the data driver 130 can be prevented.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: display device 120: timing control unit
130: data driving unit 140: gate driving unit
150: power supply 160: display panel

Claims (11)

a timing control unit for generating a completion signal corresponding to completion of reading and application of the set value for FPGA, and generating a data control signal and image data by using the image signal and a plurality of timing signals;
a data driver for generating a data voltage by using the data control signal and the image data;
A power supply unit that supplies analog power to the data driver after the completion signal is generated
including,
At a first time point, the power supply unit supplies digital power to the timing control unit,
At a second time point after the first time point, the timing control unit generates the completion signal and supplies it to the power supply unit,
At a third time point after the second time point, the power supply unit supplies the analog high potential voltage and the gamma voltage of the analog power supply to the data driver,
At a fourth time point after the third time point, the power supply unit supplies the analog semi-high potential voltage of the analog power source to the data driver unit.
delete The method of claim 1,
The timing control unit,
outputting the abnormal data control signal and the image data in a section between the first and second time points;
A driving unit for a display device that outputs the normal data control signal and the image data in a section after the second time point.
4. The method of claim 3,
The digital power source includes a digital high potential voltage,
The analog power source includes the analog high potential voltage, the gamma voltage, the analog half high potential voltage, and a first common voltage,
The data control signal includes a source output enable, a source start pulse, and a source sampling clock.
a timing control unit for generating a completion signal corresponding to completion of reading and application of the set value for FPGA, and generating a gate control signal, a data control signal, and image data using the image signal and a plurality of timing signals;
a data driver for generating a data voltage by using the data control signal and the image data;
a gate driver for generating a gate voltage by using the gate control signal;
a power supply unit for supplying a first analog power to the data driver and a second analog power to the gate driver after the completion signal is generated;
A display panel displaying an image using the gate voltage and the data voltage
including,
At a first time point, the power supply unit supplies digital power to the timing control unit,
At a second time point after the first time point, the timing control unit generates the completion signal and supplies it to the power supply unit,
At a third time point after the second time point, the power supply unit supplies the analog high potential voltage and the gamma voltage of the first analog power supply to the data driver,
At a fourth time point after the third time point, the power supply unit supplies the analog semi-high potential voltage of the first analog power supply to the data driver.
delete 6. The method of claim 5,
The timing control unit,
outputting the abnormal data control signal and the image data in a section between the first and second time points;
A display device configured to output the normal data control signal and the image data in a section after the second time point.
8. The method of claim 7,
The digital power source includes a digital high potential voltage,
The first analog power source includes the analog high potential voltage, the gamma voltage, the analog semi-high potential voltage, and a first common voltage,
The second analog power source includes a gate high voltage, a gate low voltage, and a second common voltage,
The data control signal includes a source output enable, a source start pulse, and a source sampling clock.
The method of claim 1,
The timing control unit is a driving unit for a display device configured in the form of a field programmable gate array (FPGA).
The method of claim 1,
In a section between the first and second time points, the timing controller reads and applies the set value for the FPGA.
The method of claim 1,
The interval between the first and second time points is within the range of 2 seconds to 6 seconds,
The interval between the second and third time points is within the range of 0 seconds to 2 seconds,
An interval between the third and fourth time points is within a range of 0.1 second to 1 second.

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