EP1535274B1 - Control unit and method for reducing interference patterns when an image is displayed on a screen - Google Patents

Description

The present invention relates to a control unit and to a method for controlling a screen, and more particularly to a control unit and to a method of reducing interference patterns when displaying an image on the screen. More particularly, the present invention relates to a method and to a controller for use with a TFT / LCD screen.

Complex systems that use a variety of signals show increasing interactions between digital and analog components as the feature size decreases. This situation has a serious effect on systems which combine several clock signals (clock domains) on one chip and use the similar frequencies for digital data processing and analog data acquisition.

Especially for graphic applications, such interactions show in the form of interference patterns in the output image, which will be explained in more detail below with reference to a TFT / LCD screen (TFT = T out F ilm T Transistor = thin-film transistor; LCD = L iquid C rystal D isplay = liquid crystal display).

. For the connection of TFT / LCD screens to standard video sources (for example, to PC graphics cards: VGA, DVI and parallel ports (PC = P ersonal C omputer; VGA = V ideo G raphics A dapter; DVI = D igital V ideo I nput = digital video input)) LCD control units are needed, which capture the different input data, convert it into digital RGB data (RGB = red, green, blue) and with that of the respective Screen type required time history (pixel frequency) output.

8 shows a simplified block diagram of a conventional LCD control chip 800. The control chip 800 receives input signals from different input sources 802, 804, and 806. This is the schematically illustrated signal source 802, which analog video input signals to provide (AVI = A nalogue V ideo I nput = analog video input). The signal source 804 provides digital video input signals to (DVI = D igital V ideo I nput = digital video input). The signal source 806 provides parallel video input signals to (PVI = P arallel I nput = V ideo parallel video input). The input signals provided to the control chip 800 through the input sources 802 to 806 are applied to an input selection unit 808 which selects the input signals to be processed and provides them to an input 810 of the control chip 800. The signals provided at the input 810 are provided to a processing unit 812, which includes a FIFO memory (FIFO = F irst I n F irst O ut) and comprises a memory element. The processing means 812 associated memory is coupled to a memory interface 814 (MI = M emory I nterface = memory interface). The processing unit 812 outputs via an output 814 and the output interface 816 the pixel data to be displayed on the screen with a pixel frequency ppll_clk to the screen. The control chip 800 further comprises a configuration block 818 which is operated with the system clock sys_clk.

Prior to the processing unit 812, the signals are at the clock fclk, which corresponds to the clock of the input signals detected by the input sources 802 to 806 (DVI_clk, AVI_clk, PVI_clk).

As shown in Fig. 8, are located next to the different clocks (clock domains) of the input sources (AVI_clk, DVI_clk, PVI_clk) on the control chip 800, depending on the type of control unit, additional clocks (domains) for the memory interface 814 (mpll_clk) and the screen interface 818 (ppll_clk). Furthermore, the system clock sys_clk is provided.

The control chip 800 shown in Fig. 8 is disposed on a printed circuit board, for example, and receives e.g. the video or graphics signals provided by a computer for editing and display on the screen.

The problem with such controllers is that the clock signals across the substrate of the control chip 800 couple into one or more inputs of the control chip and overlap with the applied signals. As a result, disturbing interference patterns are generated when displaying the data on the screen. This problem will be clarified below with reference to the signals received at the analog input.

With regard to the various inputs of the control chip 800, it should be noted that, theoretically, the DVI input 804 can also be disturbed via the substrate of the chip from the other clock signals (clock domains), but the following explanations are limited to the analog input 802 for the sake of simplicity (AVI) as a susceptible sink, wherein the memory and the screen clock signals mpll_clk and ppll_clk are considered as a source of interference, which couple via the usually low impedance executed substrate of the control chip 800 in the analog input AVI.

The simplest and in practice often occurring case of interference with LCD control units is the coupling of the interference signal into the analog video input 802 (AVI) with the frequency of the screen clock ppll_clk (pixel frequency) or the harmonic harmonics of this clock. There are several ways in which the interfering signal is generated and into the low-resistance substrate of the chip 800 passes. As the main source of substrate voltages, in addition to the digital logic in the core, the input / output drivers of output interface 818 can be seen.

Referring to Figure 9, an equivalent circuit diagram of the screen interface or output interface 818 of Figure 8 is shown. In the left portion of Fig. 9 (left of the broken line), the elements of the control chip are shown, and on the right of the broken line, the elements of the circuit board are shown.

From the output 816, the interface at a driver stage 822 receives the pixel signals to be displayed on the screen at the pixel frequency of the ppll_clk screen. The driver stage 822 comprises in the illustrated example a first field effect transistor 822a and a second field effect transistor 822b. The output of the driver stage 822 is connected to a pad of the control chip 800, wherein the pad has an impedance with an ohmic component and a capacitive component against the substrate ground, which is indicated in FIG. 9 by the resistor R ₁ and the capacitor C ₁ . The control chip 800 is connected to a housing via a bonding wire in order to connect a connection area of the control chip to a connection area of the chip housing. FIG. 9 shows the inductive component L ₁ and the ohmic component R _{2 of} the impedance of the bonding wire.

In addition, the capacitive, inductive and ohmic components of the impedances of the pad and of the housing, with which the control chip 800 is connected via the bonding wire, are shown as resistor R ₃ , as inductor L ₂ and as capacitances C ₂ and C ₃ .

On the circuit board, a transmission line TL (TL = Transmission Line) is provided which transmits the signal output by the control chip to another driver stage 824 outputs, which in turn forwards the signal to the screen. The driver stage 824 includes, similar to the driver stage 822, a first field effect transistor 824a and a second field effect transistor 824b. Furthermore, a capacity of the housing of the driver stage 824 is illustrated with the capacitance C ₄ .

FIG. 9 also shows the voltage u _L (t) dropping across the inductor L ₁ . As noted above, one of the major sources of substrate voltages is the outputs of the input / output driver stage 822 of the display interface. This interface generates via the inductors L ₁ , L ₂ and the resistors R ₁ , R ₂ , R _{3 of} the bonding wires and the pads very steep signals (high di / dt). As a result, voltages of up to a few 100 mV (u _L (t)) can drop across the bonding wires, which, due to the driver layout, is coupled directly or indirectly to the substrate of the control chip 800.

Another source of disturbance to the analog input of the control chip 800 may be ground or supply voltage bounces caused by little or no decoupling on the control chip in the digital core or by inadequate routing of the power supply lines ) can arise.

The visible effects are very similar in both cases, and with insufficient immunity of the analog circuits (power supply ripple rejection, ground and substrate noise decoupling) these are in the form of high frequency quasi-noise signals (with high interference frequency f _interf ≈ avi_clk), in the form of narrow diagonal stripes and lines (1/2 avi_clk ≥ f _interf ≥ f _horizontal ) or in the form of low frequency horizontally oriented stripes (f _horizontal ≥ f _interf ≥ f _vertical ) with lower or higher brightness.

The appearance of the interference visible on the screen depends on the frequencies set on the control chip 800 in relation to the input clock, whereby the respective input format (active area, blanking, line frequency, etc.) plays an essential role ,

Fig. 10A shows an example of such an interference pattern which has been simulated for a screen interface type LCD control unit based on a C model. The course of the interference pattern shown in FIG. 10A corresponds largely with the course to be observed in a real LCD control unit.

So far, only LCD control units with a screen interface have been considered. In addition, however, there are also LCD control units, as described with reference to FIG. 8, in which additionally the memory interface 814 is provided. In principle, the same considerations apply here as above, but LCD controllers with external memory in addition to the screen interface are still much stronger driver inputs / outputs for the memory interface on the control chip 800. These are intended for the memory interface stronger drivers not least because of their effect on the substrate for the consideration essential. The data on the memory interface are usually clocked at a different, usually higher clock than the screen interface. As with the screen interface, the very steep signals (high di / dt) generate inductive voltages across the bond wires, which can be coupled to the substrate and influence the analog circuits from there. In reality, there is thus a frequency mixture of at least two frequencies on the substrate which are approximately of the same order of magnitude as the input frequency avi_clk of the signal from the considered input source 802.

Considering both frequencies independently, a superposition of two interference patterns as shown in Fig. 10B is possible. Only the fundamental frequencies and not the harmonic frequency components which would lead to a different interference pattern are considered here.

The development of the interference patterns explained above with reference to FIGS. 10A and 10B will be considered in greater detail below. The formation of the interference patterns is based on the simplified mechanism described below. Starting from a real XGA input mode (XGA = e X tended G raphics dapter A) is set in consideration of the pixel frequency (only the fundamental frequency), the resulting interference pattern mathematically derived and plotted. For the following consideration, the following conditions are assumed:

• XGA 1024x768 @ 75 Hz bei 78,75 MHz
• Horizontaler Back-Porch: 176 Pixel
• Horizontaler Front-Porch: 112 Pixel
• Vertikaler Back-Porch: 28 Linien
• Vertikaler Front-Porch: 4 Linien

Input mode:

• XGA 1024x768 @ 75 Hz at 78.75 MHz
• Horizontal back porch: 176 pixels
• Horizontal front porch: 112 pixels
• Vertical back porch: 28 lines
• Vertical front porch: 4 lines

• XGA 1024x768
• Pixelfrequenz: 66 MHz

Screen settings:

• XGA 1024x768
• Pixel frequency: 66 MHz

From this, first the interference _frequency f _{interf is calculated} to: $${\mathrm{f}}_{\mathrm{interf}}\mathrm{=}\mathrm{78}\mathrm{.}\mathrm{75}\mathrm{MHz}\mathrm{-}\mathrm{66}\mathrm{Mhz}\mathrm{=}\mathrm{12}\mathrm{.}\mathrm{75}\mathrm{MHz}\mathrm{,}$$

From this, the number of interferences per input line at the analog video input (active area + blanking) can be calculated, which results in: $$\mathrm{interf}/\mathrm{row}={\left(78.75/12.75\right)}^{-1}*1312=212.4190$$

bzw. $${\mathrm{t}}_{\mathrm{interf}}\mathrm{=}{\mathrm{78}\mathrm{,}\mathrm{75}\mathrm{MHz}}^{-1}*6,1764\dots \mathrm{=}\mathrm{78}\mathrm{,}\mathrm{4313}\mathrm{\dots }\mathrm{ns}$$

auf.A maximum / minimum of the interference thus occurs periodically with a distance of $${\mathrm{l}}_{\mathrm{interf}}\mathrm{=}1312/212.4190...=6.1764...\mathrm{pixel}$$

respectively. $${\mathrm{t}}_{\mathrm{interf}}\mathrm{=}{\mathrm{78}\mathrm{.}\mathrm{75}\mathrm{MHz}}^{-1}*6.1764...\mathrm{=}\mathrm{78}\mathrm{.}\mathrm{4313}\mathrm{...}\mathrm{ns}$$

on.

$$\mathrm{Rest}\left\{\mathrm{interf}/\mathrm{Zeile}\right\}>0,5\Rightarrow \mathrm{diagonale\hspace{1em}Streifen}////////////$$

Assuming that in the first frame (frame; f = 1), first line (n = 1), the starting point t = 0s is selected, the first minimum / maximum of the interference between the sixth and seventh pixels and visible after 78.4313 ns and from there on periodically (with t _interf ) to the end of the line. Since the interference period usually does not fit integer into an input line, a remainder remains at the end of each line. The difference from (interf / line) * n to the next largest integer is then the respective start value for the following line n + 1 of the respective starting value with each line, a diagonal stripe pattern results, wherein: $$\mathrm{rest}\left\{\mathrm{interf}/\mathrm{row}\right\}<0.5\Rightarrow \mathrm{diagonal\; stripes}\setminus \setminus \setminus \setminus \setminus \setminus \setminus \setminus \setminus \setminus \setminus \setminus$$

$$\mathrm{rest}\left\{\mathrm{interf}/\mathrm{row}\right\}>0.5\Rightarrow \mathrm{diagonal\; stripes}////////////$$

The decimal value of (interf / line) * n _max in the last line determines the starting value of the interference in the following frame (f + 1), which makes it possible in most cases Cases to a shift of the diagonal lines up or down comes. The result is, depending on the vertical frequency of the screen, moving diagonal lines, which move in one direction over the output image. At fixed frequency ratios, the apparent speed and direction of this motion is constant, depending only on the interference frequency and timing of the input signal at the analog video input.

The embodiments just described, which have led to the interference pattern, are summarized again graphically with reference to FIG. 11. In particular, the specification of the starting values for the subsequent lines and subsequent frames is clarified.

In reality, the mechanism of interference generation is indeed more complex, because in addition not only all harmonic frequency components, but also the dynamic behavior of all components on the control chip and the external elements, such as the phase locked loops on the control chip, the input signal sources, etc., an important role play, but in principle here also calculate the resulting interference.

The correlated interference patterns generated on the screen due to the mechanisms described above are visible to a user / viewer and therefore disturbing.

US-A-6,046,735 relates to a graphics controller which uses spread-spectrum techniques to modulate a pixel clock over a range of frequencies so as to reduce the maximum intensity of EMI emissions. An EMI suppression circuit includes an EMI FIFO memory and an LCD controller which are clocked by a modulated clock signal, whereas the remaining elements are clocked with an unmodulated video clock. The basic approach to EMI reduction is to use a spread-spectrum technique in which the frequency of the video clock signal used is modulated while transferring pixel data to a flat panel display. This modulation of the clock frequency when transmitting a line to a flat screen reduces the EMI emission that occurs. The modulated frequency is used only to transmit the pixel data of one line, and after transferring the pixel data of one line, the clock modulator is reset so that the subsequent line is read out with exactly the same modulated clock sequence.

The present invention is therefore based on the object to provide a method and a control unit that avoids the visible interference on a screen.

This object is achieved by a method according to claim 1 and by a device according to claim /.

The present invention provides a method of reducing interference patterns when displaying an image on a screen at a pixel frequency, the image being writable by pixel data provided to the screen by a controller based on received image data, the controller having an input for receiving the image data and a plurality of clock signals, wherein one or more of the clock signals coupled via the input to the control unit and superimposed on the image data, the method comprising the following step: during the processing of the image data received on the control unit for display on the screen, varying one or more of the clock signals used in the processing of the image data by a time-dependent frequency modulation,
wherein the time-dependent frequency modulation over a line or a frame of the image data is time-discrete, and the frequency is changed at a line change or a frame change.

The present invention provides a control unit for controlling a screen operating at a pixel frequency for displaying an image on the screen with a reduced interference pattern, the control unit having a plurality of clock signals
an input for receiving image data, wherein via the input one or more of the clock signals is coupled into the control unit and superimposed with the image data;
processing means processing the received image data for display on the screen, wherein the processing means, during processing of the image data, varies one or more of the clock signals used in the processing of the image data by time-dependent frequency modulation; and
an output to provide the processed image data for display,
wherein the time-dependent frequency modulation over a line or a frame of the image data is time-discrete, and
wherein the processing means causes a change in the frequency at a line change or a frame change.

The inventive method and the control unit according to the invention cause a manipulation of the clock conditions on the control chip, whereby typical interference patterns are destroyed and thus made almost invisible.

The present invention is based on the finding that the cause for the formation of the interference pattern or the interference images is a fixed frequency ratio and a fixed input signal time profile. If it is no longer possible to avoid the visible interference by a suitable design of the analog components alone, the frequency ratios on the chip are the starting point for solving the problem in connection with interference images.

Generally speaking, the approach according to the invention is to destroy the correlation or the rigid ratio of the frequencies used, so that no regular interference patterns can occur within a frame or within successive frames. According to a preferred embodiment, this destruction of the correlation or the rigid ratio of the frequencies is effected by a time-dependent frequency modulation.

Here, the interference that typically between 1 to 5 LSB (= LSB L east S ignificant B it = minderwertigstes bit) are, though still exists, however, for the human eye only as a light irregular noise in the image, and therefore much less disturbing.

According to a preferred embodiment, the frequency modulation for a control chip by an external frequency source or according to another embodiment by an internal, realized on the chip frequency source.

According to another preferred embodiment, the frequency modulation is done by using spread spectrum phase-locked loops).

Preferred developments of the present application are defined in the subclaims.

Fig. 1A bis C

Beispiele für eine zeitkontinuierliche Modulationsfunktion g(t);

Fig. 2A bis C

Beispiele für eine zeitdiskrete Modulationsfunktion g(k);

Fig. 3

ein Blockdiagramm, das die Takterzeugung in einem Steuerchip für einen Bildschirm darstellt;

Fig. 4

ein Blockdiagramm einer Steuereinheit gemäß einem ersten Ausführungsbeispiel der vorliegenden Erfindung mit einer externen Frequenzmodulation;

Fig. 5

eine Steuereinheit gemäß einem zweiten Ausführungsbeispiel der vorliegenden Erfindung mit einer internen Frequenzmodulation;

Fig. 6

den Frequenzverlauf bei einer Spread-Spectrum-Phasenregelschleife;

Fig. 7

ein Beispiel für ein Interferenzmuster bei einer LCD-Steuereinheit mit Speicher- und Bildschirm-Schnittstelle;

Fig. 8

ein Blockschaltbild einer bekannten LCD-Steuereinheit;

Fig. 9

ein Ersatzschaltbild der Bildschirmschnittstelle der LCD-Steuereinheit aus Fig. 8;

Fig. 10A

ein Interferenzmuster einer LCD-Steuereinheit mit einer Bildschirm-Schnittstelle;

Fig. 10B

ein Interferenzmuster einer LCD-Steuereinheit mit einer Bildschirm-Schnittstelle und einer Speicher-Schnittstelle; und

Fig. 11

eine Darstellung zur Erläuterung der Entstehung eines Interferenzmusters.

Hereinafter, preferred embodiments of the present invention will be explained in more detail with reference to the accompanying drawings. Show it:

Fig. 1A to C

Examples of a continuous-time modulation function g (t);

Fig. 2A to C

Examples of a discrete-time modulation function g (k);

Fig. 3

a block diagram illustrating the clock generation in a control chip for a screen;

Fig. 4

a block diagram of a control unit according to a first embodiment of the present invention with an external frequency modulation;

Fig. 5

a control unit according to a second embodiment of the present invention having an internal frequency modulation;

Fig. 6

the frequency response in a spread spectrum phase locked loop;

Fig. 7

an example of an interference pattern in a LCD control unit with memory and screen interface;

Fig. 8

a block diagram of a known LCD control unit;

Fig. 9

an equivalent circuit diagram of the screen interface of the LCD control unit of Fig. 8;

Fig. 10A

an interference pattern of an LCD control unit having a screen interface;

Fig. 10B

an interference pattern of an LCD control unit having a screen interface and a memory interface; and

Fig. 11

a representation for explaining the formation of an interference pattern.

In the following description of the preferred embodiments, the same, similar or similar elements are provided with the same reference numerals in the figures.

Based on the simple model of interference generation described above, the approaches, methods and devices according to the invention are described below, with which the formation of visible and thus interfering interferences can be prevented or suppressed.

It should be noted, however, that the methods, approaches and devices described below are to be seen as being additive to the measures used in the affected analog circuit parts and the overall system (printed circuit board, chip, application) to reduce sensitivity to noise and unwanted substrate and ground voltages. Preferably, the present invention thus uses in systems which already have a mature and relatively noise-resistant analog operating behavior.

As mentioned above, according to a preferred embodiment of the present invention, the change in the pixel frequency to avoid the interference patterns is achieved by realizing a time-dependent frequency modulation FM which destroys the correlation or the rigid ratio of the frequencies, so that when coupling in the interference frequencies Interference patterns are reduced or suppressed.

The time-dependent frequency modulation can be realized by a continuous-time frequency modulation, for example, by the function of a frequency wobbler, the frequency required by the screen or the memory base frequency (f ₀ ) a frequency range .DELTA.f at a suitable rate by a modulation function g (t) is set, goes through.

mit:

f₀ =

Basisfrequenz des Bildschirms (Pixelfrequenz) oder Basisfrequenz des Speichers

Δf =

Frequenzbereich um die Basisfrequenz

g(t) =

Modulationsfunktion

Are generated under the assumption that the control chip on the necessary clock signals by phase-locked loops (PLL = P L oop Phase Locked) applies to the input frequencies f _{xpllin (t)} of the phase-locked loops: $${\mathrm{f}}_{\mathrm{xpllin}\left(\mathrm{t}\right)}\mathrm{=}{\mathrm{f}}_{\mathrm{0}}\mathrm{+}\mathrm{.delta.f}\mathrm{*}\mathrm{G}\left(\mathrm{t}\right)$$

With:

f ₀ =

Base frequency of the screen (pixel frequency) or base frequency of the memory

Δf =

Frequency range around the base frequency

g (t) =

modulation function

The modulation function g (t) can be any continuous function, for example the functions shown in FIGS. 1A to 1C, but in principle there is no restriction as regards the design and execution of the function used.

In the time-continuous case of frequency modulation described here, the resulting pattern of interference will change steadily within each line and thus also within each individual frame, and with proper determination of the function g (t) and the parameter Δf it is possible to derive from the original correlated interference pattern to produce a seemingly uncorrelated "white" (quasi) noise.

In a preferred embodiment of the present invention, instead of the above-described, generally quite complex procedure for the continuous-time frequency modulation, a simplified, time-discrete frequency modulation is applied, which leads to similar results but offers significant advantages in terms of implementation.

In this embodiment, the frequency to be modulated f _{xpllin (k)} does not change continuously, but, depending on the embodiment, frame by frame or line by line. Furthermore, an arbitrary timing can be selected. As with continuous-time frequency modulation, the frequency here may vary steadily or randomly and abruptly, by means of a suitable random generator, allowing more efficient generation of "white" (quasi) noise.

mit:

f₀ =

Basisfrequenz des Bildschirms (Pixelfrequenz) oder Basisfrequenz des Speichers

Δf =

Frequenzbereich um die Basisfrequenz

g(k) =

zeitdiskrete Modulationsfunktion

k =

Laufindex

In this embodiment, the input frequency of the phase locked loop arrangement is as follows: $${\mathrm{f}}_{\mathrm{xpllin}\left(\mathrm{k}\right)}\mathrm{=}{\mathrm{f}}_{\mathrm{0}}\mathrm{+}\mathrm{.delta.f}\mathrm{*}\mathrm{G}\left(\mathrm{k}\right)$$

With:

f ₀ =

Base frequency of the screen (pixel frequency) or base frequency of the memory

Δf =

Frequency range around the base frequency

g (k) =

discrete-time modulation function

k =

running Index

The running index k is incremented by 1 whenever a predetermined condition for a frequency change is met, e.g. B. a line or frame change or the like occurs, ie a new line or a new frame is achieved. FIGS. 2A to C show examples of the discrete-time modulation frequency g (k), but it should also be noted that there is basically no restriction as to the discrete function to be used.

As with the first embodiment described above, the result, with a suitable choice of the function g (k), the modulation condition and the parameter .DELTA.f, is a "white" (quasi-) noise, which in the best case is not or only very slightly visible.

With regard to the embodiment described above is generally noted that the described method for generating the time-dependent frequency modulation by a suitable determination of the modulation condition is extremely flexible, which is also required due to the large number of possible input modes and input frequencies to adapt the method according to the invention to different Enabling environmental conditions.

Hereinafter, the generation and distribution of clock signals on a control chip, as described for example with reference to FIG. 8, explained in more detail, and then based on this explanation, the Description of exemplary embodiments for implementing the inventive method in control chips for LCD screens.

Fig. 3 is a block diagram of the units required for clock generation on a control chip. As can be seen in the schematic representation of FIG. 3, the circuit elements shown there are used to generate the memory clock mpll_clk and the pixel clock ppll_clk. The circuit comprises a multiplexer 100 which receives at a first input a horizontal synchronization signal HS (H-Sync). At a second input, the multiplexer 100 receives an external oscillator clock sys_clk. Based on a drive signal, the multiplexer selects one of the two inputs as an input signal for generating the pixel clock ppll_clk. The output signal selected by the multiplexer 100 is provided via a line 102 to a pre-divider 104 (pre-divider, n _prediv ), an output signal generated _{thereby being} provided via a further line 106 to the input of a phase-locked loop 108 controlled by an internal divider Divider 110 (n _div ) provides the pixel clock ppll_clk at the output. The external oscillator clock sys_clk is further provided to another pre-divider 112 (n _prediv ), which outputs an output signal to the phase-locked loop 116 at its output via a line 114. Phase locked loop 116 is controlled by an internal controller 118 (n _div ) and outputs the memory clock mpll_clk at the output.

Further, in Fig. 3, the clock for operating the register, the configuration register shown in Fig. 8, rclk is equal to the system clock or external oscillator clock sys_clk.

Furthermore, it is shown that from the horizontal synchronization signal HS via a further phase-locked loop 120 and a downstream phase-delay loop 122 the input clock avi_clk is generated, which is also provided to a sampler 124 for acquisition and digital conversion of the AVI signal.

In the schematic diagram shown in Fig. 3 is a control unit for clock generation for a LCD control chip with external memory, which usually has at least four different clocks (clock domains), which are related to each other in a certain time-variant ratio. Furthermore, a configuration for the clock generation is considered with reference to FIG. 3, which is also found in later implementations and applications.

In Fig. 3, the four clocks and their generation are outlined, and apart from the phase locked loop 108 (llpll), which can use as input the horizontal synchronization signal HS of the analog video input AVI, all other phase locked loops are driven by the external oscillator clock sys_clk.

Uncritical is the clock rclk used for the registers of the control chip 800. This is usually identical to the external clock (rclk = sys_clk) and, since the registers are static in normal operation, has no visible or measurable influence on the analog circuits of the chip.

The situation is different for the memory clock mpll_clk and screen clock (pixel clock) ppll_clk, which are generated by the associated phase locked loops 108 and 116 (ppll, mpll). By means of these clock signals not only very large digital blocks of the LCD control chip are clocked, but also the corresponding input / output interfaces, namely the memory interface and the screen interface. The input signal used in both phase-locked loops is the external oscillator clock, and by programming the pre-dividers 104, 112 and the internal loop dividers 110, 118, the desired frequency of the clock signal can be adjusted at the output. at the screen phase-locked loop can be used as an input to the external clock sys_clk and the H-sync signal of the selected input, in the illustrated embodiment, the signal HS of the analog video input, as an input signal.

Starting from the system architecture shown in FIG. 3, two preferred embodiments for implementing the methods described above for the quasi-decorrelation of the clocks are described below. It will be apparent to one skilled in the art from the implementation described below that other implementations are possible.

A first embodiment will be described with reference to FIG. 3, in which the frequency-modulated system clock is fed by an external source. FIG. 4 shows a section of the circuit elements shown in FIG. 3 for generating the pixel clock ppll_clk and the memory clock mpll_clk. For the implementation of the method, the externally supplied system clock sys_clk is selected as the input signal to the phase locked loop 108 for generating the pixel clock that for simplicity in FIG. 4, the multiplexer 100 still shown in FIG. 3 has been omitted.

In Fig. 4, it can be seen that instead of the external quartz or crystal oscillator 126 used in conventional LCD control chips, a wobble generator 128 is now used to provide the system clock sys_clk. This is shown by the broken connection between the quartz oscillator 126 and the pre-dividers 104 and 112 (n _prediv ) at 130. In the embodiment shown in Fig. 4 is a simple implementation of the present invention, wherein instead of the conventionally used quartz oscillator 126, an external frequency generator 128, z. B. the type Stanford DG 245 is used, instead of the quartz oscillator on the printed circuit board is arranged on which the control chip is arranged to drive the screen. If the frequency generator 128 is set to produce a frequency-modulated signal according to the embodiments of the inventive method described above, this frequency-modulated output signal of the generator 128 can be used as an input signal or system clock sys_clk for the phase locked loops 108 and 116. With careful selection of the parameters, a quasi-decorrelation of the clock signals ppl_clk and mpll_clk generated by the phase-locked loops 108 and 116 (ppll, mpll) with respect to the sampling clock of the analog input signal (avi_clk) is achieved here.

The systematic limits of the parameters to be selected depend on the one hand on the dynamic control characteristics of the phase locked loops 108 and 116 and on the other hand on the frequency tolerance of the connected units, ie the connected screen and the memory. This means that even with a maximum frequency deviation due to the frequency modulation, secure data transfer to the connected units still has to be guaranteed. In addition, in order to avoid timing problems within the blocks and, above all, at the interfaces between the clocks (clock domains), it is also necessary to comply with the restrictions imposed for the synthesis of the digital blocks in the case of a strong frequency modulation.

The determination of the parameters to be selected for the frequency modulation is theoretically very complex, since in reality not only the fundamental frequencies, but also all harmonic components and the dynamic properties of all components are superimposed and lead to a complex time and frequency response. Although theoretically determinable, the parameters for frequency modulation are preferably determined empirically for each combination of input mode / application. Based on the thus determined Values are then set according to a desired mode.

Although the embodiment just described provides good results with the external frequency generator, a disadvantage in this embodiment is that the cost and expense of connecting the external frequency generator is too high. For later use, the use of an external frequency generator is undesirable, so that in the realization of a simplified programmable / parametrisable generator can be used on the printed circuit board, which is indeed a possible, but also uneconomical solution.

Therefore, according to a second embodiment of the present invention for implementing the method according to the invention, the frequency-modulated system clock is generated internally, i. H. in the control unit, namely on the chip. FIG. 5 shows a circuit for internally generating the frequency modulation. As can be seen, the conventionally used external quartz oscillator 126, which is disposed on the circuit board, is maintained to provide the control chip with the system clock sys_clk. In addition to the elements already described above, a divider controller 132 is further provided, which via a first control bus 134 to the first pre-divider 104, via a second control bus 136 to the second pre-divider 112 via a third control bus 138 is in communication with the first feedback divider 110 and via a fourth control bus 140 with the second feedback divider 118.

The realization shown in FIG. 5 is an implementation of the decorrelation by an "on-chip" frequency modulation which is more elegant and technically much easier to implement compared with the realization described with reference to FIG. 4. The this embodiment underlying starting points for the frequency modulation are the pre-dividers 104 and 112 used in the phase-locked loops 108 and 116 and the feedback dividers 110 and 118, respectively. The divider value of each of the pre-dividers 104 and 112 and the feedback divider is controlled by the divider controller 132 a suitable algorithm or a programmable pseudo-random generator, so as to obtain the above-described time and frequency response. In the embodiment illustrated in FIG. 5, the divider controller 132 includes a scan controller, a programmable counter / divider, and a random generator.

wobei z.B. gilt: $${\mathrm{n}}_{\mathrm{div}}=2^0$$

$${\mathrm{n}}_{\mathrm{prediv}}=2^{16},$$

woraus sich der minimale Δf_Schritt ergibt.For the result of the frequency modulation, the accuracy of the pre-dividers 104, 112 (n _prediv ) is important, it being noted that the smallest frequency _step Δf to be set thereby is passed through the feedback divider 110, 118 (n _div ) of the phase locked loop 108, 116 is transformed back up. For the size of the effective frequency step to be achieved at the pixel clock ppll_clk or at the memory clock mpll_clk, the following applies with the same structure of the circuits: $$\mathrm{\Delta }{\mathrm{f}}_{\mathrm{step}}\mathrm{=}\mathrm{\Delta }{\mathrm{f}}_{\mathrm{n}}*{\mathrm{n}}_{\mathrm{div}}\mathrm{/}{\mathrm{n}}_{\mathrm{prediv}}\mathrm{.}$$

where, for example: $${\mathrm{n}}_{\mathrm{div}}=2^0$$

$${\mathrm{n}}_{\mathrm{prediv}}=2^{16}.$$

which results in the minimum Δf _step .

A problem with the variation of the frequency divisors is the fact that these are in principle counters that are programmed to a certain final value and deliver an output pulse when this final value (threshold) is reached. A reprogramming and thus a modulation of the input frequency of the phase locked loops can thus only take place at the overflow of the counter. Due to the dynamic behavior of the phase-locked loops, however, there is a more or less continuous-time change of the output clock signals or the output frequencies mpll_clk, ppll_clk. For this reason, it is also not necessary to realize a high resolution at the step widths Δf _step , since the intermediate regions are continuously passed through by the phase locked loops anyway.

The realization of the second exemplary embodiment for implementing the method according to the invention is much easier than with the external generation of the frequency-modulated signal, but here too the time response of the phase-locked loop is decisive. Since the pre-dividers already exist in existing circuits and designs, the inventive method can be implemented and verified with little effort (divider logic and control).

A third preferred embodiment for implementing the frequency modulation required for decorrelation is the use of an alternative phase locked loop concept. So-called spread-spectrum phase-locked loops are used in similar applications to improve the EMC / EMI (EMC = electromagnetic compatibility, EMI minimization = interference radiation minimization). By suitably adjusting the parameters of the phase-locked loops and controlling them (linear, function, or random), it is possible to obtain both a decorrelation of the clocks, which results in no visible interference, as well as positively influencing the EMC / EMI behavior.

Fig. 6 shows the difference between a normal phase locked loop (normal PLL) and a spread spectrum PLL (spread spectrum PLL). As can be seen, the spread spectrum PLL creates in contrast to the normal PLL output signals over a predetermined frequency range, whereas the normal PLL provides only a single output frequency depending on the input frequency. Thus, the clock signals can also be realized here by the method for decorrelation described above in more detail.

In the following, experimental results for the decorrelation of the clock signals will be described in more detail, which were carried out based on the above-described first embodiment for implementing the method by means of an external supply of the frequency-modulated signals.

For the analysis of interference occurring in an LCD control unit are particularly such control units, eg. B. SAA6714, with the ability to store the data in a memory and thus statically evaluate. In the following, therefore, first a corresponding experimental set-up will be described, and then the results of the decorrelation obtained therefrom, with external supply of the frequency-modulated system clock, will be shown.

• Stanford Research Systems Synthesized Function Generator, Modell DS345 als System-Clock Generator,
• Quantum Data Video Test Generator, Modell 801 GD als AVI Signalquelle,
• SAA6714 Evaluation Board "Early Dragon", Version 1.2, mit SAA6714A,
• LG Philips Panel, 18 Zoll, Modell LM181E1, SXGA-Auflösung,
• Deutronic Power Supply 12V / 5A, Modell DTP60

The test setup included the following devices and components:

• Stanford Research Systems Synthesized Function Generator, model DS345 as system clock generator,
• Quantum Data Video Test Generator, Model 801 GD as AVI signal source,
• SAA6714 Evaluation Board "Early Dragon", Version 1.2, with SAA6714A,
• LG Philips Panel, 18 inch, Model LM181E1, SXGA resolution,
• Deutronic Power Supply 12V / 5A, model DTP60

The following settings and parameters were selected:

Entrance:

Quantum Data Test Generator Format: 83 = DMT1260 Image: 43 = 45Flat27 Resolution: 1280x1024

• Stanford Research Systems Synthesized Function Generator:
• Basisfrequenz: 25.000.005,000 Hz (25,000005 MHz)

Clock generation:

• Stanford Research Systems Synthesized Function Generator:
• Base frequency: 25,000,005,000 Hz (25,000005 MHz)

Due to the possibility of setting the frequency in Hz steps on the Stanford Research Generator, it was also possible to generate the special case of a stationary interference pattern, which could then be evaluated statically - even without buffering in the memory. If, during normal operation, the system clock is generated by a quartz oscillator, then the formation and type of interference lines depends very much on the temperature of the quartz oscillator and on its aging, manufacturing tolerances, etc.

The behavior of an LCD controller was described, as described with reference to FIG. 8. The output of the external frequency generator serves as a reference signal for the memory clock and the screen clock (pixel clock), as described above. A frequency modulation on the external generator leads to a frequency modulation of the memory clock or the screen clock determined by the dynamic behavior of the respective phase locked loop.

Fig. 7 shows a section of a screen print which has been created by freezing the image in the external memory of the LCD-Scaler and by reading this memory area. Since the printed lines of the document are barely visible, three of them have been highlighted by white lines.

In contrast to the discrete model already described, in reality a strong dependence of the interference pattern is already evident with small frequency changes. When the input frequency changed by just a few hertz, different interference patterns became visible.

The following table shows some settings as well as the respective manifestations of the interference lines. Frequency (Hz) interference lines 25000004 approx. 20 degrees tilt in a clockwise direction at a distance of approx. 5 mm 25000010 approx. 20 degrees tilt clockwise at a distance of approx. 3 mm 25000012 approx. 150 degrees tilt in a clockwise direction at a distance of approx. 2 mm 25000018 approx. 20 degrees tilt in a clockwise direction at a distance of approx. 5 mm 25000025 as at 25,000,012 and 25,000,010 together

By applying decorrelation by means of a frequency-modulated system clock instead of the quartz oscillator on the printed circuit board, it is possible to make the interference patterns shown in Fig. 7 "invisible" to the human eye. Decisive for the desired effect is the combination of interference frequency, diversion of the interference fringes by the frequency modulation and the vertical refresh rate.

As an example, consider the interference pattern that occurred at 25,000,004 Hz system clock. A sweep rate of 25 Hz, a swept frequency range of 7777 Hz and a sine function as modulation frequency g (t) were selected, and these settings on the function generator achieved a very good result, with the interference lines no longer visible to the human eye were.

Preferably, the inventive method is carried out using a random modulation, since there is the possibility that the frequency modulation itself generates a new and in its formation complex interference pattern. Since this behavior is to be expected, especially with continuous modulation functions, it follows from the simulation results with the discrete model that the random modulation is the cheaper variant of the frequency modulation.

The method according to the invention has shown, both in the model and in reality, that this can effectively mitigate or make invisible interference phenomena in LCD control units by means of the described quasi-decorrelation of the clock signals.

The technical realization is possible with relatively little effort, however, for the effective use of the method, the appropriate parameters for different modes are to be determined in order to ensure that the method works reliably and there are no problems with the external components (memory and screen).

In the foregoing, a preferred embodiment of the present invention has been described, in which the visible interference has been achieved by changing the pixel frequency in the generation of the pixel data. However, the present invention is not limited thereto.

Basically, all spurious signals on the chip or circuit board can be manipulated in the same way as the signals ppll and mpll, so that the present invention is not limited to these clock signals, but is generally applicable to all clock signals.

Claims (12)

1. A method for reducing interference patterns in the display of an image on a screen with a pixel frequency (ppll_clk), wherein the image can be described by pixel data, which are provided to the screen by a control unit (800) based on received image data, wherein the control unit has an input (802, 804, 806) for receiving the image data and a plurality of clock signals, wherein one or more of the clock signals couples into the control unit via the input and overlays the image data, the method comprising:

   while processing the image data received at the control unit for display on the screen, varying one or several of the clock signals used when processing the image data by time-dependent frequency modulation (FM),

   characterized in that
   the time-dependent frequency modulation (FM) is time-discrete over a row or a frame of the image data, and the frequency (ppll_clk) is changed in a change of rows or a change of frames.
2. The method according to claim 1, wherein while processing the image data the pixel frequency (ppll_clk) is changed.
3. The method according to claim 1 or 2, wherein the control unit comprises means (108), which generates the pixel frequency (ppll_clk) depending on an applied input frequency (sys_clk), wherein the step of changing the pixel frequency (ppll_clk) comprises changing the input frequency (sys_clk).
4. The method according to claim 3, wherein the input frequency (sys_clk) is provided by an external frequency source (128) or by an internal frequency source (132) of the control unit (800).
5. The method according to claim 3 or 4, wherein the control unit comprises a memory interface (814), which is driven by a driving signal with a memory frequency (mpll_clk), and means (116) for generating the memory frequency (mpll_clk), wherein the input frequency (sys_clk) of the means (108) for generating the pixel frequency (ppll_clk) is further applied to the means (116) for generating the memory frequency (mpll_clk).
6. The method according to one of claims 3 to 5, wherein the means for generating the pixel frequency (ppll_clk) comprises a spread spectrum phase locked loop.
7. A control unit for controlling a screen, which operates at a pixel frequency (ppll_clk), for the display of an image on the screen with reduced interference pattern, wherein the control unit comprises a plurality of clock signals, comprising
   an input (802, 804, 806) for receiving image data, wherein one or more of the clock signals couples into the control unit via the input and is overlaid with the image data;
   processing means (812), which processes the received image data for display on the screen, wherein the processing means (812) varies one or several of the clock signals used when processing the image data while processing the image data by time-dependent frequency modulation (FM); and
   an output (812) for providing the processed image data for the display,
   characterized in that
   the time-dependent frequency modulation (FM) is time-discrete over a row or a frame of the pixel data, and
   the processing means (812) causes a change of the frequency (ppll_clk) in a change of rows or a change of frames.
8. The control unit according to claim 7, wherein the processing means (812) changes the pixel frequency (ppll_clk) while processing the image data.
9. The control unit according to claim 7 or 8, wherein the processing means (812) comprises a pixel frequency generator (108), which generates the pixel frequency (ppll_clk) depending on a changing input frequency signal (sys_clk).
10. The control unit according to claim 9, wherein the variable input frequency signal is provided by an external signal source (128) or by an internal frequency control (134) based on an external constant frequency signal.
11. The control unit according to claim 9 or 10, wherein the processing unit comprises a memory frequency generator (116), which generates a memory frequency (mpll_clk) for a driving signal for a memory interface (814), based on the input frequency signal (sys_clk).
12. The control unit according to one of claims 9 to 11, wherein the pixel frequency generator comprises a spread spectrum phase locked loop.

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