EP1520297A2 - Ensemble pistes conductrices integre - Google Patents

Ensemble pistes conductrices integre

Info

Publication number
EP1520297A2
EP1520297A2 EP03749895A EP03749895A EP1520297A2 EP 1520297 A2 EP1520297 A2 EP 1520297A2 EP 03749895 A EP03749895 A EP 03749895A EP 03749895 A EP03749895 A EP 03749895A EP 1520297 A2 EP1520297 A2 EP 1520297A2
Authority
EP
European Patent Office
Prior art keywords
arrangement
conductor
conductor track
interconnect
crossover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03749895A
Other languages
German (de)
English (en)
Inventor
Rudolf Strasser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1520297A2 publication Critical patent/EP1520297A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the invention relates to an integrated interconnect arrangement.
  • the conductor track arrangement connects, for example, components of an integrated circuit arrangement or is itself part of an integrated component.
  • the three main types of integrated circuit arrangements are: monolithic circuit arrangements in which components are also arranged in a semiconductor that serves as a carrier.
  • the manufacturing techniques for integrated arrangements include Layer application methods and layer structuring methods used.
  • layer application methods are: screen printing in the case of thick-layer technology, or sputtering in the case of monolithic circuit arrangements and thin-layer circuits, the CVD method (Chemical Vapor Deposition) or the PVD method (Physical Vapor Deposition).
  • Layer structuring processes are, for example: - lithographic processes, or - etching processes.
  • the conductor track of a conductor track arrangement has an electrical resistance of less than 10 "4 ohms per centimeter for direct current.
  • the conductor tracks are usually made of aluminum, an aluminum alloy, copper or a copper alloy. These materials ensure that the conductor tracks have the lowest possible ohmic losses and eddy current losses and generate other power losses.
  • the invention is based on the consideration that, with increasing frequency in integrated interconnect arrangements, it becomes increasingly difficult due to electrodynamic phenomena to produce low-resistance connection arrangements or connection arrangements which cause low power losses.
  • the two main electrodynamic phenomena are the skin effect and the proximity effect. If alternating current flows through a conductor, an alternating magnetic field also occurs, which induces a counter voltage in the conductor that is greatest in the middle of the conductor. Because of this counter voltage, the current is distributed unevenly over the conductor. The current density increases from the center of the conductor to the edge. This phenomenon is called current displacement or skin or skin effect. Due to the current displacement, the conductor cross-section is only partially used by the alternating current. The reduction in the effective conductor cross section increases the effective resistance of the conductor.
  • the invention is based on the consideration that the depth of penetration of the current into the conductor, for example for copper, is greater than two micrometers below a frequency of one gigahertz. This means that the structures mentioned so far, with structure widths of about two micrometers or smaller, have no significant influence on performance losses. However, if signals in the frequency range from one gigahertz to 50 gigahertz, for example, are to be transmitted, a considerable increase in the line resistance due to the current displacement mechanisms can be determined even with structure dimensions of less than two micrometers.
  • a simple parallel connection of conductor tracks, which also run spatially parallel, does not reduce the power losses because the middle conductor tracks of the conductor track arrangement cannot contribute to the current flow due to the current displacement mechanisms mentioned. As already explained, the current only flows in the outer conductor tracks.
  • the conductor track arrangement according to the invention therefore contains at least three electrically connected conductor tracks.
  • An electrical insulating material is arranged between the conductor tracks.
  • the conductor track arrangement contains at least two crossover sections arranged at different points on the longitudinal axis of the conductor track arrangement, at which conductor tracks of the conductor track arrangement cross. By crossing them several times, the conductor tracks of the conductor track arrangement can be twisted or twisted, for example, by all of the conductor tracks around the longitudinal axis of the conductor track arrangement, in the manner of interweaving, in which the conductor tracks progressively alternate over another conductor track in the direction of the longitudinal axis of the conductor track arrangement and are arranged under another conductor track, or arrange in the manner of a weave. Due to the crossovers, the conductor tracks assume different positions within the conductor track arrangement.
  • the multiple crossing leads to the fact that each conductor track contributes to the current flow even at very high frequencies. The multiple crossings reduce the power losses, in particular the ohmic losses.
  • the conductor tracks of the conductor track arrangement are lined up in one plane outside the crossover sections transversely to the longitudinal direction of the conductor track arrangement.
  • Conductor tracks arranged in this way can be produced in a simple manner using the two-dimensional structuring methods of integrated technology that are usually used. In this way, the conductor tracks can be arranged next to one another in a metallization layer or also one above the other in different metallization layers.
  • the conductor tracks are arranged in a metallization layer between adjacent crossover sections.
  • the metallization layer is parallel to the main surface of a semiconductor substrate on which integrated components are located.
  • the conductor tracks lying in a metallization layer are generated simultaneously, i.e. with the same separation and structuring processes.
  • a conductor track is transverse to all other conductor tracks at the crossover sections. NEN the conductor arrangement arranged.
  • the transverse conductor track or the other conductor tracks are arranged in a different metallization layer. This enables a crossover section to be produced with only two metallization layers. If the transverse conductor track lies in the additional metallization layer, only two additional contact holes are required. Because contacting in the area of the contact holes leads to additional resistance, the total resistance increases only insignificantly with only two contact holes per crossover section.
  • the other conductor tracks lie on or within the crossover sections in a different direction than outside the crossover sections.
  • the longitudinal direction of the conductor track at the crossover section initially changes by a certain amount in a certain direction.
  • the direction of the longitudinal axis of the conductor track changes again, the direction of the change in direction here being opposite to the first change in direction and the
  • the amount of change of direction remains the same. This measure ensures that the conductor track is offset in the crossover section.
  • the offset creates space which is used by the conductor track which runs in the crossover section at right angles to the other conductor tracks. Overall, this arrangement determines the width of the conductor track arrangement only by the width of the conductor tracks and the width of the insulation between the conductor tracks. However, the other conductor tracks on the crossover section can also be arranged in a different way.
  • the conductor tracks are arranged outside the crossover sections in different metallization layers.
  • the conductor tracks lie one above the other in the normal direction to a main surface of a semiconductor substrate of the integrated circuit arrangement. This measure makes it possible to Arrange NEN with a small footprint with respect to the surface of the semiconductor substrate.
  • good capacitive decoupling can be achieved between the conductor tracks of the conductor track arrangement.
  • a conductor track is arranged at the crossover sections in a contact hole transverse to all other conductor tracks.
  • the contact hole preferably leads to a further metallization layer.
  • the conductor tracks of the conductor track arrangement in the crossover sections are each led from one metallization layer into an adjacent metallization layer, for example uniformly into the one closer to the substrate or into the one further away from the substrate Metallization layer lying on the substrate.
  • the conductor track arrangement contains exactly two crossover sections.
  • the number of contact holes within the conductor track arrangement can thereby be reduced.
  • the manufacturing process is simplified and the power losses decrease.
  • the two crossover sections are arranged at one third of the length of the conductor track arrangement and at two thirds of the length of the conductor track arrangement. This measure makes it possible for the current flow to be independent of the frequency, i.e. especially at very high frequencies, e.g. between one gigahertz and 50 gigahertz or higher, is evenly distributed on the conductor tracks.
  • all crossover sections have essentially the same structure.
  • the sections of the interconnect arrangement lying outside the crossover sections have identical spatial structures to one another. This measure simplifies the manufacturing process of the circuit arrangement because, for example, only mask patterns have to be defined for a crossover section. The same patterns are then used for all crossover sections.
  • each conductor track is arranged the same length between other conductor tracks.
  • each conductor track is arranged the same length on the edge of the conductor track arrangement.
  • the largest lateral dimension of a conductor track transverse to the longitudinal direction of the conductor track arrangement is less than ten micrometers or less than five micrometers.
  • the length of the conductor track arrangement is alternatively or cumulatively less than ten millimeters or less than one millimeter.
  • the area of application of the circuit arrangement is therefore not only in the thick-film area, in which thicknesses greater than 50 micrometers to about 1 millimeter are typically used, but also in the area of monolithic circuits and thin-film technology.
  • the invention also relates to the use of the conductor track arrangement as a coil and as a signal guide to an antenna of a transmitting part or from an antenna of a receiving part.
  • the use as a coil offers the advantage that the quality of the coil and thus also the quality of an oscillating circuit containing the coil becomes very high even at frequencies in the gigahertz range.
  • the use of the conductor track arrangement as part of the signal routing to an antenna or from an antenna now enables feeds which were previously carried out discretely into the circuit arrangement integrate. The highest frequencies of the circuit arrangement occur particularly in the area of the antenna, for example frequencies in the gigahertz range.
  • FIG. 1 shows a plan view of an integrated line, the conductor tracks of which are arranged outside of crossover sections in a metallization layer,
  • FIG. 2 shows a cross section through the integrated line of FIG. 1,
  • FIG. 3 shows a top view of an integrated line, the conductor tracks of which are arranged outside of crossover sections in three metallization layers, and
  • FIG. 4 shows a cross section through the integrated line of FIG. 3.
  • FIG. 1 shows a top view of an integrated circuit arrangement 10 which contains an integrated line 12.
  • the integrated line 12 contains three conductor tracks LB1 to LB3, which are electrically connected in parallel in connection sections 14 and 16.
  • An end section 18, a crossover section 20, a middle section 22, a crossover section 24 and an end section 26 lie between the connection sections 14 and 16 in the following order.
  • the conductor tracks LB1 to LB3 are parallel to one another an upper metallization layer 50, see also FIG. 2.
  • the crossover section 20 contains contact hole regions 28 and 30, at the bottom of which a section 32 of the conductor track LB1 ends.
  • Section 32 is at right angles to a longitudinal axis 34 of line 12 below the conductor tracks LB2 and LB3 in a lower metallization layer 54, see also FIG. 2.
  • the contact hole regions 28 and 30 adjoin sections of the conductor track LB1 lying in the metallization layer 50, the sections of the conductor track LB1 starting from the end section 18 and Taper from the central section 22 to the contact hole areas 28 and 30 in the crossover area.
  • the conductor tracks LB2 and LB3 in the crossover section 20 are arranged obliquely to the longitudinal axis 34 at an angle between 20 and 60 degrees, for example of 30 degrees.
  • the angle is dimensioned such that, seen over the length of the crossover section 20, there is exactly an offset of the conductor track LB2 or the conductor track LB3 from the width of a conductor track plus a distance A between adjacent conductor tracks. Because of the offset, the conductor track LB1 in the middle section 22 can assume the position that the conductor track LB3 has in the end section 18.
  • the crossover section 24 is structured in exactly the same way as the crossover section 20.
  • the crossover section 24 there are two contact hole regions 36 and 38, the contact hole bottom of which ends at a section 40 of the conductor track LB2.
  • the section 40 is at right angles to the longitudinal axis 34.
  • the contact hole regions are delimited by sections of the conductor track LB2 lying in the metallization layer 50.
  • the conductor tracks LB1 and LB3 are arranged in the crossover section 24 parallel to one another, but obliquely to the longitudinal axis 34 at an angle of approximately 30 degrees such that the conductor track LB1 and the conductor track LB3 by one conductor track width and by the distance A between adjacent conductor tracks NEN be relocated.
  • a length L1 of the end section 18, a length L2 of the middle section 22 and a length L3 of the end section 26 are the same, so that each conductor track LB1 to LB3 lies exactly in one end section 18 or in the middle section 22 between the other conductor tracks LB1 to LB3.
  • the conductor track LB3 is only in the middle section 2 between the conductor tracks LB1 and LB2.
  • the lengths L1, L2 and L3 are each 100 micrometers.
  • the crossover sections 20 and 24 are smaller than a fifth of this length, for example ten micrometers.
  • Widths B1, B2 and B3 of the conductor tracks LB1, LB2 and LB3 are the same in the end sections 18, 26 and in the middle section 22, for example one micrometer.
  • An insulation distance A between adjacent conductor tracks LB1 to LB3 is, for example, 0.5 micrometers.
  • the total width B of the line 12 results from the sum of the widths B1 to B3 and twice the insulation distance A, i.e. four micrometers in the exemplary embodiment.
  • a coordinate system 42 assigned to the circuit arrangement 10 shows an x-axis 44 lying in the plane of the drawing and coinciding with the direction of the longitudinal axis 34, a y-axis 46 lying at right angles to the x-axis 44 in the plane of the drawing and a y-axis 46 pointing in the normal direction to the plane of the drawing z-axis 48.
  • FIG. 1 also shows the position of a cross-section I which intersects the line 12 in the xz plane.
  • the cross section I cuts the conductor track LB1 in the end section 18, the conductor track LB2 in the middle section 22 and the conductor track LB3 in the end section 26.
  • FIG. 2 shows the cross section I through the line 12.
  • the upper metallization layer 50, the insulation layer 52, the metallization layer 54, and the insulation layer 56 have thicknesses D1, D2, D3 and D4 in this order.
  • the thicknesses D1 and D3 are the same in the exemplary embodiment and are, for example, 0.5 micrometers.
  • the thicknesses D2 and D4 of the insulating layer are also the same in the exemplary embodiment and are, for example, one micrometer.
  • more than three conductor tracks are used.
  • the number of crossover sections then increases accordingly. For example, there would be three crossover sections with four conductor tracks. However, there are also lines with more than ten conductor tracks.
  • FIG. 3 shows a top view of an integrated circuit arrangement 110 which contains an integrated line 112.
  • the integrated line 112 contains three conductor tracks LBa to LBc, which are electrically connected in parallel in a connection section 114 at the left end of the line 112 or in a connection section (not shown) at the other end of the line 112.
  • An end section 118, a crossover section 120, a middle section 122, a crossover section 124 and an end section 126 lie between the connection sections 114 and 116 in the following order.
  • the conductor tracks LBa to LBc lie one above the other in three metallization layers 202, 206 and 210 in the normal direction of a semiconductor substrate of the circuit arrangement 110, see also FIG. 4. Accordingly, only the top ones are shown in FIG. 3 Conductor tracks shown, ie in the end 118 cut the conductor track LBa, in the middle section 122 the conductor track LBb and in the end section 126 the conductor track LBc.
  • bypass section 150 of the conductor track LBb on one side of the line 112, which is located in the metallization layer 206.
  • the conductor track LBb is guided past a contact hole region 220, which is explained in more detail below with reference to FIG. 4.
  • a bypass section 152 of the conductor track LBc is located on the other side of the line 112.
  • the bypass section 152 lies in the metallization layer 210. With the help of the bypass section 152, the conductor track LBc is guided past the contact hole region 220. Also located in
  • Crossover section 120 contact hole areas 222, 224 and 226, which are also shown in Figure 4.
  • the crossover region 124 is structured in exactly the same way as the crossover region 120.
  • the conductor track LBb is guided downward in a contact hole region 230, which is explained in more detail below with reference to FIG.
  • a bypass section 160 of the conductor track LBc lies on one side of the line 112 in the crossover section 124 in the metallization layer 206.
  • the bypass section 160 leads the conductor track LBc past the contact hole region 230 and then back to the longitudinal axis 134 of the line 112.
  • On the other side of the line 112 is a bypass section 162 of the conductor track LBa in the crossover section 124.
  • the bypass section 162 lies in the metallization layer 210 and leads the line LBa past the contact hole region 230.
  • the end section 118, the middle section 122 and the end section 126 have a length La, Lb and Lc.
  • the lengths La, Lb and Lc are the same and are 50 micrometers in the exemplary embodiment.
  • the crossover sections 120 and 124 are compared to the length of the end sections 118, 126 and the middle section 122 short, for example only ten micrometers.
  • the conductor tracks LBa, LBb and LBc have widths Ba, Bb and Bc, which are the same and are, for example, one micrometer in the exemplary embodiment.
  • a coordinate system 172 shows an x-axis 174 which lies in the longitudinal direction 134 of the line 112.
  • a y-axis 176 is at right angles to the x-axis 174.
  • a z-axis 180 points in the normal direction of the drawing plane or in the normal direction of the main surface of a semiconductor substrate of the circuit arrangement 110.
  • the position of a cross section II is shown in FIG , which lies in the xz plane and intersects all conductor tracks LBa to LBc in the end section 118, in the middle section 122 or in the end section 126.
  • FIG. 4 shows the cross section II through the line 112.
  • an insulating layer 200, the metal layer 202, an insulating layer 204, the metal layer 206, an insulating layer 208, the metal layer 210, an insulating layer 212, from above to a semiconductor substrate (not shown), a metal layer 214 and an insulating layer 216 are shown.
  • the insulation layers 200, 204, 208, 212 and 216 contain, for example, silicon dioxide as the insulation material.
  • the metal layer 202, the insulating layer 204, the metal layer 206, the insulating layer 208, the metal layer 210, the insulating layer 212 and the metal layer 214 have thicknesses D5, D6, D7, D8, D9, D10 and DU in this order.
  • the thicknesses D5, D7, D9 and DU of the metal layers are the same and are, for example, 0.5 micrometers.
  • the thicknesses D6, D8 and D10 of the insulation layers are also the same and are, for example, one micrometer.
  • the line 112 has a width W1 which results from the addition of the thicknesses D5 to D9, ie in the exemplary embodiment a width W1 of 3.5 micrometers.
  • the line 112 has a width W2 which results from the addition of the thicknesses D5 to DU, ie in the exemplary embodiment a width W2 of six micrometers.
  • bypass sections 150 to 162 lie on the same side of the line 112.
  • the lower interconnect can also be routed upward in the crossover sections 120 and 124, respectively.
  • the number of conductor tracks of the type of line explained with reference to FIGS. 3 and 4 is limited by the number of metallization layers available. For example, four conductor tracks can be used, in which case three crossover sections are required. However, there are also integrated circuit arrangements with six or eight metallization layers, so that the number of conductor tracks can be increased further.
  • the overall conductance is increased even for high frequencies.
  • the overall conductance can be increased further by increasing the conductor width B or the conductor width Wl by using additional conductor paths. If one were only to use parallel conductor tracks, widening the line would no longer have a positive effect from the point at which the penetration depth of the current is smaller than half the conductor track width of the conductor tracks in the line due to the skin effect or the proximity effect. Electrodynamic simulations with field calculation programs confirm this. This means that low-impedance connecting cables can be built even for high frequencies or that their conductance scales to a good approximation with the overall width of the cable.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Waveguides (AREA)

Abstract

L'invention concerne un ensemble pistes conductrices intégré (12) qui comprend plusieurs pistes conductrices (LB1 à LB3) se croisant au niveau de deux segments de croisement (20, 24). On obtient ainsi un flux de courant uniforme dans les trois pistes conductrices même en cas de fréquences très élevées.
EP03749895A 2002-05-08 2003-03-19 Ensemble pistes conductrices integre Withdrawn EP1520297A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10220653A DE10220653A1 (de) 2002-05-08 2002-05-08 Integrierte Leiterbahnanordnung
DE10220653 2002-05-08
PCT/EP2003/050070 WO2003096419A2 (fr) 2002-05-08 2003-03-19 Ensemble pistes conductrices integre

Publications (1)

Publication Number Publication Date
EP1520297A2 true EP1520297A2 (fr) 2005-04-06

Family

ID=29285226

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03749895A Withdrawn EP1520297A2 (fr) 2002-05-08 2003-03-19 Ensemble pistes conductrices integre

Country Status (5)

Country Link
US (1) US7550854B2 (fr)
EP (1) EP1520297A2 (fr)
CN (1) CN100420016C (fr)
DE (1) DE10220653A1 (fr)
WO (1) WO2003096419A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7462038B2 (en) * 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
DE102007040871A1 (de) * 2007-08-29 2009-03-12 Osram Gesellschaft mit beschränkter Haftung Verbindungselement
US9305992B2 (en) * 2011-06-16 2016-04-05 Altera Corporation Integrated circuit inductors with intertwined conductors
DE102021112455A1 (de) 2021-05-12 2022-11-17 Technische Universität Dresden, Körperschaft des öffentlichen Rechts Spulenanordnungen und Verfahren zum Herstellen einer Spulenanordnung

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559360A (en) * 1994-12-19 1996-09-24 Lucent Technologies Inc. Inductor for high frequency circuits
DE69737411T2 (de) * 1997-02-28 2007-10-31 Telefonaktiebolaget Lm Ericsson (Publ) Verbesserter q-Induktor mit mehreren Metallisierungsschichten
FI971180A (fi) * 1997-03-20 1998-12-23 Micronas Oy Stripe-line-kela
US6049308A (en) * 1997-03-27 2000-04-11 Sandia Corporation Integrated resonant tunneling diode based antenna
DE19727758A1 (de) 1997-04-17 1998-10-22 Alsthom Cge Alcatel Mehrfachparallelleiter für Wicklungen elektrischer Geräte und Maschinen
EP0872858A3 (fr) * 1997-04-17 1999-02-24 Alcatel Conducteur parallèle multiple pour enroulements de machines et appareils électriques
DK1012855T3 (da) * 1997-06-20 2001-08-13 Ixos Ltd Elektrisk kabel og fremgangsmåde til fremstilling af dette
US6569757B1 (en) * 1999-10-28 2003-05-27 Philips Electronics North America Corporation Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
DE10132847A1 (de) 2001-07-06 2003-01-30 Fraunhofer Ges Forschung Leiter und Spule mit verringerten Wirbelstromverlusten
US6987307B2 (en) * 2002-06-26 2006-01-17 Georgia Tech Research Corporation Stand-alone organic-based passive devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None *
See also references of WO03096419A3 *

Also Published As

Publication number Publication date
CN100420016C (zh) 2008-09-17
WO2003096419A3 (fr) 2004-07-22
CN1698201A (zh) 2005-11-16
US7550854B2 (en) 2009-06-23
WO2003096419A2 (fr) 2003-11-20
DE10220653A1 (de) 2003-11-27
US20060202338A1 (en) 2006-09-14

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