WO2003096419A3 - Integrierte leiterbahnanordnung - Google Patents

Integrierte leiterbahnanordnung Download PDF

Info

Publication number
WO2003096419A3
WO2003096419A3 PCT/EP2003/050070 EP0350070W WO03096419A3 WO 2003096419 A3 WO2003096419 A3 WO 2003096419A3 EP 0350070 W EP0350070 W EP 0350070W WO 03096419 A3 WO03096419 A3 WO 03096419A3
Authority
WO
WIPO (PCT)
Prior art keywords
conductor arrangement
strip conductor
integrated strip
integrated
strip conductors
Prior art date
Application number
PCT/EP2003/050070
Other languages
English (en)
French (fr)
Other versions
WO2003096419A2 (de
Inventor
Rudolf Strasser
Original Assignee
Infineon Technologies Ag
Rudolf Strasser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Rudolf Strasser filed Critical Infineon Technologies Ag
Priority to US10/514,145 priority Critical patent/US7550854B2/en
Priority to EP03749895A priority patent/EP1520297A2/de
Publication of WO2003096419A2 publication Critical patent/WO2003096419A2/de
Publication of WO2003096419A3 publication Critical patent/WO2003096419A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Waveguides (AREA)

Abstract

Erläutert wird eine integrierte Leiterbahnanordnung (12) mit mehreren Leiterbahnen (LB1 bis LB3), die an zwei Überkreuzungsabschnitten (20, 24) einander überkreuzen. Durch diese Massnahme lässt sich selbst bei sehr hohen Frequenzen ein gleichmässiger Stromfluss in allen drei Leiterbahnen erzielen.
PCT/EP2003/050070 2002-05-08 2003-03-19 Integrierte leiterbahnanordnung WO2003096419A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/514,145 US7550854B2 (en) 2002-05-08 2003-03-19 Integrated interconnect arrangement
EP03749895A EP1520297A2 (de) 2002-05-08 2003-03-19 Integrierte leiterbahnanordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10220653A DE10220653A1 (de) 2002-05-08 2002-05-08 Integrierte Leiterbahnanordnung
DE10220653.8 2002-05-08

Publications (2)

Publication Number Publication Date
WO2003096419A2 WO2003096419A2 (de) 2003-11-20
WO2003096419A3 true WO2003096419A3 (de) 2004-07-22

Family

ID=29285226

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/050070 WO2003096419A2 (de) 2002-05-08 2003-03-19 Integrierte leiterbahnanordnung

Country Status (5)

Country Link
US (1) US7550854B2 (de)
EP (1) EP1520297A2 (de)
CN (1) CN100420016C (de)
DE (1) DE10220653A1 (de)
WO (1) WO2003096419A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7462038B2 (en) * 2007-02-20 2008-12-09 Qimonda Ag Interconnection structure and method of manufacturing the same
DE102007040871A1 (de) * 2007-08-29 2009-03-12 Osram Gesellschaft mit beschränkter Haftung Verbindungselement
US9305992B2 (en) * 2011-06-16 2016-04-05 Altera Corporation Integrated circuit inductors with intertwined conductors
DE102021112455A1 (de) 2021-05-12 2022-11-17 Technische Universität Dresden, Körperschaft des öffentlichen Rechts Spulenanordnungen und Verfahren zum Herstellen einer Spulenanordnung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559360A (en) * 1994-12-19 1996-09-24 Lucent Technologies Inc. Inductor for high frequency circuits
WO1998043258A2 (en) * 1997-03-20 1998-10-01 Micro Analog Systems Oy Stripe-line inductor
DE19727758A1 (de) * 1997-04-17 1998-10-22 Alsthom Cge Alcatel Mehrfachparallelleiter für Wicklungen elektrischer Geräte und Maschinen
WO2003005381A1 (de) * 2001-07-06 2003-01-16 Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung, E.V. Leitfähige struktur mit verbesserten wechselstromeigenschaften

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69737411T2 (de) * 1997-02-28 2007-10-31 Telefonaktiebolaget Lm Ericsson (Publ) Verbesserter q-Induktor mit mehreren Metallisierungsschichten
US6049308A (en) * 1997-03-27 2000-04-11 Sandia Corporation Integrated resonant tunneling diode based antenna
EP0872858A3 (de) * 1997-04-17 1999-02-24 Alcatel Mehrfachparallelleiter für Wicklungen elektrischer Geräte und Maschinen
DK1012855T3 (da) * 1997-06-20 2001-08-13 Ixos Ltd Elektrisk kabel og fremgangsmåde til fremstilling af dette
US6569757B1 (en) * 1999-10-28 2003-05-27 Philips Electronics North America Corporation Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
US6987307B2 (en) * 2002-06-26 2006-01-17 Georgia Tech Research Corporation Stand-alone organic-based passive devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559360A (en) * 1994-12-19 1996-09-24 Lucent Technologies Inc. Inductor for high frequency circuits
WO1998043258A2 (en) * 1997-03-20 1998-10-01 Micro Analog Systems Oy Stripe-line inductor
DE19727758A1 (de) * 1997-04-17 1998-10-22 Alsthom Cge Alcatel Mehrfachparallelleiter für Wicklungen elektrischer Geräte und Maschinen
WO2003005381A1 (de) * 2001-07-06 2003-01-16 Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung, E.V. Leitfähige struktur mit verbesserten wechselstromeigenschaften

Also Published As

Publication number Publication date
CN100420016C (zh) 2008-09-17
CN1698201A (zh) 2005-11-16
US7550854B2 (en) 2009-06-23
WO2003096419A2 (de) 2003-11-20
DE10220653A1 (de) 2003-11-27
US20060202338A1 (en) 2006-09-14
EP1520297A2 (de) 2005-04-06

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