EP1412983A2 - Elektronikbauteil und seine herstellung - Google Patents

Elektronikbauteil und seine herstellung

Info

Publication number
EP1412983A2
EP1412983A2 EP02741171A EP02741171A EP1412983A2 EP 1412983 A2 EP1412983 A2 EP 1412983A2 EP 02741171 A EP02741171 A EP 02741171A EP 02741171 A EP02741171 A EP 02741171A EP 1412983 A2 EP1412983 A2 EP 1412983A2
Authority
EP
European Patent Office
Prior art keywords
electronic device
heat
absorbent material
dimensional
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02741171A
Other languages
English (en)
French (fr)
Inventor
Mario Palazzetti
Eugenio Faggioli
Riccardo Groppo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centro Ricerche Fiat SCpA
Original Assignee
Centro Ricerche Fiat SCpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centro Ricerche Fiat SCpA filed Critical Centro Ricerche Fiat SCpA
Publication of EP1412983A2 publication Critical patent/EP1412983A2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427Cooling by change of state, e.g. use of heat pipes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06593Mounting aids permanently on device; arrangements for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an electronic device and relative fabrication method, and in particular to a three-dimensional electronic device comprising integrated circuits .
  • a three-dimensional electronic device is defined by a number of electronic circuits stacked and housed in a package made of plastic material, typically epoxy resin, and from which connecting pins project.
  • the fabrication method comprises a step of stacking a number of integrated electronic circuits 1 - only three of which are shown for the sake of simplicity.
  • each integrated electronic circuit 1 comprises a so-called die 2 glued or soldered to a flexible support 3 having a structure similar to that of a printed circuit board, and on which are formed leads 4 connected electrically at one end to respective test pads 5 equally spaced along a peripheral portion of flexible support 3, and, at the other end, to respective regions of die 2 by means of connecting wires .
  • the stacking step is followed by a step of depositing an absorbent material 10 between each integrated electronic circuit 1 and the next.
  • absorbent material 10 is deposited in the gaps between integrated electronic circuits 1, which may, for example, be located 0.2 mm apart, and each be, for example, roughly 1 cm 2 in size.
  • Absorbent material 10 is then soaked with a two- phase mixture of a thermally stable insulating liquid, which impregnates and spreads by capillarity inside absorbent material 10.
  • absorbent material 10 may be a fibrous-structure material capable of forming capillary vessels, such as cotton or cloth or powder.
  • the thermally stable insulating liquid used is a nonionic liquid, preferably an organic solvent, such as a hydrocarbon or a mixture of appropriately selected hydrocarbons, preferably with a boiling point of 50°C to
  • the step of depositing the absorbent material is followed by a molding step, in which a substantially parallelepiped- shaped package 7 made of epoxy resin and enclosing integrated electronic circuits 1 is formed.
  • Package 7 is then sawed to expose leads 4.
  • a plating step is then performed, in which the lateral walls of package 7 are plated with conducting material, e.g. a nickel and gold alloy.
  • the plating step is followed by a connecting step, in which a laser beam defines conducting tracks 8 electrically connecting leads 4 as required, so as to obtain the three-dimensional electronic device indicated as a whole by 9.
  • the liquid serves as a means of transferring heat. That is, the liquid permeates absorbent material 10 contacting integrated circuits 1, is converted to vapor, and then comes into contact with, and transfers heat to, the walls of package 7, which serve as heat-dissipating means .
  • the vapor then cools and returns to the liquid state.
  • the liquid is then reabsorbed by absorbent material 10 and, exploiting the capillarity of the absorbent material, is again brought into contact with integrated circuits 1.
  • Three-dimensional electronic device 9 has the following advantages :
  • the method of fabricating three-dimensional electronic device 9 provides for further miniaturization of the electronic circuits of three-dimensional electronic device 9.
  • the heat-dissipating means may be external to package 7.
  • the present invention may be used for dissipating heat in any type of electronic device, even other than three-dimensional, or comprising even only one electronic circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
EP02741171A 2001-06-05 2002-06-05 Elektronikbauteil und seine herstellung Withdrawn EP1412983A2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
ITTO20010540 2001-06-05
IT2001TO000540A ITTO20010540A1 (it) 2001-06-05 2001-06-05 Dispositivo elettronico e relativo processo di fabbricazione.
PCT/IT2002/000367 WO2002099883A2 (en) 2001-06-05 2002-06-05 Electronic device and relative fabrication method

Publications (1)

Publication Number Publication Date
EP1412983A2 true EP1412983A2 (de) 2004-04-28

Family

ID=11458933

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02741171A Withdrawn EP1412983A2 (de) 2001-06-05 2002-06-05 Elektronikbauteil und seine herstellung

Country Status (4)

Country Link
EP (1) EP1412983A2 (de)
AU (1) AU2002314532A1 (de)
IT (1) ITTO20010540A1 (de)
WO (1) WO2002099883A2 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673306A (en) * 1970-11-02 1972-06-27 Trw Inc Fluid heat transfer method and apparatus for semi-conducting devices
US5270571A (en) * 1991-10-30 1993-12-14 Amdahl Corporation Three-dimensional package for semiconductor devices
US5349237A (en) * 1992-03-20 1994-09-20 Vlsi Technology, Inc. Integrated circuit package including a heat pipe
JP2001183080A (ja) * 1999-12-24 2001-07-06 Furukawa Electric Co Ltd:The 圧縮メッシュウイックの製造方法、および、圧縮メッシュウイックを備えた平面型ヒートパイプ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02099883A3 *

Also Published As

Publication number Publication date
AU2002314532A1 (en) 2002-12-16
WO2002099883A3 (en) 2004-03-04
ITTO20010540A0 (it) 2001-06-05
ITTO20010540A1 (it) 2002-12-05
WO2002099883A2 (en) 2002-12-12

Similar Documents

Publication Publication Date Title
US7528009B2 (en) Wafer-leveled chip packaging structure and method thereof
US4849857A (en) Heat dissipating interconnect tape for use in tape automated bonding
US4827376A (en) Heat dissipating interconnect tape for use in tape automated bonding
JP4397587B2 (ja) 熱増強型マイクロ回路パッケージとその作製方法
US8847383B2 (en) Integrated circuit package strip with stiffener
US6229216B1 (en) Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6724631B2 (en) Power converter package with enhanced thermal management
KR100620879B1 (ko) 플립 칩 반도체 장치
CN103782381A (zh) 包括在衬底上的管芯以及在管芯上具有开窗的散热器的电子组件
US7786571B2 (en) Heat-conductive package structure
JP2000036518A (ja) ウェハスケールパッケージ構造およびこれに用いる回路基板
US7095111B2 (en) Package with integrated wick layer and method for heat removal
JP2004064043A (ja) 半導体パッケージング装置
KR101323416B1 (ko) 전력 회로 패키지와 그 제조 방법
JPWO2009011419A1 (ja) 電子部品実装装置及びその製造方法
CN112185911A (zh) 包含垂直集成电路的半导体组合件及其制造方法
KR102194720B1 (ko) 방열 구조체를 포함하는 회로기판
EP1412983A2 (de) Elektronikbauteil und seine herstellung
JP2011077075A (ja) 発熱性電子素子内蔵のモジュール基板及びその製造方法
JP2007299887A (ja) 半導体集積回路素子搭載用基板および半導体装置
JP3178405B2 (ja) 熱応力を緩和した積層半導体装置モジュール
CN115084046B (zh) 一种混合集成半导体封装及其制造方法
JPS587064B2 (ja) シユウセキカイロヨウパツケ−ジ
KR20010057046A (ko) 캐비티를 갖는 패키지 기판
JPH10256414A (ja) 半導体パッケージ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20031230

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

R17D Deferred search report published (corrected)

Effective date: 20040304

17Q First examination report despatched

Effective date: 20071106

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20080517