EP1405413B1 - Circuit multiplicateur - Google Patents

Circuit multiplicateur Download PDF

Info

Publication number
EP1405413B1
EP1405413B1 EP02752994A EP02752994A EP1405413B1 EP 1405413 B1 EP1405413 B1 EP 1405413B1 EP 02752994 A EP02752994 A EP 02752994A EP 02752994 A EP02752994 A EP 02752994A EP 1405413 B1 EP1405413 B1 EP 1405413B1
Authority
EP
European Patent Office
Prior art keywords
input
current
output
multiplier circuit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP02752994A
Other languages
German (de)
English (en)
Other versions
EP1405413A2 (fr
Inventor
Martin Simon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1405413A2 publication Critical patent/EP1405413A2/fr
Application granted granted Critical
Publication of EP1405413B1 publication Critical patent/EP1405413B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function

Definitions

  • the present invention relates to a multiplier circuit.
  • Analog multiplier circuits for multiplication two input signals that is determination of their Sum and difference frequencies are usually in transmitters and receivers used in high-frequency applications.
  • each an emitter node is ever a load terminal of a differential amplifier whose control inputs have a second, to be multiplied signal is fed, which is usually that to be implemented on a different frequency level or the carrier frequency modulating input useful signal is.
  • the differential amplifier in its linear Working area, are the transistors of the transistor pairs, where the control input side, the local oscillator signal can be fed, operated switched and form quadrature modulators of the mixer.
  • the control inputs of the differential amplifier are accordingly controlled by low pass filtered baseband signals, wherein These control inputs are powered by digital / analog converters the output side of a digital baseband module are connected.
  • a relatively large Be set working current To have sufficiently good linearity properties and to achieve a sufficiently large reinforcement, must be in the differential amplifiers a relatively large Be set working current.
  • the local oscillator signal providing oscillator also the relatively high working current and the usual provided feedback resistors of the differential amplifier to a relatively high noise level at Modulator output.
  • the system requirements GSM standard, Global System for Mobile Communication It is customary at the output of the modulator to use a surface acoustic wave filter.
  • Document EP 1 160 717 A1 discloses an analog multiplier circuit specified. Both inputs are for feeding Voltage signals designed. The emitter nodes of the differential amplifier are connected to one of the inputs via current mirrors. To convert the voltage signal into a current signal are a total of four resistors between the current mirror and Ground switched.
  • the document EP 0 365 085 A2 discloses a circuit for Setting the amplitude of a signal specified. Of the two coupled differential amplifiers is only one designed for useful signal amplification of an unbalanced signal, while the other only a DC component of the single-ended signal processed.
  • the present invention relates to a multiplier circuit, designed for processing differential signals is and has a first input for feeding a first Input signal, a second input for supplying a second input signal, an output to provide a from the first and second input signal derived output signal, a first and a second transistor pair with Control inputs coupled to the first input, and with controlled routes, on the one hand with the exit the multiplier circuit are coupled and the other each form a current input has.
  • Such Multiplier circuit is described in Coue D. et al: "A Four-quadrant Subthreshold Mode Multiplier for Analog Neural Network Applications "IEEE TRANSACTIONS ON NEURAL NETWORKS, IEEE INC, NEW YORK, US, Vol. 7, No. 5, September 1, 1996 (1996-09-01), Pages 1212-1219, XP000635147 ISSN: 1045-9227.
  • the object of the present invention is a multiplier circuit specify that for use in vector modulators is suitable and improved in a simple structure Has noise properties.
  • multiplier circuit comprising the features of the present claim 1.
  • At least a current mirror for feeding the to be transmitted Use signal provided. This allows the at the beginning Gilbert's described multiplier cell Differential amplifier, with the useful signal to be transmitted is controlled, omitted.
  • Power sources connectable on the input side to the current mirror have a much higher compared to differential amplifiers Linearity with significantly lower supply current on.
  • the feedback resistances of the differential amplifier can be used be dispensed so that the noise properties the present mixer circuit significantly improved are.
  • a further reduction in the noise of the present multiplier circuit can by reducing the Kanalweitezu Channel length ratio of the current mirror transistors achieved become.
  • a filter circuit for filtering the second Input of the multiplier circuit feedable second input signal provided with a current output connected to the Input of the at least one current mirror is connected.
  • the output side anyway usually have a current output. hereby can with advantage this current output of the low-pass filter with coupled to the inputs of the current mirror of the multiplier be such that a conversion of the output current of the filter in a voltage, which then the conventional Gilbert multiplier cell can be fed, can be avoided. hereby can the noise characteristics, the electricity needs as well the linearity properties are further improved.
  • the filter circuit comprises a low-pass filter.
  • the power source for supplying the second signal input of the mixer namely the linear Input, which in any case preferred in the output stage of the baseband low-pass filter provided power source.
  • Invention is provided a voltage controlled current source, the current output to the input of the at least one Current mirror is coupled.
  • the control voltage which can be supplied to the voltage-controlled current source for example, represents a mixer feedable Baseband signal in a mobile radio transmitter. If this Signal is present as a voltage signal, can with the described Voltage-controlled current source, which is a voltage-current converter with downstream current mirror for formation represents the second input of the analog multiplier, under Maintaining improved linearity and noise properties as well as the lower power requirement of the present Multiplier circuit a voltage input high Input resistance may be provided at the second input.
  • the at least one current mirror as Diode switched input transistor, which has a current mirror output transistor is downstream.
  • the Channel width to channel length ratios of the current mirror transistors may be a desired current gain, that is a desired transmission ratio of the current mirror achieved become.
  • Invention is between input and output transistor provided a low-pass filter of the current mirror, which input coupled with output transistor.
  • Invention is the multiplier circuit for processing formed differential signals.
  • Figure 1 shows a multiplier circuit with one for feeding a differential signal formed first Input 1, 2, the preferred one provided by an oscillator Local oscillator signal with one to be modulated Carrier frequency can be fed.
  • the first input 1, 2 is with each connected to a control input of each of a transistor 3, 4, 5, 6, in each case two transistors 3, 4; 5, 6 pairs interconnected with each other.
  • the high frequency output 9, 10 is for providing formed differential output signals.
  • the current input 7, 8 of the transistor pairs 3, 4; 5, 6 is over each a current mirror 11, 12; 13, 14 with a second entrance 15, 16 for supplying a second, to be multiplied Input signal connected.
  • the current mirrors 11, 12; 13, 14 each comprise a diode-connected input current mirror transistor 11, 13 and an output transistor 12, 14, with its control input to the control input of the Input current mirror transistor 11, 13 is connected.
  • the Current mirror transistors 11 to 14 are connected to a reference potential terminal 17 coupled via one load connection.
  • the output stage of a low-pass filter 18, which with his Output for carrying differential signals to the second Input 15, 16 of the multiplier circuit is connected.
  • the low-pass filter 18 is preceded by a digital / analog converter 19, which are usually called digital signals present, to be sent useful signals or components thereof to be sent useful signals, which for example from a Baseband processing chain are fed into analog signals transforms.
  • a digital / analog converter 19 which are usually called digital signals present, to be sent useful signals or components thereof to be sent useful signals, which for example from a Baseband processing chain are fed into analog signals transforms.
  • unwanted spectral components which before a Frequency mixing of the useful signal with a local oscillator signal filtered out with a carrier frequency with low-pass filter 18 can be.
  • FIG. 2 shows a further embodiment of the present invention Multiplier. It is at the second entrance 15, 16 for providing a current source for the current mirror transistors 11 to 14 instead of that provided in accordance with Figure 1 Low-pass filter 18 in Figure 2 each one with an operational amplifier formed voltage / current converter provided.
  • the construction of the multiplier circuit between the first Input 1, 2, second input 15, 16 and output 9, 10 corresponds in interconnection and function that already for Figure 1 explained and should therefore not at this point again be repeated.
  • At the second input 15, 16 is ever one driven by an associated operational amplifier 20, 21 Transistor 22, 23 each connected to a load terminal. Depending on a further load connection of the operational amplifier 20, 21 driven transistors 22, 23 is over a resistor 24 with a reference potential terminal 25th connected.
  • the resistors 24 operate as a power source and each serve to adjust the of the current mirrors 11th to 13 to be amplified electricity.
  • the inverting Inputs of the operational amplifiers 20, 21 are each for Forming a feedback with the load terminal of the Transistors 22, 23 connected to the resistor 24, 25 connected.
  • FIG. 3 shows a development of the multiplier circuit with voltage / current conversion according to Figure 2 in a realization the operational amplifier for voltage / current conversion and the rest of the circuit with MOS field effect transistors.
  • Structure and function of the multiplier circuit between first input 1, 2, output 9, 10, transistor pairs 3 to 6, as well as current input 15, 16 correspond to it apart from the Realization in MOS circuit technology the embodiments according to Figures 1 and 2 and are therefore intended at this point not be repeated again.
  • the current mirror branches 11 to 14 a development is provided to that between input current mirror transistors 11, 13 and output current mirror transistors 12, 14 each have an RC element as Low pass filter is interposed with a series resistor 28 and a reference potential terminal 17 to the resistance 28 downstream capacity 30.
  • FIG. 2 shows an embodiment in FIG the operational amplifier shown schematically in Figure 2 20, 21 shown with MOS field effect transistors.
  • the additional low-pass filters 29, 30 in the current mirrors 11, 12; 13, 14 lead advantageously to another Improvement of the noise characteristics of the multiplier circuit.
  • FIG. 4 shows the application per one of the invention Multiplier circuit 42, 43 each in an inphase and a quadrature branch I, Q of a transmission arrangement with complex-valued signal processing.
  • the transmission arrangement comprises a baseband module 44, with a block for digital signal processing 45, the digital, Baseband signals to be transmitted are of complex value, that is divided into an in-phase and a quadrature component I, Q, provides.
  • digital Signal is a low-pass filter 47 in each case in each case in the inphase and quadrature branch I, Q provided digital to analog converter 48 connected.
  • the low pass filter 47 are with their Outputs in turn to the useful signal inputs of the mixer 42, 43 connected.
  • the frequency mixer 42, 43 are for Formation of a vector modulator, each with a further Input, the local oscillator input, via a common Frequency divider 49 to a voltage controlled oscillator 50th connected, which provides the local oscillator signal.
  • the multipliers 42, 43 are common Summing node 51 for summing the high-frequency Output signals of the multiplier circuits 42, 43 linked, wherein the summing node 51, for example via a not shown antenna to be transmitted, high-frequency Signal provides.
  • the output at the summing node 51 has provided high-frequency signal a particularly large Signal-to-noise ratio on.
  • a longer battery or Akkumulator Screte-to-noise ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplitude Modulation (AREA)
  • Transmitters (AREA)
  • Amplifiers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Claims (7)

  1. Circuit multiplicateur comprenant
    une première entrée (1, 2) d'entrée d'un premier signal d'entrée ;
    une deuxième entrée (15, 16) constituée pour faire entrer un deuxième signal d'entrée sous la forme d'un signal de courant ;
    une sortie (9, 10) pour mettre à disposition un signal de sortie dérivé du premier et du deuxième signal d'entrée ;
    une première et une deuxième paires (3, 4, 5, 6) de transistors ayant des entrées de commande qui sont couplées à la première entrée (1, 2) et ayant des sections commandées qui sont couplées d'une part à la sortie (9, 10) du circuit multiplicateur et qui forment d'autre part, respectivement, une entrée (7, 8) de courant, le circuit multiplicateur étant conçu pour le traitement de signaux différentiels, caractérisé par
    au moins un miroir (11, 12) de courant qui est couplé du côté sortie à, respectivement, une sortie (7, 8) de courant d'une paire (3, 4, 5, 6) de transistors et du côté entrée à la deuxième entrée du circuit (15, 16) du circuit multiplicateur.
  2. Circuit multiplicateur suivant la revendication 1,
       caractérisé en ce qu'il est prévu un circuit (18) de filtrage du deuxième signal d'entrée qui, peut être envoyé à la deuxième entrée (15, 16) du circuit multiplicateur, comprenant une sortie de courant qui est reliée à l'entrée du au moins un miroir (11, 12) de courant.
  3. Circuit multiplicateur suivant la revendication 2,
       caractérisé en ce que le circuit (18) de filtrage comprend un filtre passe-bas ayant une source du courant du côté sortie.
  4. Circuit multiplicateur suivant la revendication 1,
       caractérisé en ce qu'il est prévu une source (20, 22) de courant commandée en tension comprenant une sortie de courant qui est couplée avec l'entrée du au moins un miroir (11, 12) de courant.
  5. Circuit multiplication suivant l'une des revendications 1 à 4,
       caractérisé en ce qu'au moins un miroir (11, 12) de courant comprend un transistor (11 ) d'entrée monté en diode, dont la borne de commande est couplée à une borne de commande d'un transistor (12) de sortie du miroir (11, 12) de courant.
  6. Circuit multiplicateur suivant la revendication 5,
       caractérisé en ce qu'il est prévu un filtre (29, 30) passe-bas ayant une entrée qui est couplée avec le transistor (11) d'entrée et ayant une sortie qui est couplée au transistor (12) de sortie du au moins un miroir (11, 12) de courant.
  7. Circuit multiplicateur suivant l'une des revendications 5 ou 6,
       caractérisé en ce que le transistor (11) d'entrée et le transistor (12) de sortie sont mis par, respectivement, une borne de réception commandée directement à un potentiel (17) de référence.
EP02752994A 2001-07-06 2002-07-03 Circuit multiplicateur Expired - Lifetime EP1405413B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10132802 2001-07-06
DE10132802A DE10132802A1 (de) 2001-07-06 2001-07-06 Multipliziererschaltung
PCT/DE2002/002427 WO2003005582A2 (fr) 2001-07-06 2002-07-03 Circuit multiplicateur

Publications (2)

Publication Number Publication Date
EP1405413A2 EP1405413A2 (fr) 2004-04-07
EP1405413B1 true EP1405413B1 (fr) 2005-02-02

Family

ID=7690837

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02752994A Expired - Lifetime EP1405413B1 (fr) 2001-07-06 2002-07-03 Circuit multiplicateur

Country Status (4)

Country Link
US (1) US20040174199A1 (fr)
EP (1) EP1405413B1 (fr)
DE (2) DE10132802A1 (fr)
WO (1) WO2003005582A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989835B (zh) * 2009-07-30 2013-04-03 晨星软件研发(深圳)有限公司 信号处理电路

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003016379A (ja) * 2001-06-29 2003-01-17 A&Cmos Communication Device Inc アナログ乗算回路
DE10334805B4 (de) * 2003-07-30 2005-07-07 Fachhochschule Karlsruhe-Hochschule für Technik, Anstalt des öffentlichen Rechts Analoge Multiplizierschaltung
DE10351606B3 (de) 2003-11-05 2005-05-25 Infineon Technologies Ag Hochfrequenz-Mischeranordnung
US7049882B2 (en) * 2004-02-03 2006-05-23 Broadcom Corporation Transmitter IF section and method enabling IF output signal amplitude that is less sensitive to process, voltage, and temperature
US7221300B2 (en) * 2004-05-21 2007-05-22 Texas Instruments Incorporated Digital-to-analog converter data rate reduction by interleaving and recombination through mixer switching
DE102005005332A1 (de) * 2005-01-28 2006-08-10 Atmel Germany Gmbh Mischstufe und Verfahren zur Mischung von Signalen verschiedener Frequenzen
TWI326965B (en) * 2007-01-30 2010-07-01 Mstar Semiconductor Inc Mixer
EP2218177B1 (fr) * 2007-11-09 2016-04-27 Hittite Microwave Corporation Amplificateur à gain variable
EP2218176B1 (fr) * 2007-11-12 2013-07-03 Hittite Microwave Norway AS Amplificateur à faible bruit
US8456236B2 (en) * 2008-05-19 2013-06-04 Hittite Microwave Norway As Multiple input variable gain amplifier
CN101873102A (zh) * 2010-04-30 2010-10-27 北京利云技术开发公司 一种高线性度且适合低电压工作的上变频混频器
GB2539457A (en) 2015-06-16 2016-12-21 Nordic Semiconductor Asa Voltage regulators
US10700640B2 (en) * 2018-06-11 2020-06-30 The Regents Of The University Of California Harmonic-based nonlinearity factorization scheme to facilitate up-conversion mixer linearity
US10852182B2 (en) * 2018-06-29 2020-12-01 Osram Opto Semiconductors Gmbh Ambient light detector, detector array and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3835499A1 (de) * 1988-10-19 1990-04-26 Philips Patentverwaltung Schaltungsanordnung zum einstellen der amplitude eines signals
JP3300534B2 (ja) * 1993-09-13 2002-07-08 株式会社東芝 電子回路
JP2891297B2 (ja) * 1996-09-30 1999-05-17 日本電気株式会社 電圧電流変換回路
FR2769388B1 (fr) * 1997-10-07 2001-08-03 Korea Telecomm Authority Multiplieur et synapse de reseau neuronal utilisant un miroir de courant comportant des transistors a effet de champ mos de faible puissance
FI107656B (fi) * 1998-10-30 2001-09-14 Nokia Mobile Phones Ltd Alipäästösuodin lähettimessä ja matkaviestin
JP2001344559A (ja) * 2000-05-30 2001-12-14 Matsushita Electric Ind Co Ltd アナログ乗算回路および可変利得増幅回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989835B (zh) * 2009-07-30 2013-04-03 晨星软件研发(深圳)有限公司 信号处理电路

Also Published As

Publication number Publication date
DE50202182D1 (de) 2005-03-10
EP1405413A2 (fr) 2004-04-07
WO2003005582A3 (fr) 2003-03-13
DE10132802A1 (de) 2002-11-14
WO2003005582A2 (fr) 2003-01-16
US20040174199A1 (en) 2004-09-09

Similar Documents

Publication Publication Date Title
EP1405413B1 (fr) Circuit multiplicateur
DE4420447C2 (de) Phasenschieberschaltung und Quadraturnetzwerk
DE4126080C2 (de) Mischersystem für einen Direktumsetzungsempfänger
DE69834875T2 (de) Frequenzumsetzungsschaltung
DE10351606B3 (de) Hochfrequenz-Mischeranordnung
DE69934020T2 (de) Pll-schaltung und funkbetriebenes kommunikationssendegerät mit einer phasenregelschleife
DE69623292T2 (de) Bipolarer analogmultiplizierer für niederspannungsanwendungen
EP0341531A2 (fr) Amplificateur à large bande réglable
DE3875713T2 (de) Oszillatorschaltung und quadratur netzwerk fuer radioempfaenger.
DE10245609B4 (de) Mischvorrichtung
DE69802158T2 (de) Doppelgegentaktmodulator und vier Phasen Modulationseinrichtung
EP1481487B1 (fr) Dispositif d'emission
EP1407543A2 (fr) Dispositif d'emission a regulation de puissance
DE10344876B3 (de) Signalverarbeitungseinrichtung, insbesondere für den Mobilfunk
EP1119903A1 (fr) Circuiterie pour melanger un signal d'entree et un signal d'oscillateur
DE3412191A1 (de) Integrierbare empfaengerschaltung
DE10210708B4 (de) Mobilfunkgerät mit einer Schaltungsanordnung zur Frequenzumsetzung
EP1407416B1 (fr) Circuit multiplicateur
DE2646035A1 (de) Verstaerkerschaltung fuer wechselspannung
DE69509287T2 (de) Oszillator, Synthetisierer-Abstimmschaltung und den Oszillator verwendende AM synchrone Detektorschaltung
EP1527524A1 (fr) Systeme de transmission, en particulier pour la radiotelephonie mobile
DE2105431C3 (de) Verstärkende Doppelgegentakt-Mischstufe
EP1421677B1 (fr) Systeme emetteur, notamment pour la telephonie mobile
DE102004002826B4 (de) Schaltung zur Änderung einer Frequenz
DE3412190A1 (de) Integrierbare empfaengerschaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040123

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR

RIC1 Information provided on ipc code assigned before grant

Ipc: 7H 03J 1/00 B

Ipc: 7G 06F 7/52 A

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: GERMAN

REF Corresponds to:

Ref document number: 50202182

Country of ref document: DE

Date of ref document: 20050310

Kind code of ref document: P

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20050412

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050712

Year of fee payment: 4

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050913

Year of fee payment: 4

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

ET Fr: translation filed
26N No opposition filed

Effective date: 20051103

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070201

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060703

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20070330

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060731