EP1407416B1 - Circuit multiplicateur - Google Patents

Circuit multiplicateur Download PDF

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Publication number
EP1407416B1
EP1407416B1 EP02753008A EP02753008A EP1407416B1 EP 1407416 B1 EP1407416 B1 EP 1407416B1 EP 02753008 A EP02753008 A EP 02753008A EP 02753008 A EP02753008 A EP 02753008A EP 1407416 B1 EP1407416 B1 EP 1407416B1
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EP
European Patent Office
Prior art keywords
signal
multiplier
transistors
transistor
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP02753008A
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German (de)
English (en)
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EP1407416A2 (fr
Inventor
Günther TRÄNKLE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function

Definitions

  • the present invention relates to a multiplier circuit.
  • Analog multiplier circuits come in, for example Mass products of mobile communications, such as mobile phones, are used. Both in the sending and in the receiving direction is in it Usually an analog circuit is provided, which all required Circuit components for coupling the digital Signal processing to a radio interface includes. ever according to modulation method is a carrier signal in the transmission direction modulated and received in the receive direction Radio frequency signal linked to a beat signal and translated into a low frequency signal.
  • multiplier circuits For frequency conversion in both transmit and receive directions become analog multiplier circuits in one so-called mixer operation used. Further application examples for analog multiplier circuits are included the usual in modern mobile radio stations and receivers Splitting the signals into a complex-valued signal with a Inphase and a quadrature component. For this are the Multipliers feedable overlay respectively Carrier signals required, with a pair of signals which each other has an exact phase offset of 90 °. multiplier circuits, especially those with similar Signal inputs, such as passive ring mixer, allow a particularly precise monitoring of the phase offset of 90 °.
  • Analog multiplier circuits in the described fields of application are subject to demands for ever lesser Supply voltage, low space requirement and manufacturability in cost-effective monolithic integration.
  • the object of the present invention is a multiplier circuit specify which with high accuracy for monitoring the 90 ° phase difference of high frequency signals can be used.
  • the object is achieved by a multiplier circuit solved, having the features of the claim 1.
  • the indicated four-quadrant multiplier circuit has two inputs for feeding one each to be multiplied Signal due to the same source impedance of the Signal sources have the same electrical properties.
  • control inputs of the multiplier core are preferably the Control inputs of the transistors, which cross-coupled the two Form transistor pairs.
  • the present multiplier circuit with a low Number of transistor levels is buildable, it can be used for operating voltages ⁇ 2.5V are used.
  • the control of the multiplier core with the two cross-coupled Transistor pairs, which advantageously as Differential amplifiers, which are cross-coupled, interconnected are, takes place for a first input signal via the Common-mode input signal of the respective transistor pair and for a second input signal via the respective differential Modulation of the two transistor pairs.
  • the common mode modulation of the transistor pairs takes place not, as with the Gilbert cell, over the common Emitter node and its common mode, but the Control with both input signals accesses the control inputs of the transistors, so that same source impedances and thus the same electrical properties of the two inputs can be achieved.
  • the present multiplier circuit thus combines the Advantages of an active Gilbert multiplier cell, namely the monolithic integrability, with the advantages of passive ring mixer circuit, namely the high electrical Symmetry of the two inputs.
  • the Multiplier core a first and a second transistor pair, which are interconnected in a crosstalk, wherein the pairs of transistors each have a first and a second Transistor with one control input each include.
  • the signal sources control the multiplier core at the control inputs the transistors so that with the first to multiplying signal a reversal between the first and the second transistor pair and to be multiplied by the second Signal a reversal between the first and second transistor each effected in both transistor pairs is.
  • Invention is the first signal source with the multiplier core coupled to the signal supply such that the control inputs of first and second transistors of the first transistor pair the first signal to be multiplied unchanged and the control inputs of the first and second transistors of the second transistor pair, the first signal to be multiplied is supplied inverted, and that the control inputs of the first transistors of the first and second transistor pair the second signal to be multiplied unchanged and the control inputs the second transistors of first and second Transistor pair the second signal to be multiplied inverted is supplied.
  • the transistor pairs of the Multiplier core can with the described wiring their tax receipts by means of the usually anyway symmetrical signals present signals to be multiplied be driven differentially in a simple manner, wherein those supplied by the first and second signal sources Overlay input signals according to the present principle.
  • Invention are the control terminals of the transistors of Transistor pairs of the multiplier core their base or gate terminals.
  • Invention are each emitter or source terminals of first and second transistors for forming one transistor pair each connected with each other.
  • Invention include the first and the second signal source one differential amplifier each with two inputs to Supply of the signals to be multiplied and four outputs for connection to the control inputs of the transistors.
  • the two inputs of the differential amplifiers form one each symmetrical signal input for feeding the to be multiplied Signal as a differential signal.
  • the outputs of the differential amplifiers are for provision the one required to drive the multiplier core Overlay signals with four outputs each, that is formed with two symmetrical output terminal pairs, with two inverting and two non-inverting connections.
  • Invention is the differential amplifier of the first signal source with a supply potential terminal and the differential amplifier the second signal source with a reference potential terminal coupled.
  • these can either be connected to a reference potential terminal, for example, ground, or both to a supply potential terminal be coupled, or as described and preferably in high frequency application of the multiplier as a mixer each provided one of the differential amplifier for Providing the first and second signal source with supply or coupled to reference potential terminal be.
  • the outputs, such as the collector terminals the signal source differential amplifier, are with the Control inputs of the multiplier core connected.
  • the division into equal signal streams for the first signal source and in the same signal streams for the second signal source can preferably be with surface-parallel transistors or in addition with negative feedback resistances between the emitter terminals that of the paired transistors of the signal source differential amplifiers and a connected power source be achieved.
  • Invention are first and second signal source as voltage / current converter educated.
  • Signals to be multiplied are usually in the form of voltage signals before, while driving the actual Multiplier core advantageously via current signals can. Therefore, the described embodiment of the signal sources advantageous as voltage / current converter.
  • the multiplier core of the present multiplier circuit which is provided with reference numeral 1, comprises two as Differential amplifier interconnected bipolar transistor pairs, where a first transistor pair a first transistor 2 and a second transistor 3 and a second transistor pair a first transistor 4 and a second transistor 5 comprises.
  • First transistor pair 2, 3 and second transistor pair 4, 5 are interconnected in a cross-coupling.
  • the two collector terminals of the first transistors 2, 4 and the collector terminals of the second transistors 3, 5 each directly connected.
  • Farther are the emitter terminals for forming the differential amplifiers the transistors 2, 3 and the transistors 4, 5, which the first and second transistor pair form, directly connected.
  • a first and a second signal to be multiplied are at the as basic connections trained control terminals of the transistors 2 to 5 coupled.
  • the common emitter node of Transistor pairs 2, 3; 4, 5 are each a power source 6, 7th connected to a reference potential terminal 8. Furthermore is a negative feedback resistor 9 is provided, the two Emitter nodes of the transistor pairs 2, 3; 4, 5 connects to each other. In alternative embodiments, this negative feedback resistance 9 omitted.
  • First and second signal sources for driving the multiplier core 1 via the control inputs of the transistors 2 to 5 with first and second signal to be multiplied are in simplified circuit diagram of Figure 1 as power sources 10, 11, 13, 14 with parallel impedance 12 shown.
  • the control input that is the base terminal of the first Transistor 2 of the first transistor pair 2, 3 a the first signal representing controlled, to be multiplied
  • Current source 10 connected to reference potential terminal 8.
  • Parallel to the current source 10 is a further current source 11 which represents the second signal to be multiplied.
  • a source impedance 12 a resistor is provided, which is connected in parallel with the current sources 10, 11.
  • the control terminal of the first transistor 4 of the second transistor pair 4, 5 is the source impedance 12 and a to parallel power source 14 and also in parallel switched current source 13 connected to reference potential 8. While the current source 14 is the inverted, from represents the first signal derived from the signal to be multiplied, current source 13 is the inverted, as mentioned above second signal to be multiplied of the multiplier ready.
  • the first signal source of the present multiplier comprises Accordingly, the current sources 10, 14, while the second signal source the current sources 11, 13 comprises.
  • this can preferably for monitoring the exact phase difference of 90 ° for local oscillator signals as well as high-frequency mixer be used.
  • Figure 2 shows the known implementation of a current source with parallel impedance in an equivalent voltage source with series impedance.
  • a current source 15 with a short-circuit current I k and parallel-connected source impedance 16 is electrically equivalent to a voltage source 17 with an open circuit voltage U L and a series impedance 16.
  • the representations of the signal sources 10 to 14 according to Figure 1, which for clarity and to facilitate understanding Current sources are drawn, can therefore be implemented in a simple manner according to Figure 2 in voltage sources which have equivalent electrical properties.
  • no-load voltage and source impedance Ohm's law can be used.
  • FIG. 2b shows a development of the principle of FIG. 2a applied to two superimposed current or voltage sources.
  • Figure 3 shows an embodiment of an inventive Multiplier circuit in a development of the circuit according to FIG. 1.
  • the multiplier core 1 with the transistor pairs 2, 3; 4, 5 corresponds in structure and operation of the of Figure 1 and is therefore not described again here become.
  • a current source 18 is provided, via each a resistor 19 to the emitter node of Differential amplifier 2, 3; 4, 5 and with a reference potential terminal 8 is coupled.
  • first and second signal source for feeding provide the first and second signals to be multiplied, is ever a resistor 20 between the control input the transistors 2, 3, 4, 5 and a supply potential terminal 21 switched.
  • All resistors 20 have the same resistance value.
  • FIG. 4 and FIG. 5 each show exemplary implementation possibilities for the power sources 10, 11, 13, 14, the means to form the first and second signal sources.
  • FIG. 4 shows by way of example the first signal source 10, 14, which, however, as a second signal source 11, 13 mutatis mutandis can be used.
  • Figure 4 shows a differential amplifier each with doubly executed transistors 24, 25; 26, 27, the input side connected in parallel are. At base terminals of the transistors 24, 25, 26, 27 is as a symmetrical signal, the first signal to be multiplied applied.
  • the emitter terminals of the bipolar transistors 24 to 27 are to form a differential amplifier over each an emitter resistor 28 to a common emitter node connected, via a current source 29 with a reference potential terminal 8 is connectable.
  • the collector connections form current outputs of the transistors, wherein the collector terminal of the transistor 24, the current source output Is1, the Collector terminal of the transistor 25 the electrically equivalent Provide current output Is1 'and complementary, that is, inverted current outputs Is1 ⁇ and equivalent Is1 ⁇ 'from the collector terminals of npn bipolar transistors 26, 27 are provided. Because the emitter resistors 28 all have the same resistance, and these Source impedance for both the first and second signal sources can be used, both with a circuit can be realized according to Figure 4, are the present Principle underlying symmetric properties of Input gates of the circuit achievable.
  • the emitter resistors 28 according to FIG. 4 favor the exact ones Halving the current to the current outputs Isl, Is1 '.
  • FIG. 5 shows a further exemplary embodiment of the first embodiment and second signal source used to form the signal sources 10, 11, 13, 14 according to FIG. 3 as an exemplary alternative to a signal source according to Figure 4 can be used.
  • a differential amplifier as shown in Figure 4 respectively two npn bipolar transistors 24, 25, 26, 27 emitter side with each other, and via a power source 29 with a reference or Supply potential connection coupled.
  • Base side the transistors 24 to 27 is a first or second to multiplying signal, each as a balanced signal, fed.
  • the Emitter resistors 28 omitted.
  • To provide the required Symmetry have the integrated transistors 24th to 27 the same emitter areas A on.
  • FIG. 6 shows a further exemplary embodiment of a multiplier circuit in an alternative embodiment according to FIG. 3.
  • the circuit according to FIG. 6 is in construction and function largely with the circuit of Figure 3 match. Differences exist only in the missing ones Emitter resistors 19 and in replacing the power source resistors 20 by transistor diodes 33th Accordingly, respectively diode-connected transistors 33 between the supply potential terminal 21 and control inputs of the multiplier core transistors 2 to 5 or current source outputs 10, 11, 13, 14 switched.
  • the diodes 33 form a logarithmic Load to linearize the tanh characteristic, then, if no emitter resistors at emitter nodes of the transistor pairs 2, 3; 4, 5 are provided.
  • FIG. 7 shows a further exemplary embodiment of a multiplier circuit according to the present principle, which starting from the multiplier circuit according to FIG. 1 as High-frequency mixer circuit is developed.
  • the multiplier core 1 corresponds to the circuit according to FIG. 7 in structure and function as previously explained and will therefore not be discussed again at this point. Likewise, the emitter-side power supply with negative feedback resistance 9 already described in Figure 1 and is therefore also not repeated here again.
  • the peculiarity of the multiplier circuit according to FIG. 7 lies in the division of the first and second signal source forming differential amplifier 34, 35; 24 to 27 on the one handlongedspotehtialseite and the other on the reference potential side.
  • the first signal source 34, 35 with the associated Collector resistors 32 corresponds to an emitter follower circuit.
  • the second signal source 24 to 27 with the Emitter resistors 28 corresponds in construction and mode of action the signal source according to FIG 4.
  • first signal input 37, 38 which is designed as a high-frequency output is a Redirection from the first differential amplifier 2, 3 to the second Differential amplifier 4, 5 causes.
  • Supply potential connection 21 is via a voltage source 36 connected to reference potential 8.
  • the emitter terminal of the Transistor 34 is each a resistor 32 to the control inputs the transistors of the first transistor pair 2, 3; and the emitter terminal of the transistor 35 via one each similar resistor 32 to the two control inputs of second differential amplifier 4, 5 of the multiplier core 1 connected.
  • each within the transistor pairs are transistors 24 to 27 on the collector side according to the present principle to the transistor pairs 2, 5 and 3, 4 connected.
  • the transistors 24 to 27 of the second Signal source via a respective emitter resistor 28 to a common emitter node and continue via a power source 29 connected to reference potential terminal 8 while a second signal input 39, 40, the second to be multiplied Signal can be fed to each of a base terminal of the Transistors 24 to 27 is coupled.
  • the multiplier is a receive demodulator designed, the at its first input terminal pair 37, 38 a radio frequency signal from an antenna RF can be fed and at the second input terminal pair 39, 40 a differential local oscillator signal LO can be supplied as an overlay signal.
  • a differential local oscillator signal LO can be supplied as an overlay signal.
  • At the output 22 of the multiplier core 1 is a downmixed or Demodulated useful signal derivable.
  • the multiplier circuit according to FIG. 7 can be supplied with supply voltages ⁇ 3 V operated at a current requirement ⁇ 3 mA become.
  • the transistors operate 34, 35 as a voltage follower and generate at their emitter points low-impedance voltage control node.
  • the necessary quiescent current the voltage follower transistors 34, 35 is off the currents added to the constant current of the common mode current paths of the voltage / current transformer differential amplifier won the second signal source.
  • the Multiplier circuit At a noise figure NF (noise figure) of 20 dB, the Multiplier circuit according to Figure 7, a gain of 6 dB.
  • the 2nd and 3rd order input intercept points (IIP) lie at +65 dBm or 20 dBm or greater.
  • FIG. 8 shows an alternative to the control with the transistors 34, 35 according to FIG. 7, their voltage drive replaced by a current control according to Figure 8 is.
  • the transistors connected as emitter followers are 34, 35 of the first signal source of Figure 7 replaced by a negative feedback differential amplifier.
  • This differential amplifier comprises two bipolar transistors 30, 31, whose Collector connections via one high-frequency resistor 41 are connected to the supply potential terminal 21.
  • the collector terminals are each a resistor 32, as drawn in Figure 7, with the four control inputs of the multiplier core 1.
  • the basic connections the transistors 30, 31 is above the balanced one Input 37, 38, a high-frequency signal can be supplied.
  • the emitter connections the transistors 30, 31 are via a negative feedback resistor 42 with each other and each have a power source 43 connected to the reference potential terminal 8.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplitude Modulation (AREA)
  • Amplifiers (AREA)
  • Networks Using Active Elements (AREA)
  • Manipulation Of Pulses (AREA)

Claims (9)

  1. Circuit multiplicateur comprenant
    un noyau (1) multiplicateur ayant deux paires (2, 3; 4, 5) de transistors couplés transversalement et ayant des entrées de commande,
    une première source (10, 14) de signal, à laquelle peut être relié un premier signal à multiplier, ayant une sortie, qui est reliée aux entrées de commande du noyau (1) multiplicateur, et avec une première impédance de la première source (12) de circuit de signal, et
    une deuxième source (11, 13) de signal, à laquelle peut être envoyé un deuxième signal à multiplier, ayant une sortie, qui est reliée aux entrées de commande du noyau (1) multiplicateur, et avec une deuxième impédance de la deuxième source (12) de signal, le circuit multiplicateur étant caractérisé par le fait que ladite deuxième impédance est égale à la première impédance (12) de façon à former deux entrées équivalentes électriquement du circuit multiplicateur.
  2. Circuit multiplicateur suivant la revendication 1,
    caractérisé en ce que le noyau (1) multiplicateur comprend une première paire (2, 3) de transistors et une deuxième paire (4, 5) de transistors, qui sont couplés transversalement entre elles et qui comprennent respectivement un premier (2, 4) et un deuxième (3, 5) transistors ayant respectivement une entrée de commande et en ce que les sources (10, 11, 13, 14) de signal commandent le noyau (1) multiplicateur de façon à provoquer par le premier signal à multiplier une inversion entre la première paire (2, 3) de transistors et la deuxième paire (4, 5) de transistors et par le deuxième signal à multiplier une inversion entre les premier (2, 4) transistors et les deuxièmes (3, 5) transistors.
  3. Circuit multiplicateur suivant la revendication 2,
    caractérisé en ce que la première source (10, 14) de signal est couplée au noyau (1) multiplicateur pour l'envoi d'un signal de façon à ce que,
    le premier signal à multiplier soit envoyé sans modification aux entrées de commande par le premier et le deuxième transistors (2, 3) de la première paire de transistors, et
    le premier signal à multiplier soit envoyé de manière inversée aux entrées de commande par le premier et le deuxième transistors (4, 5) de la deuxième paire de transistors et en ce que,
    le deuxième signal à multiplier soit envoyé sans modification aux entrées de commande des premiers transistors (2, 4), et
    le deuxième signal à multiplier soit envoyé de manière inversée aux entrées de commande des deuxièmes transistors (3, 5) par la première et la deuxième paire de transistors.
  4. Circuit multiplicateur suivant l'une des revendications 1 à 3,
    caractérisé en ce que les bornes de commande des transistors (2, 3; 4, 5) des paires de transistors du noyau (1) multiplicateur sont des bornes de base ou des bornes de grille.
  5. Circuit multiplicateur suivant l'une des revendications 1 à 4,
    caractérisé en ce que les bornes d'émetteur ou de source des premiers et deuxièmes transistors (2, 3; 4, 5) sont reliées respectivement entre elles pour former une paire de transistors.
  6. Circuit multiplicateur suivant l'une des revendications 1 à 5,
    caractérisé en ce que la première et la deuxième sources (10, 14; 11, 13) de signal comprennent respectivement un amplificateur (24, 25, 26, 27) différentiel ayant respectivement deux entrées pour entrer des signaux à multiplier et quatre sorties pour la connexion aux entrées de commande des transistors du noyau (1) multiplicateur.
  7. Circuit multiplicateur suivant la revendication 6,
    caractérisé en ce que l'amplificateur différentiel de la première source (34, 35) de signal est couplée à une borne (21) de potentiel d'alimentation et l'amplificateur différentiel de la deuxième source (30, 31) de signal à une borne (8) de potentiel de référence.
  8. Circuit multiplicateur suivant la revendication 6 ou 7,
    caractérisé en ce que l'amplificateur différentiel comprend respectivement quatre transistors (24, 25, 26, 27) auxquels est raccordée respectivement une résistance (28) d'émetteur.
  9. Circuit multiplicateur suivant l'une des revendications 1 à 8,
    caractérisé en ce que la première et la deuxième sources (10, 11, 13, 14) de signal sont constituées sous la forme d'un convertisseur tension/courant.
EP02753008A 2001-07-17 2002-07-10 Circuit multiplicateur Expired - Lifetime EP1407416B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10134754 2001-07-17
DE10134754A DE10134754A1 (de) 2001-07-17 2001-07-17 Multipliziererschaltung
PCT/DE2002/002525 WO2003009078A2 (fr) 2001-07-17 2002-07-10 Circuit multiplicateur

Publications (2)

Publication Number Publication Date
EP1407416A2 EP1407416A2 (fr) 2004-04-14
EP1407416B1 true EP1407416B1 (fr) 2005-06-01

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Family Applications (1)

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EP02753008A Expired - Lifetime EP1407416B1 (fr) 2001-07-17 2002-07-10 Circuit multiplicateur

Country Status (4)

Country Link
US (1) US7026857B2 (fr)
EP (1) EP1407416B1 (fr)
DE (2) DE10134754A1 (fr)
WO (1) WO2003009078A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9396362B2 (en) * 2011-04-25 2016-07-19 Citizen Holdings Co., Ltd. Analog multiplier circuit, variable gain amplifier, detector circuit, and physical quantity sensor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519444B2 (fr) * 1972-12-29 1980-05-26
DE3840855C2 (de) 1988-12-03 1996-07-18 Telefunken Microelectron Phasenvergleicher
US5379457A (en) * 1993-06-28 1995-01-03 Hewlett-Packard Company Low noise active mixer
DE4420376C2 (de) 1993-09-22 1998-09-17 Hewlett Packard Co Quadraturmodulator
JPH08265047A (ja) * 1995-01-24 1996-10-11 Matsushita Electric Ind Co Ltd 周波数変換回路
JP2888212B2 (ja) * 1996-03-08 1999-05-10 日本電気株式会社 バイポーラマルチプライヤ
DE19844970C2 (de) * 1998-09-30 2001-02-22 Siemens Ag Schaltungsanordnung zum Mischen eines Eingangssignals und eines Oszillatorsignals miteinander

Also Published As

Publication number Publication date
WO2003009078A2 (fr) 2003-01-30
DE50203287D1 (de) 2005-07-07
US20040155694A1 (en) 2004-08-12
EP1407416A2 (fr) 2004-04-14
WO2003009078A3 (fr) 2003-04-03
DE10134754A1 (de) 2003-02-06
US7026857B2 (en) 2006-04-11

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