EP1336136B1 - Verfahren zum abgleichen eines bgr-schaltkreises und bgr-schaltkreis - Google Patents
Verfahren zum abgleichen eines bgr-schaltkreises und bgr-schaltkreis Download PDFInfo
- Publication number
- EP1336136B1 EP1336136B1 EP01997727A EP01997727A EP1336136B1 EP 1336136 B1 EP1336136 B1 EP 1336136B1 EP 01997727 A EP01997727 A EP 01997727A EP 01997727 A EP01997727 A EP 01997727A EP 1336136 B1 EP1336136 B1 EP 1336136B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- differential amplifier
- circuit
- voltage differential
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 16
- 230000001105 regulatory effect Effects 0.000 claims description 2
- 238000009966 trimming Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Definitions
- the invention relates to a method for comparing a BGR circuit and one that can be compared according to the method BGR circuit.
- Circuits which are one of temperature and supply voltage fluctuations generate independent, constant output voltage, are becoming more diverse in semiconductor circuit technology Way needed. They are both in analog, digital as well as used in analog-digital mixed circuits.
- a common type of such circuits are the so-called BGR circuits (band gap reference circuits).
- the basic principle of a BGR circuit is two Partial signals (voltages or currents) that are opposite Have temperature behavior to add. During one of the both partial signals falls with increasing temperature, increases the other partial signal with increasing temperature. From the The sum of the two partial signals is then over a certain Range derived from constant temperature output voltage.
- the output voltage of a BGR circuit is made according to the usual Language usage in the following also as reference voltage designated.
- a known problem with BGR circuits is that circuits of the same series are different Have reference voltages. It is therefore common in practice required the BGR circuit to achieve one sufficient accuracy with regard to the desired absolute Reference voltage value and / or the desired temperature constancy the reference voltage.
- BGR circuits have both passive components, e.g. resistors, as well as active components, mostly in the form of a Differential or operational amplifier. A deviation from the Reference voltage from the ideal, calculated value and from a constant temperature behavior goes to a lack Adaptation of passive and active components.
- the goal of balancing a BGR circuit is to on the one hand a deviation of at a certain temperature obtained reference voltage value from a with respect to minimize this temperature calculated value and on the other hand the temperature characteristic of the reference voltage optimize, i.e. a flat voltage-temperature characteristic to obtain.
- offset compensation is used directly on the amplifier generating the offset.
- Most operational amplifiers have suitable ones for this Control inputs.
- Through offset compensation becomes the dominant error portion of the deviation between the reference voltage value obtained at the output of the circuit and the calculated value is eliminated.
- the disadvantage is that there is usually a residual deviation of the sizes mentioned remains and that no optimal temperature characteristics the reference voltage is obtained, but on the contrary often the temperature characteristic through this step even is deteriorating.
- the output voltage of the circuit i.e. the reference voltage
- the circuit is set directly to the calculated value. This way, at the temperature at which the setting the correct voltage value is achieved.
- U.S. Patent No. 6,118,264 A is a BGR circuit described with a balancing device is connected.
- the balancing device generates a compensation voltage, which on the from the BGR circuit provided BGR voltage is added, creating a reference voltage is produced.
- the compensation voltage has over certain temperature ranges to the BGR voltage opposite temperature characteristics. Total results this results in an improved temperature characteristic of the reference voltage.
- the invention is based, an easy to carry out the task To specify adjustment procedures for BGR circuits, with which there is a good temperature stability of the reference voltage and a good match of the reference voltage value with an expected or calculated voltage value let achieve.
- the invention further aims to provide one easy to match BGR circuitry.
- the adjustment method according to the invention comprises Claim 1 two consecutive adjustment steps: In a first adjustment step, an offset adjustment is carried out of the voltage difference amplifier at a predetermined temperature carried out. In a second adjustment step then the value of the reference voltage, which at the first Matching step has been obtained to the predetermined (i.e. calculated) value of the reference voltage for this circuit set.
- the particular advantage of the method according to the invention lies in that the two adjustment steps in one and the same Temperature are carried out and (nevertheless) an adjustment both in terms of the absolute value and the Temperature characteristic of the reference voltage obtained becomes.
- voltage differential amplifier is every type an amplifier meant to amplify a voltage difference is designed.
- the term includes a differential amplifier and an operational amplifier.
- Step the partial steps of short-circuiting the inputs of the voltage differential amplifier and regulating the output voltage of the Differential voltage amplifier to a predetermined voltage value includes.
- the specified voltage value can in particular be the common mode voltage, which is the mean of the positive and negative potential the operating voltage of the voltage differential amplifier is.
- the voltage difference amplifier is used for the offset adjustment preferably operated as a comparator.
- the inputs of the voltage differential amplifier through the Disconnect the first switching means from the external circuit and short circuit by the second switching means can then short-circuit compensation of the voltage difference amplifier for offset correction become. Then the inputs of the Differential voltage amplifier by the first switching means reconnect to the external wiring and the short circuit the inputs can be canceled by the second switching means become.
- the circuit can now by adjusting the resistance of the at least one Component with adjustable resistance to balance the Output voltage of the circuit to the specified value Reference voltage can be carried out. Through this comparison is caused to be within a certain range around the predetermined Temperature around an almost constant, i.e. temperature-independent Sets reference voltage.
- 1A and 1B illustrate the two essential effects, the for the occurrence of discrepancies between the received Reference voltage and the calculated reference voltage are responsible.
- Fig. 1A shows the case where that of an unbalanced one BGR circuit output reference voltage plotted on the Y axis over the entire temperature range considered (X-axis) either higher (reference voltage curve RS +) or lower (reference voltage curve RS-) than the calculated one ideal reference voltage curve RS0 runs, but with respect on their temperature behavior an optimally flat and regarding the room or operating temperature TR symmetrical course having.
- This effect is mainly due to a Offset in the voltage differential amplifier causes. He will be in hereinafter referred to as offset error and is usually the dominant proportion of errors in unbalanced BGR circuits.
- Fig. 1B shows the case where the reference voltage is either a characteristic increasing with increasing temperature (Reference voltage curve RSd +) or one with increasing temperature falling characteristic (reference voltage curve RSd-) having. This effect is mainly due to a lack of adjustment of the passive components of the BGR circuit. In the following, it is also called a temperature characteristic error designated.
- the reference voltage curve RSOT is both with an offset error as well as a temperature characteristic error afflicted.
- the offset error is eliminated so that the reference voltage curve RSOT parallel to the X axis in the direction of calculated ideal reference voltage curve RS0 shifted becomes.
- this step does not result in the optimal one Temperature characteristic (i.e. the resulting reference voltage curve RST differs in their temperature characteristics still from the calculated ideal reference voltage curve RS0) because the errors of the passive components of the BGR circuit cannot be compensated.
- FIG. 3 illustrates the second adjustment step according to the invention AS2.
- AS2 the temperature characteristic error the reference voltage curve RST is eliminated by an adjustment the reference voltage to the specified value of the reference voltage performed at room or operating temperature TR becomes.
- This will make the temperature characteristic of the reference voltage curve RST to the calculated ideal reference voltage curve RS0 adjusted so that both reference voltage curves then have the same course.
- Fig. 4 shows a BGR circuit according to the invention, which suitable for carrying out the method according to the invention and is designed.
- the inverting input of an operational amplifier OP1 is via a switch S1 with a node K1 of a first circuit branch of an external circuit of the operational amplifier OP1 connected.
- the non-inverting Input of the operational amplifier OP1 is via a switch S2 with a node K2 of a second Circuit branch of the external circuitry of the operational amplifier OP1 in connection.
- the two circuit branches extend each have a common fixed potential, especially a mass VSS, up to a common node K3. From there they are connected to the output via a switch S3 of the operational amplifier OP1 connected.
- the first circuit branch points between the nodes K1 and the common node K3 has a resistor R1.
- the second Circuit branch is located between nodes K2 and K3 a resistor R2.
- the node K1 is above an adjustable resistor R0 with the collector terminal of a bipolar transistor T1 of the first circuit branch in connection.
- the basic connection of the bipolar transistor T1 is also with its Collector connection connected while the emitter connection lies on the ground VSS.
- the node K2 is with the collector and the emitter terminal of a bipolar transistor T2 of the second Circuit branch connected.
- the emitter connection of the bipolar transistor T2 is again on the ground VSS.
- the inverting and the non-inverting input of the Operational amplifiers OP1 can be switched via a switch S4 short.
- the constant voltage source shown in Fig. 4 Vdc represents the common mode voltage, which by the mean of the operating voltage potentials is given.
- At the A reference voltage can be output from the operational amplifier OP1 Tap Vref.
- At the connections of the operational amplifier OP1 for offset adjustment is an adjustable one Roffset resistance on.
- Ic1 Collector current of the bipolar transistor T1 Ic2 Collector current of the bipolar transistor T2 Vbe1 Base-emitter voltage of the bipolar transistor T1 be2 Base-emitter voltage of the bipolar transistor T2 VR0 Voltage dropping at the adjustable resistor R0 VR1 Voltage drop across resistor R1 VR2 Voltage drop across resistor R2
- Vref VR2 + Vbe2
- the one falling at a bipolar transistor between the base and emitter Voltage has a temperature dependency.
- To a temperature stabilized To get reference voltage Vref must the base-emitter voltage is a voltage with absolute value same temperature coefficient, but opposite Signs are added. That means that the resistance R2 falling voltage VR2 at a temperature of 300 K have a temperature coefficient of +2 mV / K got to. This temperature dependent voltage is with the help of the bipolar transistor T1 generated.
- Equation (5) represents the voltage VR2.
- Isx stands for the reverse current of the respective bipolar transistor T1 or T2.
- T temperature voltage
- VT k * T / q
- k denotes the Boltzmann constant (1.38 * 10 -23 J / K) and q the elementary charge (1.6 * 10 -19 C).
- the base-emitter voltage shows Vbe2 has a temperature coefficient of -2 mV / K. From equation (7) it follows that the temperature voltage VT has a temperature coefficient of +0.086 mV / K.
- suitable resistors R0, R1 and R2 Summand of the right side of equation (11) designed in this way that it has a temperature coefficient of +2 mV / K.
- the BGR circuit according to the invention creates two tensions, the opposite, but have equal magnitude temperature coefficients. By adding these two tensions one a temperature stabilized reference voltage. by virtue of of inhomogeneities among the same components that are used for the different BGR circuits from the same series are used, there are deviations from the ideal Value of the reference voltage and the ideal temperature behavior the reference voltage.
- the BGR circuit according to the invention allows such inhomogeneities by voltage balancing both the operational amplifier used and the to compensate for built-in resistances.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Description
- Fig. 1A
- ein Schaubild, in welchem die Referenzspannung über der Temperatur aufgetragen ist, zur Erläuterung des Offset-Fehlers;
- Fig. 1B
- ein Schaubild, in welchem die Referenzspannung über der Temperatur aufgetragen ist, zur Erläuterung des Temperaturcharakteristik-Fehlers;
- Fig. 2
- ein Schaubild, in welchem die Referenzspannung über der Temperatur aufgetragen ist, zur Erläuterung der erfindungsgemäßen Kompensation des Offset-Fehlers;
- Fig. 3
- ein Schaubild, in welchem die Referenzspannung über der Temperatur aufgetragen ist, zur Erläuterung der erfindungsgemäßen Kompensation des Temperaturcharakteristik-Fehlers; und
- Fig. 4
- ein Schaltbild eines erfindungsgemäßen BGR-Schaltkreises.
Ic1 | Kollektorstrom des Bipolartransistors T1 |
Ic2 | Kollektorstrom des Bipolartransistors T2 |
Vbe1 | Basis-Emitter-Spannung des Bipolartransistors T1 |
Vbe2 | Basis-Emitter-Spannung des Bipolartransistors T2 |
VR0 | An dem einstellbaren Widerstand R0 abfallende Spannung |
VR1 | An dem Widerstand R1 abfallende Spannung |
VR2 | An dem Widerstand R2 abfallende Spannung |
Claims (12)
- Verfahren zum Abgleichen eines BGR-Schaltkreises zum Erzeugen einer temperaturstabilisierten Referenzspannung (Vref) auf einen vorgegebenen Wert der Referenzspannung, wobei die Schaltung einen Spannungsdifferenzverstärker (OP1) und eine dem Spannungsdifferenzverstärker (OP1) zugeordnete äußere Beschaltung mit mindestens einem Bauelement mit veränderbarem Widerstand (R0) umfaßt, mit den Schritten:(a) Durchführen eines Offset-Abgleichs des Spannungsdifferenzverstärkers (OP1) bei einer vorgegebenen Temperatur (TR); und nachfolgend(b) Durchführen eines Abgleichs der Referenzspannung auf den vorgegebenen Wert der Referenzspannung bei derselben vorgegebenen Temperatur (TR) durch Einstellen des veränderbaren Widerstands (R0) des mindestens einen Bauelements.
- Verfahren nach Anspruch 1,
dadurch gekennzeichnet, daß der Schritt (a) die Teilschritte aufweist:(a1) Kurzschließen der Eingänge des Spannungsdifferenzverstärkers (OP1); und(a2) Regeln der Ausgangsspannung des Spannungsdifferenzverstärkers (OP1) auf einen vorgegebenen Spannungswert. - Verfahren nach Anspruch 2,
dadurch gekennzeichnet,daß der Spannungsdifferenzverstärker (OP1) in Schritt (a2) als Komparator betrieben wird. - Verfahren nach einem der vorhergehenden Ansprüche,
dadurch gekennzeichnet, daß der Schritt (b) die Teilschritte aufweist:(b1) Messen der Referenzspannung (Vref) der Schaltung; und(b2) Verstellen des veränderbaren Widerstands (R0) des mindestens einen Bauelements, bis die gemessene Referenzspannung (Vref) den vorgegebenen Wert der Referenzspannung annimmt. - BGR-Schaltkreis zum Erzeugen einer temperaturstabilisierten Referenzspannung, welcheeinen Spannungsdifferenzverstärker (OP1) mit einem invertierenden und einem nicht-invertierenden Eingang, welchem ein Mittel zur Offset-Korrektur (Roffset) zugeordnet ist, undeine äußere Beschaltung des Spannungsdifferenzverstärkers (OP1), welche mit dem invertierenden und dem nicht-invertierenden Eingang und dem Ausgang des Spannungsdifferenzverstärkers (OP1) in Verbindung steht, umfaßt, wobei die äußere Beschaltungderart aufgebaut ist, daß die Summe mindestens zweier Teilsignale, deren Charakteristiken bezüglich der Temperatur unterschiedliche Vorzeichen aufweisen, der Ausgangsspannung des Spannungsdifferenzverstärkers (OP1) entspricht,mindestens ein Bauelement mit veränderbarem Widerstand (R0) umfaßt, mittels welchem die Temperaturcharakteristik mindestens einer der mindestens zwei Teilsignale beeinflußbar ist, sowieein erstes Schaltmittel (S1, S2) zur Trennung der Eingänge des Spannungsdifferenzverstärkers (OP1) von der äußeren Beschaltung, undein zweites Schaltmittel (S4) zum Kurzschließen der Eingänge des Spannungsdifferenzverstärkers (OP1)
- Schaltung nach Anspruch 5,
dadurch gekennzeichnet,daß'die äußere Beschaltung zwei Schaltungszweige umfaßt, welche sich von einem gemeinsamen festen Potential, insbesondere Masse (VSS), zum Ausgang des Spannungsdifferenzverstärkers (OP1) erstrecken,daß der invertierende Eingang des Spannungsdifferenzverstärkers (OP1) über einen ersten Schalter (S1) des ersten Schaltmittels (S1, S2) an einem Knoten K1 des ersten Schaltungszweigs liegt, unddaß der nicht-invertierende Eingang des Spannungsdifferenzverstärkers (OP1) über einen zweiten Schalter (S2) des ersten Schaltmittels (S1, S2) an einem Knoten K2 des zweiten Schaltungszweigs liegt. - Schaltung nach Anspruch 5 oder 6,
dadurch gekennzeichnet,daß jeder der zwei Schaltungszweige jeweils eine Transistorschaltung (T1, T2) umfaßt. - Schaltung nach einem der Ansprüche 5 bis 7,
dadurch gekennzeichnet,daß die Knoten K1 und K2 jeweils mit dem Ausgang des Spannungsdifferenzverstärkers (OP1) über einen Widerstand (R1, R2) verbunden sind. - Schaltung nach einem der Ansprüche 5 bis 8,
dadurch gekennzeichnet,daß einer der zwei Knoten K1 und K2 über das mindestens eine Bauelement mit veränderbarem Widerstand (R0) mit dem Kollektoranschluß eines ersten Transistors (T1) verbunden ist, dessen Basisanschluß mit seinem Kollektoranschluß verbunden ist und dessen Emitteranschluß auf dem gemeinsamen festen Potential liegt, unddaß der andere der zwei Knoten K1 und K2 mit dem Kollektoranschluß eines zweiten Transistors (T2) verbunden ist, dessen Basisanschluß mit seinem Kollektoranschluß verbunden ist und dessen Emitteranschluß auf dem gemeinsamen festen Potential liegt. - Schaltung nach einem der Ansprüche 5 bis 9,
dadurch gekennzeichnet,daß einer der beiden Eingänge des Spannungsdifferenzverstärkers (OP1) mit einer Konstantspannungsquelle (Vdc) verbindbar ist, unddaß die Schaltung dritte Schaltmittel (S5) zur Trennung dieses Eingangs des Spannungsdifferenzverstärkers (OP1) von der Konstantspannungsquelle (Vdc) aufweist. - Schaltung nach einem der Ansprüche 5 bis 10,
dadurch gekennzeichnet,daß es sich bei dem Spannungsdifferenzverstärker (OP1) um einen Operationsverstärker handelt. - Schaltung nach einem der Ansprüche 5 bis 11,
dadurch gekennzeichnet,daß das Mittel zur Offset-Korrektur (Roffset) ein einstellbarer Trimmwiderstand ist.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10057844A DE10057844A1 (de) | 2000-11-22 | 2000-11-22 | Verfahren zum Abgleichen eines BGR-Schaltkreises und BGR-Schaltkreis |
DE10057844 | 2000-11-22 | ||
PCT/DE2001/004230 WO2002042856A1 (de) | 2000-11-22 | 2001-11-08 | Verfahren zum abgleichen eines bgr-schaltkreises und bgr-schaltkreis |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1336136A1 EP1336136A1 (de) | 2003-08-20 |
EP1336136B1 true EP1336136B1 (de) | 2004-06-16 |
Family
ID=7664183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01997727A Expired - Lifetime EP1336136B1 (de) | 2000-11-22 | 2001-11-08 | Verfahren zum abgleichen eines bgr-schaltkreises und bgr-schaltkreis |
Country Status (6)
Country | Link |
---|---|
US (1) | US6812684B1 (de) |
EP (1) | EP1336136B1 (de) |
JP (1) | JP2004514230A (de) |
CN (1) | CN100464275C (de) |
DE (2) | DE10057844A1 (de) |
WO (1) | WO2002042856A1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7248102B2 (en) * | 2005-01-20 | 2007-07-24 | Infineon Technologies Ag | Internal reference voltage generation for integrated circuit testing |
JP4808069B2 (ja) * | 2006-05-01 | 2011-11-02 | 富士通セミコンダクター株式会社 | 基準電圧発生回路 |
US7710190B2 (en) * | 2006-08-10 | 2010-05-04 | Texas Instruments Incorporated | Apparatus and method for compensating change in a temperature associated with a host device |
US20080106326A1 (en) * | 2006-11-06 | 2008-05-08 | Richard Gaggl | Reference voltage circuit and method for providing a reference voltage |
JP2009217809A (ja) * | 2008-02-12 | 2009-09-24 | Seiko Epson Corp | 基準電圧生成回路、集積回路装置および信号処理装置 |
JP2011130248A (ja) * | 2009-12-18 | 2011-06-30 | Sanyo Electric Co Ltd | 信号処理回路 |
JP5808116B2 (ja) | 2011-02-23 | 2015-11-10 | スパンション エルエルシー | 基準電圧回路および半導体集積回路 |
EP2560066B1 (de) | 2011-08-16 | 2014-12-31 | EM Microelectronic-Marin SA | Verfahren zum Einstellen einer Referenzspannung auf Basis eines Bandgap-Schaltkreises |
CN102393783A (zh) * | 2011-10-19 | 2012-03-28 | 四川和芯微电子股份有限公司 | 具有高阶温度补偿的电流源电路及系统 |
US9362874B2 (en) * | 2013-07-10 | 2016-06-07 | Fairchild Semiconductor Corporation | Differential measurements with a large common mode input voltage |
US9444405B1 (en) | 2015-09-24 | 2016-09-13 | Freescale Semiconductor, Inc. | Methods and structures for dynamically reducing DC offset |
US10013013B1 (en) * | 2017-09-26 | 2018-07-03 | Nxp B.V. | Bandgap voltage reference |
CN110597345B (zh) * | 2019-09-27 | 2021-01-08 | 宜确半导体(苏州)有限公司 | 带隙基准电路及其操作方法 |
CN110992870B (zh) | 2019-12-24 | 2022-03-08 | 昆山国显光电有限公司 | 一种驱动芯片和显示装置 |
US12111676B2 (en) * | 2022-09-19 | 2024-10-08 | Apple Inc. | Bandgap circuit with low power consumption |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4902959A (en) | 1989-06-08 | 1990-02-20 | Analog Devices, Incorporated | Band-gap voltage reference with independently trimmable TC and output |
US5291122A (en) * | 1992-06-11 | 1994-03-01 | Analog Devices, Inc. | Bandgap voltage reference circuit and method with low TCR resistor in parallel with high TCR and in series with low TCR portions of tail resistor |
US5352973A (en) * | 1993-01-13 | 1994-10-04 | Analog Devices, Inc. | Temperature compensation bandgap voltage reference and method |
US5325045A (en) * | 1993-02-17 | 1994-06-28 | Exar Corporation | Low voltage CMOS bandgap with new trimming and curvature correction methods |
US5519354A (en) * | 1995-06-05 | 1996-05-21 | Analog Devices, Inc. | Integrated circuit temperature sensor with a programmable offset |
KR100400383B1 (ko) * | 1996-03-07 | 2003-12-31 | 마츠시타 덴끼 산교 가부시키가이샤 | 기준 전압원 회로 및 전압 피드백 회로 |
DE69621020T2 (de) * | 1996-11-04 | 2002-10-24 | Stmicroelectronics S.R.L., Agrate Brianza | Banddistanzreferenzspannungsgenerator |
DE19735381C1 (de) * | 1997-08-14 | 1999-01-14 | Siemens Ag | Bandgap-Referenzspannungsquelle und Verfahren zum Betreiben derselben |
IT1301803B1 (it) * | 1998-06-25 | 2000-07-07 | St Microelectronics Srl | Circuito regolatore di band-gap per produrre un riferimento ditensione avente una compensazione in temperatura degli effetti di |
US6150871A (en) * | 1999-05-21 | 2000-11-21 | Micrel Incorporated | Low power voltage reference with improved line regulation |
US6198266B1 (en) * | 1999-10-13 | 2001-03-06 | National Semiconductor Corporation | Low dropout voltage reference |
US6201379B1 (en) * | 1999-10-13 | 2001-03-13 | National Semiconductor Corporation | CMOS voltage reference with a nulling amplifier |
-
2000
- 2000-11-22 DE DE10057844A patent/DE10057844A1/de not_active Ceased
-
2001
- 2001-11-08 CN CNB018193781A patent/CN100464275C/zh not_active Expired - Fee Related
- 2001-11-08 DE DE50102636T patent/DE50102636D1/de not_active Expired - Lifetime
- 2001-11-08 EP EP01997727A patent/EP1336136B1/de not_active Expired - Lifetime
- 2001-11-08 WO PCT/DE2001/004230 patent/WO2002042856A1/de active IP Right Grant
- 2001-11-08 JP JP2002545317A patent/JP2004514230A/ja not_active Withdrawn
-
2003
- 2003-05-22 US US10/444,861 patent/US6812684B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1476553A (zh) | 2004-02-18 |
DE10057844A1 (de) | 2002-06-06 |
WO2002042856A1 (de) | 2002-05-30 |
CN100464275C (zh) | 2009-02-25 |
US6812684B1 (en) | 2004-11-02 |
DE50102636D1 (de) | 2004-07-22 |
JP2004514230A (ja) | 2004-05-13 |
EP1336136A1 (de) | 2003-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69516767T2 (de) | Referenzschaltung mit kontrollierter temperaturabhängigkeit | |
DE69519837T2 (de) | Schaltung und Verfahren zur Leckstromkompensation in einer analogen Anordnung | |
EP1336136B1 (de) | Verfahren zum abgleichen eines bgr-schaltkreises und bgr-schaltkreis | |
DE3874974T2 (de) | Cmos-leistungsoperationsverstaerker. | |
EP1704452B1 (de) | Transistoranordnung mit temperaturkompensation und verfahren zur temperaturkompensation | |
DE102010007771B4 (de) | Elektronische Vorrichtung und Verfahren zum Erzeugen einer krümmungskompensierten Bandabstandsreferenzspannung | |
DE10010153B4 (de) | Switched-Capacitor-Referenzstromquelle | |
EP1446884A2 (de) | Temperaturstabilisierter oszillator-schaltkreis | |
EP0789866B1 (de) | Spannungsreferenz mit prüfung und eigenkalibrierung | |
DE102005017538B4 (de) | Anordnung und Verfahren zur Temperaturkompensation eines Widerstands | |
DE102005039335A1 (de) | CMOS-Bandabstandsreferenzschaltkreis | |
DE10066032A1 (de) | Schaltungsanordnung zur Steuerung der Verstärkung einer Verstärkerschaltung | |
DE102019124959A1 (de) | Wärmesensor mit geringem temperaturfehler | |
DE69427471T2 (de) | Transkonduktanzstufe mit gesteuerter Verstärkung | |
DE10224747A1 (de) | Sensorschaltung und Verfahren zur Herstellung derselben | |
DE10220332B4 (de) | Integrierte Schaltungsanordnung mit einem aktiven Filter und Verfahren zum Trimmen eines aktiven Filters | |
DE10047620B4 (de) | Schaltung zum Erzeugen einer Referenzspannung auf einem Halbleiterchip | |
DE102004004305B4 (de) | Bandabstands-Referenzstromquelle | |
DE69305289T2 (de) | Gleichtaktsignalsensor | |
DE4109893A1 (de) | Integrierte schaltungsanordnung mit einem differenzverstaerker | |
DE10237122A1 (de) | Schaltung und Verfahren zur Einstellung des Arbeitspunkts einer BGR-Schaltung | |
EP0952509B1 (de) | Referenzspannungsschaltung | |
DE102007048454B3 (de) | Schaltkreis zur Kompensation von leckstrominduziertem Offset in einem asymmetrischen Operationsverstärker | |
DE69410654T2 (de) | Stromquelle | |
DE4427974C1 (de) | Bipolare kaskadierbare Schaltungsanordnung zur Signalbegrenzung und Feldstärkedetektion |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20030409 |
|
AK | Designated contracting states |
Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: MUELLAUER, MARKUS Inventor name: LEIFHELM, MARTIN |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REF | Corresponds to: |
Ref document number: 50102636 Country of ref document: DE Date of ref document: 20040722 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: GERMAN |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20040816 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20050317 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 15 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 17 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20181120 Year of fee payment: 18 Ref country code: FR Payment date: 20181123 Year of fee payment: 18 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20190121 Year of fee payment: 18 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 50102636 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20191108 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191108 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20200603 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20191130 |