EP1263049A4 - Reseau de cellules memoire a condensateur ferroelectrique, son procede de fabrication, et dispositif a memoire ferroelectrique - Google Patents

Reseau de cellules memoire a condensateur ferroelectrique, son procede de fabrication, et dispositif a memoire ferroelectrique

Info

Publication number
EP1263049A4
EP1263049A4 EP01958382A EP01958382A EP1263049A4 EP 1263049 A4 EP1263049 A4 EP 1263049A4 EP 01958382 A EP01958382 A EP 01958382A EP 01958382 A EP01958382 A EP 01958382A EP 1263049 A4 EP1263049 A4 EP 1263049A4
Authority
EP
European Patent Office
Prior art keywords
ferroelectric
signal electrode
cell array
memory cell
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01958382A
Other languages
German (de)
English (en)
Other versions
EP1263049A1 (fr
Inventor
Eiji Natori
Kazumasa Hasegawa
Koichi Oguchi
Takao Nishikawa
Tatsuya Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of EP1263049A1 publication Critical patent/EP1263049A1/fr
Publication of EP1263049A4 publication Critical patent/EP1263049A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un réseau de cellules mémoire comprenant une couche ferroélectrique constituant un condensateur ferroélectrique comportant un motif spécifique, et dont la capacité parasite d'une électrode de signal est faible, un procédé de fabrication de ce réseau de cellules mémoire, ainsi qu'un dispositif à mémoire ferroélectrique. Le réseau de cellules mémoire (100A) est composé de cellules mémoire consistant chacune d'elles en un condensateur ferroélectrique (20), disposées en matrice. Le condensateur ferroélectrique (20) comprend une première électrode de signal (12), une seconde électrode de signal (16) perpendiculaire par rapport à la première électrode de signal (12), ainsi qu'une couche ferroélectrique (14) disposée linéairement le long de la première électrode de signal (12) ou de la seconde électrode de signal (16). La couche ferroélectrique (14) peut être disposée de façon alternée dans un bloc, uniquement aux points d'intersection entre la première électrode de signal (12) et la seconde électrode de signal (16).
EP01958382A 2000-08-22 2001-08-21 Reseau de cellules memoire a condensateur ferroelectrique, son procede de fabrication, et dispositif a memoire ferroelectrique Withdrawn EP1263049A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000251436A JP3901432B2 (ja) 2000-08-22 2000-08-22 強誘電体キャパシタを有するメモリセルアレイおよびその製造方法
JP2000251436 2000-08-22
PCT/JP2001/007143 WO2002017403A1 (fr) 2000-08-22 2001-08-21 Reseau de cellules memoire a condensateur ferroelectrique, son procede de fabrication, et dispositif a memoire ferroelectrique

Publications (2)

Publication Number Publication Date
EP1263049A1 EP1263049A1 (fr) 2002-12-04
EP1263049A4 true EP1263049A4 (fr) 2005-08-31

Family

ID=18740844

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01958382A Withdrawn EP1263049A4 (fr) 2000-08-22 2001-08-21 Reseau de cellules memoire a condensateur ferroelectrique, son procede de fabrication, et dispositif a memoire ferroelectrique

Country Status (5)

Country Link
US (2) US6617627B2 (fr)
EP (1) EP1263049A4 (fr)
JP (1) JP3901432B2 (fr)
CN (1) CN1246905C (fr)
WO (1) WO2002017403A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3901432B2 (ja) * 2000-08-22 2007-04-04 セイコーエプソン株式会社 強誘電体キャパシタを有するメモリセルアレイおよびその製造方法
US6858482B2 (en) * 2002-04-10 2005-02-22 Micron Technology, Inc. Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US20070166838A1 (en) * 2003-12-22 2007-07-19 Koninklijke Philips Electronics N.V. Method for patterning a ferroelectric polymer layer
US20050156217A1 (en) * 2004-01-13 2005-07-21 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and method for fabricating the same
JP2005285190A (ja) * 2004-03-29 2005-10-13 Sanyo Electric Co Ltd メモリ
JP2005327919A (ja) * 2004-05-14 2005-11-24 Seiko Epson Corp デバイスの製造方法及びデバイス、電気光学素子、プリンタ
US7253502B2 (en) * 2004-07-28 2007-08-07 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same
DE102005017071B4 (de) 2004-12-29 2011-09-15 Hynix Semiconductor Inc. Schwebe-Gate-Speichereinrichtung
NO322202B1 (no) * 2004-12-30 2006-08-28 Thin Film Electronics Asa Fremgangsmate i fremstillingen av en elektronisk innretning
NO324539B1 (no) * 2005-06-14 2007-11-19 Thin Film Electronics Asa Fremgangsmate i fabrikasjonen av en ferroelektrisk minneinnretning
GB2436893A (en) * 2006-03-31 2007-10-10 Seiko Epson Corp Inkjet printing of cross point passive matrix devices
GB0809840D0 (en) * 2008-05-30 2008-07-09 Univ Catholique Louvain Ferroelectric organic memories with ultra-low voltage operation
US8357582B2 (en) 2010-11-01 2013-01-22 Micron Technology, Inc. Methods of forming electrical components and memory cells
TWI463641B (zh) * 2012-02-24 2014-12-01 Nat Applied Res Laboratories Ultra - high density resistive memory structure and its manufacturing method
DE102020108366A1 (de) 2020-03-26 2021-09-30 Bayerische Motoren Werke Aktiengesellschaft Informationsspeicher und Verfahren zum Programmieren und Auslesen von Informationen

Citations (6)

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Publication number Priority date Publication date Assignee Title
JPH08255879A (ja) * 1995-03-15 1996-10-01 Sony Corp 半導体メモリ及びその作製方法
JPH09102587A (ja) * 1995-10-05 1997-04-15 Olympus Optical Co Ltd 強誘電体薄膜素子
JPH09249972A (ja) * 1996-03-15 1997-09-22 Fujitsu Ltd 薄膜形成方法、半導体装置及びその製造方法
US5874364A (en) * 1995-03-27 1999-02-23 Fujitsu Limited Thin film deposition method, capacitor device and method for fabricating the same, and semiconductor device and method for fabricating the same
US6077716A (en) * 1996-10-31 2000-06-20 Samsung Electronics Co., Ltd. Matrix type multiple numeration system ferroelectric random access memory using leakage current
US6617627B2 (en) * 2000-08-22 2003-09-09 Seiko Epson Corporation Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device.

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2788265B2 (ja) 1988-07-08 1998-08-20 オリンパス光学工業株式会社 強誘電体メモリ及びその駆動方法，製造方法
US5530667A (en) * 1991-03-01 1996-06-25 Olympus Optical Co., Ltd. Ferroelectric memory device
WO1997007429A1 (fr) * 1995-08-18 1997-02-27 President And Fellows Of Harvard College Application de motifs sur des surfaces concernant des couches monomoleculaires auto-assemblees
JPH0991970A (ja) 1995-09-26 1997-04-04 Olympus Optical Co Ltd 非破壊型強誘電体メモリ及びその駆動方法
US6163043A (en) * 1996-04-19 2000-12-19 Matsushita Electronics Corp. Semiconductor device
KR100370416B1 (ko) 1996-10-31 2003-04-08 삼성전기주식회사 고밀도 데이터의 기록/재생을 위한 부호화/복호화 방법 및 그에 따른 장치
NO309500B1 (no) 1997-08-15 2001-02-05 Thin Film Electronics Asa Ferroelektrisk databehandlingsinnretning, fremgangsmåter til dens fremstilling og utlesing, samt bruk av samme
US6316801B1 (en) * 1998-03-04 2001-11-13 Nec Corporation Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same
US5963466A (en) * 1998-04-13 1999-10-05 Radiant Technologies, Inc. Ferroelectric memory having a common plate electrode
US6239028B1 (en) * 1998-09-03 2001-05-29 Micron Technology, Inc. Methods for forming iridium-containing films on substrates
US6174735B1 (en) * 1998-10-23 2001-01-16 Ramtron International Corporation Method of manufacturing ferroelectric memory device useful for preventing hydrogen line degradation
DE60042811D1 (de) * 1999-06-04 2009-10-08 Seiko Epson Corp Herstellungsverfahren für eine ferroelektrische Speichervorrichtung

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255879A (ja) * 1995-03-15 1996-10-01 Sony Corp 半導体メモリ及びその作製方法
US5874364A (en) * 1995-03-27 1999-02-23 Fujitsu Limited Thin film deposition method, capacitor device and method for fabricating the same, and semiconductor device and method for fabricating the same
JPH09102587A (ja) * 1995-10-05 1997-04-15 Olympus Optical Co Ltd 強誘電体薄膜素子
JPH09249972A (ja) * 1996-03-15 1997-09-22 Fujitsu Ltd 薄膜形成方法、半導体装置及びその製造方法
US6077716A (en) * 1996-10-31 2000-06-20 Samsung Electronics Co., Ltd. Matrix type multiple numeration system ferroelectric random access memory using leakage current
US6617627B2 (en) * 2000-08-22 2003-09-09 Seiko Epson Corporation Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device.
US6913937B2 (en) * 2000-08-22 2005-07-05 Seiko Epson Corporation Memory cell array having ferroelectric capacity, method of manufacturing the same and ferroelectric memory device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
OKAMURA S. ET AL.: "Fabrication of Ferroelectric Microcapacitors with Self-Aligned Top Electrodes by Electron-Beam-Induced Patterning Process", JPN. J. APPL. PHYS., vol. 41,Pt.1, no. 11B, November 2002 (2002-11-01), pages 6754 - 6757 *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 02 28 February 1997 (1997-02-28) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 07 31 March 1999 (1999-03-31) *
See also references of WO0217403A1 *

Also Published As

Publication number Publication date
US20020031005A1 (en) 2002-03-14
JP3901432B2 (ja) 2007-04-04
CN1388990A (zh) 2003-01-01
JP2002064187A (ja) 2002-02-28
EP1263049A1 (fr) 2002-12-04
CN1246905C (zh) 2006-03-22
US20040014247A1 (en) 2004-01-22
US6913937B2 (en) 2005-07-05
US6617627B2 (en) 2003-09-09
WO2002017403A1 (fr) 2002-02-28

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