EP1251522A3 - Dispositif de mémoire à semiconducteurs - Google Patents
Dispositif de mémoire à semiconducteurs Download PDFInfo
- Publication number
- EP1251522A3 EP1251522A3 EP02250447A EP02250447A EP1251522A3 EP 1251522 A3 EP1251522 A3 EP 1251522A3 EP 02250447 A EP02250447 A EP 02250447A EP 02250447 A EP02250447 A EP 02250447A EP 1251522 A3 EP1251522 A3 EP 1251522A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- data
- circuit
- parity
- reading
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001119439A JP4782302B2 (ja) | 2001-04-18 | 2001-04-18 | 半導体記憶装置 |
JP2001119439 | 2001-04-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1251522A2 EP1251522A2 (fr) | 2002-10-23 |
EP1251522A3 true EP1251522A3 (fr) | 2004-03-17 |
Family
ID=18969658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02250447A Withdrawn EP1251522A3 (fr) | 2001-04-18 | 2002-01-23 | Dispositif de mémoire à semiconducteurs |
Country Status (6)
Country | Link |
---|---|
US (1) | US6922750B2 (fr) |
EP (1) | EP1251522A3 (fr) |
JP (1) | JP4782302B2 (fr) |
KR (1) | KR100823013B1 (fr) |
CN (1) | CN1381847B (fr) |
TW (1) | TW546657B (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005017914A1 (fr) * | 2003-08-18 | 2005-02-24 | Fujitsu Limited | Memoire a semi-conducteurs et procede de fonctionnement de memoire a semi-conducteurs |
KR100511047B1 (ko) | 2003-12-08 | 2005-08-30 | 삼성전자주식회사 | 반도체 메모리 테스트 방법 및 이를 수행하기 위한 장치,테스트용 반도체 메모리 |
JP4569182B2 (ja) * | 2004-03-19 | 2010-10-27 | ソニー株式会社 | 半導体装置 |
EP1945724A2 (fr) * | 2005-11-08 | 2008-07-23 | Laxmi C. Gupta | Procédés permettant d'appliquer des systèmes retardateurs de flamme, compositions et utilisations |
KR100852191B1 (ko) * | 2007-02-16 | 2008-08-13 | 삼성전자주식회사 | 에러 정정 기능을 가지는 반도체 메모리 장치 및 에러 정정방법 |
KR101094402B1 (ko) | 2009-12-29 | 2011-12-15 | 주식회사 하이닉스반도체 | 반도체 장치 및 반도체 장치를 포함하는 반도체 시스템 |
CN102420017A (zh) * | 2011-09-28 | 2012-04-18 | 上海宏力半导体制造有限公司 | 检测存储器记忆能力的方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4766573A (en) * | 1986-03-18 | 1988-08-23 | Fujitsu Limited | Semiconductor memory device with error correcting circuit |
US5297102A (en) * | 1991-11-27 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device storing data and parity bit |
US6108229A (en) * | 1996-05-24 | 2000-08-22 | Shau; Jeng-Jye | High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62120699A (ja) * | 1985-11-20 | 1987-06-01 | Fujitsu Ltd | 半導体記憶装置 |
JPH01200455A (ja) * | 1988-02-05 | 1989-08-11 | Sharp Corp | パリティ機能を有する半導体記憶装置に於けるパリティ機能テスト方法 |
JPH0440697A (ja) * | 1990-06-06 | 1992-02-12 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JPH04132093A (ja) * | 1990-09-21 | 1992-05-06 | Toshiba Corp | 半導体記憶装置 |
JP2830730B2 (ja) * | 1994-02-28 | 1998-12-02 | 日本電気株式会社 | ダイナミックメモリ |
EP0955640A3 (fr) * | 1998-03-30 | 2000-01-19 | Siemens Aktiengesellschaft | Mode de rafraichissement automatique décodé pour DRAM |
JP3938842B2 (ja) * | 2000-12-04 | 2007-06-27 | 富士通株式会社 | 半導体記憶装置 |
JP4001724B2 (ja) * | 2001-03-29 | 2007-10-31 | 富士通株式会社 | 半導体記憶装置 |
-
2001
- 2001-04-18 JP JP2001119439A patent/JP4782302B2/ja not_active Expired - Fee Related
-
2002
- 2002-01-17 TW TW091100657A patent/TW546657B/zh not_active IP Right Cessation
- 2002-01-17 US US10/046,754 patent/US6922750B2/en not_active Expired - Fee Related
- 2002-01-23 EP EP02250447A patent/EP1251522A3/fr not_active Withdrawn
- 2002-02-07 CN CN021035644A patent/CN1381847B/zh not_active Expired - Fee Related
- 2002-02-07 KR KR1020020007134A patent/KR100823013B1/ko not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4766573A (en) * | 1986-03-18 | 1988-08-23 | Fujitsu Limited | Semiconductor memory device with error correcting circuit |
US5297102A (en) * | 1991-11-27 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device storing data and parity bit |
US6108229A (en) * | 1996-05-24 | 2000-08-22 | Shau; Jeng-Jye | High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
Also Published As
Publication number | Publication date |
---|---|
JP2002313077A (ja) | 2002-10-25 |
JP4782302B2 (ja) | 2011-09-28 |
US6922750B2 (en) | 2005-07-26 |
US20020156967A1 (en) | 2002-10-24 |
KR100823013B1 (ko) | 2008-04-17 |
CN1381847B (zh) | 2010-05-12 |
EP1251522A2 (fr) | 2002-10-23 |
TW546657B (en) | 2003-08-11 |
KR20030010465A (ko) | 2003-02-05 |
CN1381847A (zh) | 2002-11-27 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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AK | Designated contracting states |
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PUAL | Search report despatched |
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Extension state: AL LT LV MK RO SI |
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17P | Request for examination filed |
Effective date: 20040913 |
|
AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: FUJITSU MICROELECTRONICS LIMITED |
|
17Q | First examination report despatched |
Effective date: 20091215 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: FUJITSU SEMICONDUCTOR LIMITED |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SOCIONEXT INC. |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20151007 |